JP4983378B2 - Semiconductor memory device, operating method thereof, control method thereof, memory system and memory control method - Google Patents

Description

  The present invention relates to a semiconductor memory device having a low power consumption mode.

  Recently, mobile phones have come to have a function of transmitting character data or image data as well as a function of having a conversation by voice. Furthermore, the mobile phone is expected to become a kind of information terminal (portable personal computer) due to the diversification of Internet services in the future. In this way, the amount of information of data handled by mobile phones tends to increase significantly. Conventionally, cellular phones use SRAM having a storage capacity of about 4 Mbits as work memory. The work memory is a memory for holding data necessary during operation of the mobile phone. It is clear that the storage capacity of the work memory will be insufficient in the future.

  In addition, the communication speed of mobile phones tends to improve. As mobile phones become smaller, the built-in battery tends to be smaller. Therefore, the work memory used in the mobile phone must be high speed, low power consumption and large capacity. In addition, it is necessary to reduce the parts cost as much as possible in a mobile phone where price competition is intense. For this reason, the work memory must be inexpensive.

Conventionally, SRAM used for work memory has a higher bit unit price than DRAM. In addition, the price is unlikely to drop because the production volume is small. Furthermore, a product with a large storage capacity (for example, 64 Mbit) has not been developed.
JP-A-7-169267

  Under such circumstances, use of flash memory or DRAM as work memory for mobile phones is being considered instead of SRAM.

  Flash memory consumes as little as several microwatts during standby. On the other hand, a data write operation requires several μs to several tens of μs. For this reason, when a flash memory is used as a work memory of a mobile phone, it is difficult to transmit and receive a large amount of data at high speed. In addition, since the flash memory performs a writing operation in units of sectors, it is not suitable for applications in which image data is rewritten little by little, such as moving image data.

  On the other hand, the DRAM can execute both read and write operations in several tens of ns. Moving image data can also be handled easily. On the other hand, power consumption during standby is greater than that of flash memory. In the current DRAM, the power consumption during standby is about 1 mW in the self-refresh mode that holds the written data, and about 300 μW in the standby mode that does not need to hold the written data.

  If the power consumption in the standby mode can be reduced to a flash memory level, it can be used as a work memory for a mobile phone, but such circuit technology has not been proposed.

  Note that the power consumption of the DRAM can be reduced to zero by stopping the supply of power to the DRAM. However, because the DRAM address terminals, data terminals, etc. are also connected to the terminals of other electronic components via wiring patterns on the circuit board, the power supply to the DRAM can be stopped by Significant system change (circuit board pattern change, re-layout, etc.) is required.

  Further, no technology has been proposed for canceling the standby mode without causing the internal circuit to malfunction after stopping the supply of power in the standby mode and stopping the internal circuit.

  Further, when the internal voltage used in the internal circuit is generated inside the device, the internal voltage must be quickly returned to a predetermined voltage when the standby mode (low power consumption mode) is released. However, such a technique has not been proposed.

  An object of the present invention is to surely shift a semiconductor memory device to a low power consumption mode and reliably release the semiconductor memory device from the low power consumption mode.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device and a control method therefor that can significantly reduce the current consumption during standby compared to the prior art.

  Another object of the present invention is to easily put a chip into a low power consumption mode by an external control signal.

  Another object of the present invention is to prevent a through current (leakage path) of an internal circuit in the low power consumption mode.

  Yet another object of the present invention is to easily put a chip into a low power consumption mode using an existing control signal.

  Another object of the present invention is to easily put a chip into a low power consumption mode by inputting a command.

  Another object of the present invention is to easily put a chip into a low power consumption mode by a dedicated control signal.

  Another object of the present invention is to perform high-speed recovery from the low power consumption mode.

  In the present invention, the internal voltage generation circuit generates an internal voltage to be supplied to a predetermined internal circuit when activated. During the operation of the internal voltage generation circuit, predetermined power is consumed. The entry circuit deactivates the internal voltage generation circuit in response to an external control signal. Due to the inactivation of the internal voltage generation circuit, the internal voltage is not generated and the power consumption is reduced. Therefore, the chip can be easily and reliably put into the low power consumption mode by the control signal from the outside.

  In the present invention, the external voltage supply circuit supplies the power supply voltage as an internal voltage to the internal circuit in the low power consumption mode. Therefore, when the internal voltage generation circuit is inactivated, a predetermined power supply voltage is supplied to the power supply terminal of each internal circuit. As a result, each element of the internal circuit is fixed in a predetermined state, and a leak path is prevented from occurring. That is, the through current is prevented from flowing.

  In the present invention, a predetermined internal circuit is deactivated when a reset signal is supplied from the outside. When receiving the reset signal, the entry circuit shifts the chip to the low power consumption mode. At reset, there is no need to operate the chip. For this reason, it is possible to shift to the low power consumption mode using an existing signal. Since the types and the number of external terminals are the same as the conventional one, the usability is not lowered by adding the low power consumption mode.

  In the present invention, the entry circuit receives a plurality of control signals from the outside. When the entry circuit recognizes that the state of the control signal is a low power consumption command, the entry circuit shifts the chip to the low power consumption mode. For this reason, the chip can be shifted to the low power consumption mode by command input.

  In the present invention, the entry circuit shifts the chip to the low power consumption mode when receiving a predetermined level or transition edge of the low power consumption mode signal from the outside. For this reason, it is possible to reliably shift the chip to the low power consumption mode by using a dedicated signal.

  In the present invention, the low power consumption mode is canceled when the state of the control signal received during the low power consumption mode requires the cancellation of the low power consumption mode. Therefore, the chip can be easily released from the low power consumption mode by an external control signal. The cancellation of the low power consumption mode is performed, for example, by controlling the entry circuit.

  In the present invention, when the low power consumption mode is released, a reset signal for initializing the internal circuit is activated for a period during which the internal voltage is lower than a predetermined voltage. For example, the reset signal is activated during a period when the internal voltage is lower than the reference voltage generated by stepping down the power supply voltage. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented.

  In the present invention, when the low power consumption mode is released, a reset signal for initializing the internal circuit is activated for a period in which the internally generated boosted voltage is lower than a predetermined voltage. For example, the reset signal is activated while the boosted voltage is lower than the power supply voltage. Further, the reset signal may be activated during a period in which the boosted voltage is lower than the reference voltage generated by stepping down the power supply voltage.

  In the present invention, when the low power consumption mode is released, the reset signal for initializing the internal circuit is activated while the timer is measuring a predetermined time. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented.

  In the present invention, the self-refresh control circuit automatically refreshes the memory cells at a predetermined cycle. The internal voltage generation circuit receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit. When receiving a control signal from the outside, the semiconductor memory device deactivates the self-refresh control circuit, lowers the supply capability of the internal voltage of the internal voltage generation circuit, and shifts to the low power consumption mode. When it is not necessary to retain the contents of the memory cell during the low power consumption mode, the operation of the self-refresh control circuit is unnecessary. Since the refresh is not executed, the internal voltage generation circuit may be operated with an ability sufficient to compensate for the power (leakage current) consumed by the internal circuit. As a result, the power consumption during the low power consumption mode can be reduced.

  The internal voltage is supplied to the internal circuit even during the low power consumption mode. For this reason, the internal circuit can operate immediately after the release of the low power consumption mode.

  In the present invention, the stabilizing capacitor connected to the power supply line stores a part of the electric charge supplied to the power supply line. When receiving a control signal from the outside, the semiconductor memory device maintains the connection between the power supply line and the stabilization capacitor, cuts off the connection between the power supply line and the internal circuit, and shifts to the low power consumption mode. For this reason, the power consumption of the internal circuit can be made zero during the low power consumption mode. When the power supply line and the internal circuit are connected after the low power consumption mode is released, a voltage corresponding to the charge stored in the stabilizing capacitor is applied to the internal circuit via the power supply line. As a result, the internal circuit can operate immediately after the release of the low power consumption mode.

  In the present invention, the internal voltage generation circuit receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit. The internal voltage detection circuit detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result. When receiving a control signal from the outside, the semiconductor memory device reduces the current consumption of the internal voltage detection circuit and shifts to the low power consumption mode. If the current consumption is reduced, the response of the internal voltage detection circuit becomes dull, but the problem does not occur because the internal circuit of the chip is not operating.

  In the present invention, the internal voltage generation circuit receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit. The internal voltage detection circuit detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result. The semiconductor memory device reduces the absolute value of the internal voltage generated by the internal voltage generation circuit by reducing the detection level of the internal voltage in the internal voltage detection circuit when receiving a control signal from the outside, thereby reducing the power consumption. Enter mode. For this reason, it is possible to reduce the leakage current of the transistors and the like in the internal circuit and reduce the power consumption.

  In the present invention, the internal voltage generation circuit generates an internal voltage to be supplied to a predetermined internal circuit when activated. During the operation of the internal voltage generation circuit, predetermined power is consumed. The internal voltage generation circuit is deactivated in response to an external control signal. Due to the inactivation of the internal voltage generation circuit, the internal voltage is not generated and the power consumption is reduced. Therefore, the chip can be easily put into the low power consumption mode by an external control signal.

  In the present invention, when a plurality of control signals are received from the outside and it is recognized that the state of the control signal is a low power consumption command, the chip is shifted to the low power consumption mode. For this reason, the chip can be shifted to the low power consumption mode by command input.

  In the present invention, the chip can be easily put into the low power consumption mode by an external control signal. In the low power consumption mode, the internal voltage generation circuit is stopped, so that the current consumption can be greatly reduced. In the present invention, since each element of the internal circuit is fixed in a predetermined state, generation of a through current can be prevented.

  In the present invention, an existing signal can be used to shift to the low power consumption mode. Therefore, usability is not reduced by adding the low power consumption mode. In the present invention, the chip can be shifted to the low power consumption mode by command input.

  In the present invention, it is possible to reliably shift the chip to the low power consumption mode by using the dedicated signal for shifting to the low power consumption mode. In the present invention, the chip can be easily released from the low power consumption mode by an external control signal.

  In the present invention, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented. In the present invention, since the supply capability is lowered rather than stopping the supply of the internal voltage supplied to the internal circuit during the low power consumption mode, the internal circuit can be operated immediately after the release of the low power consumption mode.

  In the present invention, the power consumption of the internal circuit can be made zero during the low power consumption mode, and the internal circuit can be operated immediately after the low power consumption mode is released. In the present invention, the current consumption of the internal voltage detection circuit can be reduced during the low power consumption mode, and the power consumption can be reduced.

  In the present invention, the level of the internal voltage is lowered during the low power consumption mode. As a result, the leakage current of the transistors in the internal circuit can be lowered, and the power consumption can be reduced. In the present invention, the chip can be easily put into the low power consumption mode by an external control signal. In the low power consumption mode, since the internal voltage generating circuit is stopped, the power consumption can be greatly reduced. In the present invention, the chip can be shifted to the low power consumption mode by command input.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a state transition diagram of the semiconductor memory device of the present invention. First, the semiconductor memory device enters an idle mode upon power-on. When a read command or a write command is received during the idle mode, the operation mode is shifted to and a read operation or a write operation is executed. After executing the read operation or the write operation, the mode automatically returns to the idle mode. When a self-refresh command is received during the idle mode, the mode is shifted to the self-refresh mode and self-refresh is executed. Here, in the self-refresh mode, the refresh address is automatically generated, and the refresh operation of the memory cells is sequentially executed.

  Further, the semiconductor memory device detects the state of a predetermined signal during the idle mode and shifts to the low power consumption mode. In the first embodiment to be described later, the chip enable signal CE2 is received to shift to the low power consumption mode. In other words, the chip enable signal CE2 has a reset function for deactivating a predetermined internal circuit and a function for shifting the chip to the low power consumption mode. In the second embodiment, a command input by the chip enable signals / CE1 and CE2 is received, and the mode is shifted to the low power consumption mode. In the third embodiment, in response to the dedicated low power consumption mode signal / LP, the mode is shifted to the low power consumption mode. The semiconductor memory device detects the state of a predetermined signal during the low power consumption mode and cancels the low power consumption mode.

  FIG. 2 shows the basic principle of the semiconductor memory device of the present invention. The semiconductor memory device has an entry circuit 1, an internal voltage generation circuit 2, an external voltage supply circuit 3, and an internal circuit 4.

  The internal voltage generation circuit 2 generates an internal voltage in each mode after power-on, and supplies the internal voltage to the internal circuit 4. The entry circuit 1 receives the control signal and deactivates the internal voltage generation circuit 2 when detecting a predetermined state of the control signal. Due to the inactivation of the internal voltage generation circuit 2, the generation of the internal voltage is stopped. At the same time, the entry circuit 1 activates the external voltage supply circuit 3. The external voltage supply circuit 3 supplies the power supply voltage as an internal voltage to the internal circuit. Then, the semiconductor memory device shifts to a low power consumption mode.

  FIG. 3 shows a first embodiment of the semiconductor memory device, the operation method thereof, the control method thereof, the memory system and the memory control method of the present invention. The semiconductor memory device of this embodiment is formed as a DRAM on a p-type silicon substrate using CMOS process technology.

  The DRAM includes a VII activation circuit 10, a VDD activation circuit 12, a low power entry circuit 14, a command decoder 16, an internal voltage generation circuit 18, and a chip body 20. The internal voltage generation circuit 18 includes a low-pass filter 22, a reference voltage generation circuit 24, a VDD supply circuit 26, a booster circuit 28, a precharge voltage generation circuit 30, an internal power supply voltage generation circuit 32, a substrate voltage generation circuit 34, and a VSS supply circuit. 36. The chip body 20 has a memory core 38 and a peripheral circuit 40. Here, the low power entry circuit 14 corresponds to the entry circuit 1 shown in FIG. 2, and the VDD supply circuit 26 and the VSS supply circuit 36 correspond to the external voltage supply circuit 3 shown in FIG.

  The DRAM has an external power supply voltage VDD (for example, 2.5 V), a ground voltage VSS, chip enable signals / CE1 and CE2 as control signals, a plurality of address signals AD, a data input / output signal DQ, and other control signals CN. Have been supplied. Since this DRAM does not employ the address multiplex method, the address signal AD is supplied once for each read operation and each write operation. The power supply voltage VDD and the ground voltage VSS are supplied to almost all circuits except for some circuits of the memory core 38. A signal having “/” in front of the signal name is a negative logic signal. In the following description, the “address signal AD” may be abbreviated as “AD signal”.

  The / CE1 signal is a signal that is set to a low level when executing a read operation, a write operation, etc., and activates the DRAM. The CE2 signal functions as a reset signal and deactivates a predetermined internal circuit of the chip body 20 when it is at a low level.

  The VII activation circuit 10 receives the internal power supply voltage VII and the ground voltage VSS and outputs the activation signal STTVII to the chip body 20. The VII starter circuit 10 is a circuit for resetting the chip body 20 and preventing its malfunction until the internal power supply voltage VII reaches a predetermined voltage after power-on. The VDD startup circuit 12 receives the power supply voltage VDD and the ground voltage VSS and outputs a startup signal STTCRX. The VDD activation circuit 12 is a circuit for deactivating the low power entry circuit 14 until the power supply voltage VDD becomes a predetermined voltage after power-on, and preventing the malfunction.

  The low power entry circuit 14 is a circuit that receives the activation signals STTCRX and the CE2 signal and activates the low power signal ULP.

  The command decoder 16 receives the / CE1 signal and the other control signal CN, decodes the command, and outputs the decoded command to the peripheral circuit 40 as an internal command signal.

  The low-pass filter 22 has a function of receiving the power supply voltage VDD and removing noise contained therein. The power supply voltage VDD from which noise has been removed is supplied to the reference voltage generation circuit 24 and the like. In the low power consumption mode, the switch in the low pass filter 22 is turned off, the power supply voltage VDD is not supplied to the reference voltage generation circuit 24, and current consumption is eliminated.

  The reference voltage generation circuit 24 receives the power supply voltage VDD and generates a reference voltage VPREF (for example, 1.5 V), VPRREFL (for example, 0.8 V), VPRREFH (for example, 1.2 V), and VRFV (for example, 2.0 V).

  The VDD supply circuit 26 is a circuit for setting the boost voltage VPP and the internal power supply voltage VII to the power supply voltage VDD in the low power consumption mode.

  The booster circuit 28 receives the reference voltage VPREF, generates a boost voltage VPP (eg, 3.7 V), and supplies it to the memory core 38. The precharge voltage generation circuit 30 receives the reference voltage VPRREFL and the reference voltage VPRREFH and generates a precharge voltage VPR (for example, 1.0 V) to be supplied to the memory core 38. The internal power supply voltage generation circuit 32 receives the reference voltage VRFV and generates an internal power supply voltage VII (for example, 2.0 V) to be supplied to the memory core 38 and the peripheral circuit 40.

  The substrate voltage generation circuit 34 receives the reference voltage VRFV and generates a substrate voltage VBB (for example, −1.0 V) for supplying the substrate and the p well of the memory cell. The VSS supply circuit 36 is a circuit for setting the precharge voltage VPR and the substrate voltage VBB to the ground voltage VSS in the low power consumption mode.

  FIG. 4 shows details of the booster circuit 28 and the precharge voltage generation circuit 30. The booster circuit 28 includes resistors R1 and R2, which are connected in series, a differential amplifier 28a, a pump circuit 28b, an nMOS 28c, and a switch circuit 28d that controls the gate of the nMOS 28c. The boost voltage VPP is supplied to one end of the resistor R1, and the ground voltage VSS is supplied to one end of the resistor R2 via the nMOS 28c. A divided voltage V1 is generated from the connection node of the resistors R1 and R2. The nMOS 28c receives the power supply voltage VDD from the switch circuit 28d in the low power consumption mode. The differential amplifier 28a is formed by, for example, a MOS differential amplifier circuit using a current mirror circuit as a current source. The differential amplifier 28a outputs a high level when the voltage V1 is lower than the reference voltage VPREF. The pump circuit 28b receives the high level from the differential amplifier 28a and starts the pumping operation. By this pumping operation, VPP rises and voltage V1 rises. When the voltage V1 coincides with the reference voltage VPREF (that is, 1.5V), the output of the differential amplifier 28a becomes low level and the pumping operation is stopped. By repeating this operation, the boost voltage VPP is held at a constant voltage.

  The precharge voltage generation circuit 30 includes two differential amplifiers 30a and 30b whose outputs are connected to each other. A reference potential VPRREFL and a precharge voltage VPR are supplied to the differential amplifier 30a. A reference potential VPRREFH and a precharge voltage VPR are supplied to the differential amplifier 30b. The differential amplifiers 30a and 30b generate a precharge voltage VPR having an intermediate value between the reference voltages VPRREFL and VPRREFH.

  FIG. 5 shows details of the internal power supply voltage generation circuit 32 and the substrate voltage generation circuit 34. The internal power supply voltage generation circuit 32 includes a negative feedback differential amplifier 32a, a compensation circuit 32b, a regulator 32c made of nMOS, an nMOS 32d, and a switch circuit 32e for controlling the gate of the nMOS. The differential amplifier 32a is a circuit that receives the reference voltage VRFV and the voltage V2 generated by the compensation circuit 32b and applies a predetermined voltage to the node VG. In the compensation circuit 32b, a diode-connected nMOS and resistors R3 and R4 are arranged in series between the node VG and the ground VSS. The voltage V2 is a voltage generated at the connection node of the resistors R3 and R4. In the regulator 32c, the gate is connected to the node VG, the drain receives the power supply voltage VDD, and the source generates the internal power supply voltage VII.

  The nMOS 32d has a source grounded and a drain connected to the node VG. The switch circuit 32e is a circuit that applies the power supply voltage VDD to the gate of the nMOS 32d in the low power consumption mode. The nMOS 32d receives the power supply voltage VDD from the switch circuit 32e in the low power consumption mode, and fixes the node VG to the ground level.

  In the internal power supply voltage generation circuit 32, for example, when the threshold value of the regulator 32c decreases due to an increase in the ambient temperature, the threshold value of the nMOS of the compensation circuit 32b decreases, so the voltage V2 increases. The differential amplifier 32a decreases the voltage at the node VG in response to the increase in the voltage V2. Then, the source-drain current of the nMOS 32c is made constant, and the internal power supply voltage VII becomes constant.

  The substrate voltage generation circuit 34 includes an oscillation circuit 34a and a pumping circuit 34b. The oscillation circuit 34a is a circuit that receives the high level of the control signal VBBEN, starts an oscillation operation, and outputs an oscillation signal OSC. The pumping circuit 34b includes a capacitor that receives an oscillation signal OSC from the oscillation circuit 34a and repeats charge and discharge, and an nMOS transistor that is connected to one end of the capacitor and is diode-connected. The substrate voltage VBB is lowered by extracting the charge of the p-type substrate connected to the anode by a pumping operation. By making the substrate voltage VBB negative, it is possible to obtain an effect such that the influence of the variation of the threshold value of the memory cell due to the substrate effect is reduced, and the characteristics of the memory cell are improved.

  FIG. 6 shows details of the main part of the memory core 38. The memory core 38 includes a memory cell MC, nMOS switches 42a and 42b, a precharge circuit 44, and a sense amplifier 46. The memory cell MC is composed of an nMOS for data transfer and a capacitor. A word line WL0 (or WL1) is connected to the gate of the nMOS. The nMOS switches 42a and 42b control connection between the bit line BL (or / BL) on the memory cell MC side and the bit line BL (or / BL) on the sense amplifier SA side. A control signal BT is supplied to the gates of the nMOS switches 42a and 42b.

  The precharge circuit 44 includes three nMOSs 44a, 44b, and 44c. The source and drain of the nMOS 44a are connected to the bit lines BL and / BL, respectively. One of the source and drain of the nMOSs 44b and 44c is connected to the bit lines BL and / BL, respectively, and the other is supplied with a precharge voltage VPR. A bit line control signal BRS is supplied to the gates of the nMOSs 44a, 44b and 44c.

  The sense amplifier 46 is configured by connecting the inputs and outputs of two CMOS inverters to each other. The output of each CMOS inverter is connected to the bit lines / BL and BL, respectively. The pMOS source and nMOS source of each CMOS inverter are connected to power supply lines PSA and NSA, respectively. Each power supply line PSA, NSA is at the VPR level during standby and when the sense amplifier is inactive, and changes to the internal power supply voltage VII and the ground voltage VSS when the bit line is amplified.

  FIG. 7 shows operations of power-on, transition to the low power consumption mode (entry), and release from the low power consumption mode (exit) of the semiconductor memory device described above. First, the power supply voltage VDD gradually rises upon power-on (FIG. 7 (a)). The VDD activation circuit 12 shown in FIG. 3 deactivates the activation signal STTCRX (low level) until the power supply voltage VDD becomes a predetermined voltage (FIG. 7 (b)). This control prevents the ULP signal from being activated due to the low power entry circuit 14 malfunctioning at power-on. An external controller (CPU, memory controller, etc.) that controls the DRAM sets the CE2 signal to a high level after a predetermined period T0 after the power supply voltage VDD becomes the operation guarantee voltage VDDmin. (FIG. 7 (c)).

  Thereafter, the DRAM enters a standby state or performs a normal operation. When the external controller shifts the DRAM to the low power consumption mode, the CE2 signal is set to a low level (FIG. 7 (d)). The low power entry circuit 14 receives the falling edge of the CE2 signal when the STTCRX signal is at a high level, and activates the ULP signal (high level) (FIG. 7 (e)).

  The low pass filter 22 of the internal voltage generation circuit 18 receives the high level of the ULP signal, stops the supply of the power supply voltage VDD to the reference voltage generation circuit 24, and supplies the ground voltage VSS from the VSS supply circuit 36 instead. . The reference voltage generation circuit 24 receives the ground voltage VSS and sets the reference voltages VPREF, VPRREFL, VPRREFH, and VRFV to the ground level. The nMOS 28c of the booster circuit 28 shown in FIG. 4 and the nMOS 32d of the internal power supply voltage generating circuit 32 shown in FIG. 5 are turned off. As a result, booster circuit 28, precharge voltage generation circuit 30, internal power supply voltage generation circuit 32, and substrate voltage generation circuit 34 are deactivated and stop operating. For this reason, in the low power consumption mode, all the circuits that have been operated conventionally are stopped. Therefore, the power consumption in the low power consumption mode is greatly reduced compared to the conventional case.

  Due to the inactivation of these circuits, generation of the boost voltage VPP, the precharge voltage VPR, the internal power supply voltage VII, and the substrate voltage VBB is stopped. However, boost voltage VPP and internal power supply voltage VII become power supply voltage VDD by VDD supply circuit 26, and substrate voltage VBB and precharge voltage VPR become ground voltage VSS by VSS supply circuit 36. Therefore, a leak path is prevented from occurring in the internal circuit of the chip body 20.

  When canceling the low power consumption mode, the external controller sets the CE2 signal to a high level (FIG. 7 (f)). In response to the high level of the CE2 signal, the low power entry circuit 14 deactivates the ULP signal (low level) (FIG. 7 (g)). The low-pass filter 22 receives the inactivation of the ULP signal and supplies the power supply voltage VDD to the reference voltage generation circuit 24. The VDD supply circuit 26 and the VSS supply circuit 36 stop supplying the power supply voltage VDD and the ground voltage VSS in response to the inactivation of the ULP signal. Then, booster circuit 28, precharge voltage generation circuit 30, internal power supply voltage generation circuit 32, and substrate voltage generation circuit 34 are activated again and start operation. Here, the DRAM enters the idle mode after time T1 from the high level of the CE2 signal. Time T1 is a time until each internal voltage VPP, VPR, VII, VBB is stabilized to a predetermined voltage.

  FIG. 8 shows an example in which the semiconductor memory device of the first embodiment is used for a mobile phone. This mobile phone has the DRAM, CPU, and flash memory of this embodiment mounted on a circuit board. The CPU controls reading and writing of data with respect to the DRAM and the flash memory. The DRAM is used as a work memory, and the flash memory is used as a backup memory when the mobile phone is off and in a standby state.

  FIG. 9 shows a use state of the mobile phone shown in FIG. In this example, when the mobile phone is in a waiting state, the DRAM is in a low power consumption mode under the control of the CPU. At this time, the power consumption of the DRAM is approximately the same as the power consumption of the flash memory during standby.

  Thereafter, when the mobile phone changes from the standby state to the talking state, the CPU sets the CE2 signal shown in FIG. 8 to a high level. After the DRAM enters the idle mode, the data held in the flash memory is transferred to the DRAM (FIG. 9 (a)). During a call, DRAM is used as work memory. Here, the call state includes data transmission.

  When the call state is changed to the waiting state, necessary data to be held among the DRAM data is saved in the flash memory (FIG. 9B). After that, the CPU changes the CE2 signal to a low level and shifts the DRAM to the low power consumption mode. Since DRAM does not perform a refresh operation in the low power consumption mode, unnecessary data is lost. When the power is turned off, necessary data is held in the flash memory.

  As described above, by applying the DRAM of the first embodiment to the work memory of the mobile phone, the power consumption in the standby state of the mobile phone is greatly reduced. The DRAM and flash memory may be controlled using a dedicated memory controller or the like instead of the CPU. The data transfer is not limited to switching between the waiting state and the call state, and may be performed as necessary during the call. Furthermore, the data backup memory is not limited to the flash memory, and may be an SRAM. Data may be saved in a server such as a mobile phone base station.

  FIG. 10 is a flowchart showing a control state of the mobile phone shown in FIG. First, in step S1, the transition to the low power consumption mode is prevented when the power is turned on. Specifically, as shown in FIG. 7, malfunction is prevented by the activation timing of the STTCRX signal of the VDD starting circuit 12.

  Next, in step S2, the CPU changes the CE2 signal to a low level and causes the DRAM to shift to the low power consumption mode. In step S3, the mobile phone enters a waiting state. Next, in step S4, the CPU detects whether the power is turned off. When the power is turned off, the control ends. When the power is not turned off, control proceeds to step S5.

  In step S5, the CPU repeats the wait state until it enters a call state. If a call is entered, control is transferred to step S6. In step S6, the CPU sets the CE2 signal to a high level and causes the DRAM to shift from the low power consumption mode to the idle mode. Then, each power supply circuit 28, 30, 32, 34 shown in FIG. 3 is restarted.

  Next, in step S7, the CPU transfers (returns) the data held in the flash memory (Flash) to the DRAM. Next, in step S8, a call or data transmission is performed.

  In step S9, the CPU detects whether or not it has entered a wait state. When it does not enter the waiting state, the control proceeds to step S7 again. When it enters the waiting state, the control proceeds to step S10. In step S10, the CPU transfers (saves) the data that needs to be held among the DRAM data to the flash memory. Control is then transferred again to step S2, and the mobile phone is again in a waiting state. DRAM goes into a low power consumption mode.

  As described above, in the semiconductor memory device and the control method thereof according to the present invention, the operations of the booster circuit 28, the precharge voltage generation circuit 30, the internal power supply voltage generation circuit 32, and the substrate voltage generation circuit 34 are stopped in the low power consumption mode. For this reason, the power consumption at the time of a low power consumption mode can be reduced significantly compared with the past. In the low power consumption mode, the boost voltage VPP, the internal power supply voltage VII, the substrate voltage VBB, and the precharge voltage VPR are set to the power supply voltage VDD and the ground voltage VSS, respectively. For this reason, it is possible to prevent a leak path from occurring in the internal circuit of the chip body 20 and to reduce power consumption.

  The DRAM was shifted to the low power consumption mode using the existing CE2 signal. For this reason, the kind and number of external terminals can be made the same as in the past. Thus, users using DRAM do not need to make significant circuit board changes by adding a low power consumption mode. At power-on, the VDD startup circuit 12 inactivates the startup signal STTCRX (low level) until the power supply voltage VDD becomes a predetermined voltage. For this reason, it is possible to prevent the low power entry circuit 14 from malfunctioning when the power is turned on and the ULP signal is activated, so that the DRAM shifts to the low power consumption mode.

  At power-on, the CE2 signal is set to a high level after a predetermined period T0 after the power supply voltage VDD becomes the guaranteed operating voltage VDDmin. For this reason, it is possible to prevent erroneous shift to the low power consumption mode at the time of power-on. Therefore, by applying the DRAM of the present invention to the work memory of a mobile phone, the power consumption in the waiting state of the mobile phone can be greatly reduced. Moreover, malfunction can be prevented.

  FIG. 11 shows a second embodiment of the semiconductor memory device, its operation method, and its control method according to the present invention. Note that the same reference numerals are given to the same circuits as those described in the first embodiment, and detailed description thereof will be omitted.

  In this embodiment, the low power entry circuit 50 is supplied with the / CE1 signal and the CE2 signal. The command decoder 52 is supplied with the / CE1 signal, the CE2 signal, and other control signals CN. Other configurations are the same as those of the first embodiment described above.

  FIG. 12 shows details of the low power entry circuit 50. The low power entry circuit 50 includes timing adjustment circuits 54 a and 54 b, a level shifter 56, an RS flip-flop 58, and a combinational circuit 60.

  The timing adjustment circuit 54a is formed by cascading a two-input NOR gate having a delay circuit 54c connected to one input and a two-input NAND gate having a delay circuit 54c connected to one input. In each delay circuit 54c, a MOS capacitor is arranged between an even number of inverters connected in cascade. The timing adjustment circuit 54a has a function of delaying the falling edge of the chip enable signal CE2Z by about 100 ns and outputting it to the node ND1. The CE2Z signal is a signal obtained by receiving an externally supplied CE2 signal with an input buffer (not shown). The timing adjustment circuit 54b is the same circuit as the timing adjustment circuit 54a. The timing adjustment circuit 54b has a function of delaying the falling edge of the signal transmitted to the node ND3 by about 100 ns.

  The level shifter 56 has two sets of pMOS and nMOS connected in series. Each nMOS gate receives an inverted signal of the row address strobe signal RASX and an in-phase signal. An internal power supply voltage VII and a ground voltage VSS are supplied to an inverter that generates an inverted signal of the RASX signal and an in-phase signal. The RASX signal is a control signal that goes low when the word line is activated. The pMOS gate is connected to the drain of the opposing pMOS, and the nMOS drain (output node) that receives the positive logic of the RASX signal at the gate is connected to the RS flip-flop 58. A power supply voltage VDD is supplied to the source of each pMOS, and a ground voltage VSS is supplied to the source of each nMOS.

  The RS flip-flop 58 is composed of two 2-input NOR gates. The activation signal STTCRX is supplied to one input corresponding to the output node ND2, and the output signal of the level shifter 56 is supplied to the other input.

  The combinational circuit 60 is a circuit that lowers the output node ND3 in response to the low levels of the nodes ND1 and ND2 and the chip enable signal CE1X. The CE1X signal is a signal obtained by receiving the / CE1 signal supplied from the outside with an input buffer (not shown), and is a negative logic signal. The timing adjustment circuit 54b activates the ULP signal (high level) via the inverter after about 100 ns in response to the low level of the node ND3.

  FIG. 13 shows the operation of the low power entry circuit 50. First, at power-on, the STTCRX signal goes low, and the voltage of the / CE1 signal rises following the power supply voltage VDD. By doing so, malfunction is prevented.

  STTCRX goes high after a predetermined time from power-on (FIG. 13 (a)). Thereafter, the external controller that controls the DRAM sets the CE2 signal to a high level (FIG. 13B). The timing so far is the same as in the first embodiment. Due to the high level of the CE2Z signal, the node ND1 shown in FIG. 12 becomes high level (FIG. 13 (c)).

  Thereafter, an initial cycle is executed, and the RASX signal becomes low level (FIG. 13 (d)). In response to the low level of the RASX signal, the RS flip-flop 58 sets the node ND2 to the high level (FIG. 13 (e)). Thereafter, the operation of the internal voltage generation circuit 18 shown in FIG. 11 is started.

  Next, an entry command for shifting to the low power consumption mode is supplied. In this embodiment, the DRAM shifts to the low power consumption mode by setting the / CE1 signal to a low level after a predetermined time after setting the CE2 signal to a low level.

  The timing adjustment circuit 54a receives the low level of the CE2Z signal and sets the node ND1 to the low level after about 100 ns (FIG. 13 (f)). The CE1X signal is set to the low level after 100 ns or more from the falling edge of the CE2Z signal (FIG. 13 (g)). In response to the low level of the CE1Z signal and the low level of the node ND1, the combinational circuit 60 shown in FIG. 12 sets the node ND3 to low level (FIG. 13 (h)). The timing adjustment circuit 54b receives the low level of the node ND3, and after about 100 ns, sets the ULP signal to the high level via the inverter (FIG. 13 (i)). Then, the DRAM enters a low power consumption mode.

  As described above, the DRAM shifts to the low power consumption mode in response to the command input. At this time, the power supply voltage VDD is supplied to the inverter of the level shifter 56 shown in FIG. 12 instead of the internal power supply voltage VII. Therefore, the level shifter 56 prevents the occurrence of a leak path by surely turning off the nMOS gate.

  When canceling from the low power consumption mode, the CE1X signal is first set to a high level (FIG. 13 (j)). The combinational circuit 60 receives the high level of CE1X, the node ND3 becomes high level (FIG. 13 (k)), and the ULP signal becomes low level (FIG. 13 (l)). The CE2Z signal is set to the high level 200 μs after the rising edge of the CE1X signal (FIG. 13 (m)). Since the CE2Z signal is high, the node ND1 becomes high. The internal voltage generation circuit 18 is activated during the period of 200 μs, and the internal voltages VPP, VPR, VII, and VBB are stabilized at a predetermined voltage.

  The activation operation and the deactivation operation of the internal voltage generation circuit 18 are performed in the same manner as in the first embodiment. That is, the control of each circuit in the present embodiment is the same as that in the first embodiment except that entry and exit in the low power consumption mode are performed by command input.

  Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Further, in this embodiment, the DRAM can be shifted to the low power consumption mode and the low power consumption mode can be released by command input using the / CE1 signal and the CE2 signal.

  FIG. 14 shows a third embodiment of the semiconductor memory device, its operation method, and its control method according to the present invention. The same circuits as those described in the first and second embodiments are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In this embodiment, the low power entry mode 62 is supplied with the low power consumption mode signal / LP. The low power consumption mode signal / LP is a dedicated signal for shifting the DRAM to the low power consumption mode. The low power entry circuit 62 detects the falling edge of the / LP signal and shifts the DRAM to the low power consumption mode. The command decoder 52 is supplied with the / CE1 signal, the CE2 signal, and other control signals CN. Other configurations are the same as those of the first embodiment described above.

  The operation timing at the time of exiting and entering the low power consumption mode of the DRAM of this embodiment is the same as when the CE2 signal is replaced with the / LP signal in the timing diagram shown in FIG. Also in this embodiment, the same effect as that of the first embodiment described above can be obtained. Furthermore, in this embodiment, the DRAM can be reliably switched to or released from the low power consumption mode by the dedicated low power consumption mode signal / LP.

  FIG. 15 and FIG. 16 show the VII starter circuit in the fourth embodiment of the semiconductor memory device, its operating method and its control method of the present invention. Note that the same reference numerals are given to the same circuits as those described in the first embodiment, and detailed description thereof will be omitted.

  In this embodiment, a VII starting circuit 70 is formed instead of the VII starting circuit 10 of FIG. 3 (first embodiment). Other configurations are the same as those in FIG. That is, as shown in FIG. 7, the DRAM of this embodiment shifts to the low power consumption mode by changing the CE2 signal to a low level during the high level period of the / CE1 signal, and enters the low power consumption mode. Then, the low power consumption mode is canceled by changing the CE2 signal to a high level.

  The VII activation circuit 70 has a release detection circuit 72 shown in FIG. 15, and a level detection circuit 74 and a power-on circuit 76 shown in FIG. 15 and 16, the logic circuit is supplied with the power supply voltage VDD except for the power supply voltage.

  The cancellation detection circuit 72 includes a detection circuit 72a, a level shifter 72b, and a flip-flop 72c. The detection circuit 72a receives the low power signal ULP shown in FIG. 3, and outputs a low-level pulse LPLS in synchronization with the falling edge of the ULP signal. The level shifter 72b converts the high level voltage (internal power supply voltage VII) of the row address strobe signal RASZ into the external power supply voltage VDD, and outputs a row address strobe signal RASX1 whose logic is inverted. The level shifter 72b is the same circuit as the level shifter 56 shown in FIG. The flip-flop 72c sets the release signal REL to a high level when receiving a low pulse from the detection circuit 72a, and sets the release signal REL to a low level when receiving a low level (RASZ = high level) from the level shifter 72b. .

  In FIG. 16, the level detection circuit 74 has a differential amplifier circuit 74a including a current mirror circuit and an inverter row 74b including an odd number of inverters and receiving the output of the differential amplifier circuit 74a. The differential amplifier circuit 74a is activated when the release signal REL is at a high level, compares the internal power supply voltage VII with the reference voltage VREF, and outputs the comparison result to the inverter row 74b. Here, the generation circuit of the internal power supply voltage VII generates the internal power supply voltage VII having a constant value without depending on the fluctuation of the power supply voltage VDD supplied from the outside. On the other hand, the reference voltage VREF changes depending on the power supply voltage VDD.

  The output voltage from the differential amplifier circuit 74a is low when the internal power supply voltage VII is lower than the reference voltage VREF. The differential amplifier circuit 74a has a MOS capacitor 74c that receives the reference voltage VREF in order to prevent the differential amplifier circuit 74a from responding to slight fluctuations in the reference voltage VREF. In addition, an nMOS 74d receiving the reference voltage VREF is disposed in the path to the ground line in order to limit the current flowing through the ground line and reduce power consumption during the operation of the differential amplifier circuit 74a. The nMOS 74d acts as a high resistance. The first stage inverter 74e of the inverter row 74b has nMOSs connected in series in order to match the logical threshold value of the input signal to the output of the differential amplifier circuit 74a.

  The power-on circuit 76 sets the activation signal STT to a high level for a predetermined period after the power supply voltage is supplied to the DRAM. The OR circuit 78 outputs a high level start signal STTVII (reset signal) when receiving a high level start signal STTPZ or a high level STT. The activation signal STTVII is supplied to the chip body 20 as in FIG. 3, and initializes a predetermined internal circuit.

  FIG. 17 shows operations of transition (entry) of the DRAM to the low power consumption mode described above and release (exit) from the low power consumption mode. First, when the CE2 signal is set to a low level, the DRAM shifts to the low power consumption mode by the low power entry circuit 14 shown in FIG. 3, and the generation circuit of the internal power supply voltage VII stops its operation. The internal power supply voltage VII (eg, 2.0 V during normal operation) becomes the power supply voltage VDD (eg, 2.5 V) (FIG. 17 (a)), and the ULP signal becomes high (FIG. 17 (b)).

  Thereafter, when the CE2 signal (not shown) is set to the high level, the DRAM is released from the low power consumption mode, and the ULP signal is set to the low level (FIG. 17 (c)). That is, the DRAM is released from the low power consumption mode according to the state of the CE2 signal received during the low power consumption mode. The cancellation of the low power consumption mode is performed under the control of the low power entry circuit 14 shown in FIG.

  The detection circuit 72a in FIG. 15 changes the LPLS signal to a low level (pulse) in response to the falling edge of the ULP signal (FIG. 17 (d)). The flip-flop 72c of FIG. 15 receives the low level LPLS signal and sets the REL signal to the high level (FIG. 17 (e)).

  On the other hand, the release from the low power consumption mode releases the connection between the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD, and at the same time, the generation circuit of the internal power supply voltage VII starts operation. The internal power supply voltage VII decreases for a while after the generation circuit starts operating (FIG. 17 (f)). The differential amplifier circuit 74a of FIG. 16 outputs a low level to the inverter row 74b when the internal power supply voltage VII is lower than a reference voltage VREF (for example, 1.25 V). The inverter train 74b receives the low level from the differential amplifier circuit 74a and outputs a high level STTPZ signal (FIG. 17 (g)). The OR circuit 78 receives the high level STTPZ signal and sets the activation signal STTVII to the high level. The activation signal STTVII acts as a reset signal, and a predetermined internal circuit of the chip body 20 shown in FIG. 3 is initialized.

  After releasing from the low power consumption mode, the operation command is supplied to the DRAM, so that the RASZ signal is set to the high level (FIG. 17 (h)) and the REL signal is set to the low level (FIG. 17 (i)). ). Due to the low level of the REL signal, the differential amplifier circuit 74a is inactivated. In this way, when the internal power supply voltage VII is lower than the predetermined voltage (reference voltage VREF) and the operation of the internal circuit to which the internal power supply voltage VII is supplied cannot be guaranteed, the internal circuit is initialized to reduce the consumption. When the power mode is released, the malfunction of the internal circuit is prevented.

  As described above, in this embodiment, the low power consumption mode is canceled when the state of the CE2 signal received during the low power consumption mode requires the low power consumption mode to be canceled. Therefore, the chip can be easily released from the low power consumption mode by an external control signal. When the low power consumption mode is released, the activation signal STTVII, which is a reset signal for initializing the internal circuit, is activated while the internal power supply voltage VII is lower than the reference voltage VREF. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented. With only one control signal (CE2 signal), the chip can be shifted to the low power consumption mode and the chip can be released from the low power consumption mode.

  FIG. 18 shows a level detection circuit 80 according to the fifth embodiment of the semiconductor memory device, its operation method and its control method of the present invention. Note that the same reference numerals are given to the same circuits as those described in the first and fourth embodiments, and detailed description thereof will be omitted. In this embodiment, a level detection circuit 80 is formed instead of the level detection circuit 74 of the fourth embodiment described above. The other configuration is the same as that of the fourth embodiment.

  The level detection circuit 80 includes a differential amplifier circuit 80a that compares the internal power supply voltage VII and the reference voltage VREF, an inverter row 80b including an even number of inverters, a boosted voltage VPP of a word line (not shown), and an external voltage A differential amplifier circuit 80c for comparing the power supply voltage VDD, an inverter array 80d including an even number of inverters, and a NAND gate 80e are provided. The boosted voltage VPP is generated by a booster circuit formed inside the chip. The differential amplifier circuits 80a and 80c are the same as the differential amplifier circuit 74a of FIG. 16, and are activated upon receiving a high level REL signal. Inverter trains 80b and 80d are composed of the first-stage inverter and the next-stage inverter of the inverter train 74b of FIG. The inverter row 80b receives the output of the differential amplifier circuit 80a and outputs the received logic level to the NAND gate 80e as the activation signal STT1X. The inverter array 80d receives the output of the differential amplifier circuit 80c, and outputs the received logic level to the NAND gate 80e as the activation signal STT2X. The NAND gate 80e operates as a negative logic OR circuit and outputs a start signal STTPZ.

  FIG. 19 shows operations of transition (entry) to the low power consumption mode of the above-described DRAM and release (exit) from the low power consumption mode. First, when the CE2 signal is set to a low level and the DRAM shifts to the low power consumption mode, the generation circuit for the internal power supply voltage VII and the generation circuit for the boost voltage VPP stop operating. The internal power supply voltage VII (eg, 2.0 V during normal operation) and the boosted voltage VPP (eg, 3.7 V during normal operation) become the power supply voltage VDD (eg, 2.5 V) (FIG. 19A). The ULP signal becomes high level (FIG. 19 (b)).

  Thereafter, when the CE2 signal is set to the high level, the DRAM is released from the low power consumption mode, and the ULP signal is set to the low level (FIG. 19 (c)). As in FIG. 17, the LPLS signal is set to a low level (pulse) (FIG. 19 (d)), and the REL signal is set to a high level (FIG. 19 (e)).

  On the other hand, by releasing from the low power consumption mode, the connection between the power supply line of the internal power supply voltage VII and the power supply line of the power supply voltage VDD is released, and the generation circuit of the internal power supply voltage VII starts operating. The internal power supply voltage VII decreases for a while after the generation circuit starts operating (FIG. 19 (f)). While the internal power supply voltage VII is lower than the reference voltage VREF (for example, 1.25 V), the low-level STT1X signal is output (FIG. 19 (g)). Similarly, the connection between the power supply line of the boost voltage VPP and the power supply line of the power supply voltage VDD is released, and the generation circuit of the boost voltage VPP starts operation. The boosted voltage VPP decreases for a while after the generation circuit starts operating (FIG. 19 (h)). While the boosted voltage VPP is lower than the power supply voltage VDD, a low level STT2X signal is output (FIG. 19 (i)).

  The NAND gate 80e in FIG. 18 outputs a high level STTPZ signal while the STT1X signal or the STT2X signal is at a low level (FIG. 19 (j)). During the period when the STTPZ signal is at a high level, the activation signal STTVII (FIG. 16) is set at a high level. The activation signal STTVII acts as a reset signal and initializes a predetermined internal circuit of the chip body 20 shown in FIG.

  As the DRAM operates after the release from the low power consumption mode, the RASZ signal is set to the high level (FIG. 19 (k)) and the REL signal is set to the low level (FIG. 19 (l)). )). Due to the low level of the REL signal, the differential amplifier circuits 80a and 80c are inactivated.

  Also in this embodiment, the same effect as that of the above-described fourth embodiment can be obtained. Further, in this embodiment, when the low power consumption mode is released, the activation signal STTVII for initializing the internal circuit is activated for a period in which the internally generated boosted voltage VPP is lower than the external power supply voltage VDD. More specifically, when the low power consumption mode is released, the internal circuit is initialized while at least one of the internal power supply voltage VII and the internally generated boosted voltage VPP is lower than the reference voltage VREF and the power supply voltage VDD, respectively. The activation signal STTVII for activated. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be reset more reliably, and malfunction of the internal circuit can be prevented.

  FIG. 20 shows a start signal generation circuit in a sixth embodiment of the semiconductor memory device, the operation method thereof and the control method thereof according to the present invention. Note that the same reference numerals are given to the same circuits as those described in the first and fourth embodiments, and detailed description thereof will be omitted. In the DRAM of this embodiment, an activation signal generation circuit 82 is formed instead of the release detection circuit 72 and the level detection circuit 72 of the fourth embodiment. Other configurations are the same as those in FIG. 3 (first embodiment).

  The start signal generation circuit 82 receives a CMOS inverter 82a that receives a CE2X signal (internal signal) that is an inverted signal of the CE2 signal, a MOS capacitor 82b that is connected to the output of the CMOS inverter, an output of the CMOS inverter, and a reference voltage VREF. And a differential amplifier circuit 82c. The differential amplifier circuit 82c has a current mirror circuit, and sets the activation signal STTPZ to a high level when the voltage at the node ND4 is lower than the reference voltage VREF.

  The pMOS of the CMOS inverter 82a has a long channel length and a high on-resistance. A CR time constant circuit is configured by the pMOS and the MOS capacitor 82b of the CMOS inverter 82a. By configuring the CR time constant circuit using the on-resistance of the transistor, the layout area can be reduced as compared with the case where the diffusion resistance is used.

  FIG. 21 shows operations of the transition (entry) of the DRAM to the low power consumption mode and the release (exit) from the low power consumption mode. First, when the CE2 signal is set to the low level, the CE2X signal is set to the high level, and the DRAM shifts to the low power consumption mode. The internal power supply voltage VII generation circuit and the boost voltage VPP generation circuit stop operating. The CMOS inverter 82a of FIG. 20 receives the high level CE2X signal, turns on the nMOS, and lowers the node ND4 (FIG. 21 (a)). The differential amplifier circuit 82c sets the STTPZ signal to a high level when the voltage at the node ND4 is lower than the reference voltage VREF (FIG. 21 (b)).

  Thereafter, when the / CE2 signal is set to the high level and the CE2X signal is set to the low level, the DRAM is released from the low power consumption mode (FIG. 21 (c)). The CMOS inverter 82 of FIG. 20 receives the low level CE2X signal, turns on the pMOS, and sets the node ND4 to the high level (FIG. 21 (d)). At this time, the voltage of the node ND4 gradually increases according to the time constant due to the on-resistance of the pMOS and the CMOS capacitance. The differential amplifier circuit 82c sets the STTPZ signal to a low level when the voltage at the node ND4 becomes higher than the reference voltage VREF (FIG. 21 (e)).

  As a result, during the period T2 from the cancellation of the low power consumption mode, the STTPZ signal (reset signal) is activated (high level), and the internal circuit is initialized. The period T2 is set corresponding to a period in which the internal power supply voltage VII is lower than a predetermined voltage and the operation of the internal circuit to which the internal power supply voltage VII is supplied cannot be guaranteed after the low power consumption mode is released. That is, the activation signal generation circuit 82 operates as a timer that generates the period T2.

  Also in this embodiment, the same effect as that of the above-described fourth embodiment can be obtained. Further, in this embodiment, when the low power consumption mode is released, the start signal generation circuit 82 is operated as a timer to generate the STTPZ signal, and the internal circuit is initialized for a period T2 after the low power consumption mode is released. . For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented.

  Since the activation signal generation circuit 82 is operated as a CR time constant circuit, the period T2 can be set based on the propagation delay time of the signal propagated to the CR time constant circuit. For this reason, the reset period of the internal circuit can be set with a simple circuit. Since the CR time constant circuit is formed using the on-resistance of the pMOS, the layout area of the activation signal generation circuit 82 can be reduced.

  FIG. 22 shows a seventh embodiment of the semiconductor memory device, its operation method, and its control method according to the present invention. Note that the same reference numerals are given to the same circuits as those described in the first embodiment, and detailed description thereof will be omitted.

  In this embodiment, the DRAM includes a VII activation circuit 10, a VDD activation circuit 12, a low power entry circuit 84, a command decoder 16, an internal voltage generation circuit 86, and a chip body 88. The internal voltage generation circuit 86 includes a low-pass filter 22, a reference voltage generation circuit 24, a VPP detection circuit 90, a booster circuit 92, a precharge voltage generation circuit 94, an internal power supply voltage generation circuit 96, a VBB detection circuit 98, and a substrate voltage generation circuit. 100. The chip body 88 includes a memory core 38, a peripheral circuit 40, a frequency dividing circuit 102, and an oscillation circuit 104. The frequency dividing circuit 102 and the oscillation circuit 104 are control circuits that generate a timing signal for automatically executing a refresh operation in the self-refresh mode.

  FIG. 23 shows details of the reference voltage generation circuit 24. The reference voltage generation circuit 24 includes a reference voltage generation circuit 24a that generates a reference voltage VREF, a starter circuit 24b made of pMOS, a differential amplifier 24c, and a regulator 24d.

  The reference voltage generating circuit 24a has a current mirror circuit composed of pMOS, two nMOSs connected in series with the current mirror circuit, and a resistor connected between the source of one nMOS and the ground line VSS. is doing. The output of the reference voltage generation circuit 24a is connected to the gate of one nMOS and the drain of the other nMOS, and a reference voltage VREF is generated from this node. The gate of the other nMOS is connected to the source of one nMOS.

  The starter circuit 24b sets the reference voltage VREF to a high level during the period when the activation signal STTCRX is activated after power-on. The differential amplifier 24c has a current mirror unit composed of pMOS, a differential input unit composed of nMOS, and an nMOS that is supplied with a reference voltage VREF at its gate and connects the differential input unit to the ground line VSS. ing. A reference voltage VREF is supplied to one nMOS gate of the differential input section, and a reference voltage VRFV is supplied to the other nMOS gate.

  The regulator 24d is configured by connecting a pMOS and five resistors in series between a power supply line VDD and a ground line VSS. Reference voltages VRFV, VPREF, VPRREFL, and VPRREFH are output from connection nodes of the respective elements. The source and drain of the nMOS controlled by the low power signal NAPX are connected to both ends of the resistor connected to the ground line VSS. The resistor connected to the ground line VSS is bypassed when the low power signal NAPX is activated (low level). For this reason, the levels of the reference voltages VRFV, VPREF, VPRREFL, and VPRREFH are lowered during the low power consumption mode.

  FIG. 24 shows details of the internal power supply voltage generation circuit 96. The internal power supply voltage generation circuit 96 deletes the switch circuit 32e and the nMOS 32d from the VII internal power supply voltage generation circuit 32 of the first embodiment shown in FIG. 5, and adds a stabilization capacitor 96a, a switch 96b, and an nMOS 96c. Is formed. The stabilization capacitor 96a stores a part of the electric charge supplied to the internal power supply line VII, and reduces the fluctuation of the power supply voltage VII due to power supply noise or the like. The switch 96b is formed of, for example, a CMOS transmission gate. The inversion logic of the low power signal NAPX is input to the gate of the nMOS 96c arranged between the internal power supply line VII and the ground line VSS via an inverter.

  The switch 96b is turned off when the low power signal NAPX is activated, and disconnects the connection between the regulator 32c and the internal circuit. At this time, the nMOS 96c is turned on, and the internal power supply line VII becomes the ground voltage (0 V). Since the power supply voltage VII is not supplied to the internal circuit, no leakage current is generated in the transistors of the internal circuit during the low power consumption mode. That is, the power consumption of the internal circuit can be reduced to zero. At this time, the connection between the regulator 32c and the stabilization capacitor 96a is maintained, and the stabilization capacitor 96a can store charges in the same manner as during normal operation.

  After the low power consumption mode is released, the low power signal NAPX is deactivated, so that the switch 96b is turned on, and at the same time, the nMOS 96c is turned off, and the regulator 32c and the internal circuit are connected. At this time, in addition to the charge supplied from the regulator 32c, the charge stored in the stabilizing capacitor is supplied to the internal power supply line VII, and the internal power supply voltage VII is increased and supplied to the internal circuit. As a result, the internal circuit can operate immediately after the release of the low power consumption mode.

  FIG. 25 shows a booster circuit 92, a VPP detection circuit 90, a substrate voltage generation circuit 100, and a VBB detection circuit 98.

  The booster circuit 92 includes an oscillation circuit 106 that operates by activation of the boost enable signal VPPEN, and a plurality of units 108 and 110. The unit 108 receives the pulse signals PLS1 to PLS6 from the oscillation circuit 106, and generates a boost voltage VPP when the low power signal NAPX is activated. The unit 110 always generates the boost voltage VPP when receiving the pulse signals PLS1 to PLS6 from the oscillation circuit 106 regardless of the low power signal NAPX. When the unit 108 stops operating based on the activation of the low power signal NAPX, the power consumption of the booster circuit 92 is reduced in the low power consumption mode. As will be described later, since the refresh operation is not executed during the low power consumption mode, there is no problem even if the driving capability of the booster circuit 92 is reduced. The number of units 110 that are always operated regardless of the operation mode is determined according to the time (product specification) until the normal operation or the refresh operation is executed after returning from the low power consumption mode.

  The substrate voltage generation circuit 100 includes a plurality of units 112 that operate by activating the substrate voltage detection signal VBBDET and a deactivation of the low power signal NAPX, and a plurality of units 114 that operate by activating the substrate voltage detection signal VBBDET. is doing. When the unit 112 stops operating based on the activation of the low power signal NAPX, the power consumption of the substrate voltage generation circuit 100 is reduced during the low power consumption mode. The number of units 114 that are always operated regardless of the operation mode is determined according to the time (product specification) until the normal operation or the refresh operation is executed after returning from the low power consumption mode.

  FIG. 26 shows details of the unit 108 of the booster circuit 92. The unit 108 includes four capacitors 108a, 108b, 108c, and 108d made of nMOS, and pMOSs 108e and 108f that operate as switches. One ends of the capacitors 108a, 108b, 108c, and 108d receive the inverted logic of the pulse signals PLS1, PLS2, PLS3, and PLS4, respectively, when the low power signal NAPX is inactivated. The other ends of the capacitors 108a to 108d are connected to the power supply line VDD via a plurality of diode-connected nMOSs. The gates of the pMOSs 108e and 108f receive the pulse signals PLS5 and PLS6 through the logic gates when the low power signal NAPPX is inactivated.

  The pulse signals PLS1, PLS2, and PLS5 and the pulse signals PLS3, PLS4, and PLS6 are out of phase with each other. The high level voltages of the low power signal NAPX and the pulse signals PLS5 and PLS6 are the same as the boost voltage VPP in order to ensure that the pMOSs 108e and 108f are turned off. Capacitors 108a, 108b and 108c, 108d are alternately charged / discharged in accordance with input pulse signals PLS1, PLS2, PLS3, and PLS4. The pMOSs 108e and 108f are alternately turned on in synchronization with the pumping operations of the capacitors 108a and 108b and the capacitors 108c and 108d. The pumping operation boosts the power supply voltage VDD to the boost voltage VPP. The unit 108 stops operating when the low power signal NAPX is activated.

  FIG. 27 shows details of the unit 110 of the booster circuit 92. The unit 110 is a circuit obtained by removing the logic of the low power signals NAPX and NAPPX from the unit 108. That is, the unit 110 always operates after the power is turned on, and generates the boost voltage VPP.

  FIG. 28 shows details of the VPP detection circuit 90. The VPP detection circuit 90 includes a differential amplifier circuit 90a and a voltage generation circuit 90b that applies a voltage to one input of the differential amplifier circuit 90a.

  The differential amplifier circuit 90a includes a current mirror unit 90c configured by pMOS and a pair of differential input units 90d and 90e configured by nMOS. The inputs of the differential input sections 90d and 90e both receive the reference voltage VPREF and the control voltage VPP2 generated by shifting the level of the boost voltage VPP from the voltage generation circuit 90b. The differential input unit 90d is connected to the ground line VSS via an always-on nMOS, and the differential input unit 90e is connected to the ground line VSS via an nMOS that is turned on when the low power signal NAPX is inactivated. Has been.

  That is, the differential input unit 90d always operates, and the differential input unit 90e operates only when the low power signal NAPX is inactivated. Since the differential input unit 90e stops operating during the low power consumption mode, power consumption is reduced. The differential amplifier circuit 90a activates (high level) the boost enable signal when the control voltage VPP2 is lower than the reference voltage VPREF.

  The voltage generation circuit 90b is configured by connecting three resistors in series between the generation node of the boost voltage VPP and the ground line VSS. The control voltage VPP2 is output from the other end of the resistor on the generation node side of the boost voltage VPP. The source and drain of the nMOS controlled by the low power signal NAPX are connected to both ends of the resistor connected to the ground line VSS. The resistor connected to the ground line VSS is bypassed when the low power signal NAPX is activated. For this reason, the level of the control voltage VPP2 decreases during the low power consumption mode.

  FIG. 29 shows details of the unit 112 of the substrate voltage generation circuit 100. The unit 112 includes an oscillation circuit 112a and a pumping circuit 112b. The oscillation circuit 112a is configured as a ring oscillator including an odd number of logic gates. The oscillation circuit 112a operates when the substrate voltage detection signal VBBDET is activated and the low power signal NAPX is deactivated.

  The pumping circuit 112b includes a voltage supply unit 112c in which three pMOSs and one nMOS are connected in series between a power supply line VDD and a pumping node PND, a capacitor 112d including a pMOS having a gate connected to the pumping node PND, and a pumping node PND. NMOS 112e that connects the pumping node PND and the ground line VSS when n is high, and the diode-connected nMOS 112f that connects the pumping node PND and the substrate node VBB.

  In the pumping circuit 112b, the pMOS and nMOS of the voltage supply unit 112c and the capacitor 112d receive the clock signal from the oscillation circuit 112a, so that the pumping node PND alternately becomes a ground voltage and a negative voltage. Then, when the pumping node PND becomes a negative voltage, the charge of the substrate node VBB is extracted, and the substrate node VBB becomes a negative voltage. The unit 112 stops operation during the low power consumption mode (when the low power signal NAPX is activated).

  FIG. 30 shows details of the unit 114 of the substrate voltage generation circuit 100. The unit 114 includes an oscillation circuit 114a and a pumping circuit 114b. The oscillation circuit 114 a is a circuit obtained by removing the logic of the low power signal NAPX from the oscillation circuit 112 a of the unit 112. That is, the oscillation circuit 114a operates according to the substrate voltage detection signal VBBDET even during the low power consumption mode, and generates the substrate voltage VBB. The pumping circuit 114b is the same circuit as the pumping circuit 112b of the unit 112.

  FIG. 31 shows details of the VBB detection circuit 98. The VBB detection circuit 98 includes two detection units 98a and 98b and an OR circuit 98c that outputs the OR logic of the detection results of these units 98a and 98b as a substrate voltage detection signal VBBDET.

  The detection unit 98a includes a reference voltage generator 98d in which a resistor, a pMOS, and a resistor are connected in series between the internal power line VII and the ground line VSS, a level detector 98e in which two nMOSs are connected in series, and a pMOS load circuit The pMOS is connected to the power supply line VII through the CMOS inverter 98f, and the level detection unit 98f has an nMOS 98g that connects the output node NOUT1 to the ground line VSS. The pMOS gate and the nMOS 98gn gate of the reference voltage generator 98d receive the low power signal NAPX. For this reason, the detection unit 98a is deactivated in the normal operation mode and activated in the low power consumption mode. The voltage of the output node NOUT1 of the level detection unit 98e rises with the rise of the substrate voltage VBB when activated. In this embodiment, when the substrate voltage VBB rises to -0.5V, the CMOS inverter 98f receives the detection result (voltage of the output node NOUT1) at the level detection unit 98d and outputs a low level. The OR circuit 98c activates the substrate voltage detection signal VBBDET when receiving a low level from the CMOS inverter 98f.

  In the detection unit 98b, the inverted logic of the low power signal NAPX is supplied to the gate of the pMOS and the gate of the nMOS 98g of the reference voltage generator 98d. The other configuration is the same as that of the detection unit 98a. In this embodiment, the CMOS inverter 98f receives the detection result (voltage of the output node NOUT1) at the level detection unit 98e and outputs a low level when the substrate voltage VBB rises to −1.0 V in the normal operation mode. . The output of the reference voltage generator 98d of the detection unit 98b becomes the ground voltage VSS (0 V) when the low power signal NAPX is at a low level (in the low power consumption mode). For this reason, the output node NOUT2 of the level detector 98e is always at a low level. That is, the detection unit 98b is deactivated during the low power consumption mode.

  Therefore, the VBB detection circuit 98 activates the substrate voltage detection signal VBBDET when the substrate voltage VBB rises to −1.0 V using only the detection unit 98b in the normal operation mode. By activation of substrate voltage detection signal VBBDET, units 112 and 114 of substrate voltage generation circuit 100 shown in FIGS. 29 and 30 operate, and substrate voltage VBB decreases.

  Further, the VBB detection circuit 98 activates the detection unit 98a and deactivates the detection unit 98b in response to the activation of the low power signal NAPX in the low power consumption mode. As a result, the power consumption of the VBB detection circuit 98 is reduced. Since the level of the substrate voltage VBB is detected only by the detection unit 98a during the low power consumption mode, the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to −0.5V. Since the detection level (absolute value) of the substrate voltage VBB decreases, the absolute value of the substrate voltage VBB generated by the substrate voltage generation circuit 100 decreases. That is, during the low power consumption mode, the operation of the substrate voltage generation circuit 100 can be suppressed as compared with the normal operation mode. As a result, power consumption can be reduced. Since the difference between the substrate voltage VBB and the ground voltage VSS is reduced, the amount of substrate leakage is reduced. Therefore, the generation frequency of the substrate voltage detection signal VBBDET decreases, and the operation frequency of the substrate voltage generation circuit 100 decreases. As a result, power consumption can be further reduced.

  FIG. 32 shows details of the precharge voltage generation circuit 94. The precharge voltage generation circuit 94 includes differential amplifier circuits 94a and 94b and a VPR generation unit 94c.

  The differential amplifier circuit 94a includes a current mirror unit 94d made of pMOS and a pair of differential input units 94e and 94f made of nMOS. The inputs of the differential input units 94e and 94f both receive the reference voltage VPRREFL and the precharge voltage VPR. The differential input unit 94e is connected to the ground line VSS through the nMOS that is always on, and the differential input unit 94f is connected to the ground line VSS through the nMOS that is turned on when the low power signal NAPX is inactivated. Has been.

  That is, the differential input unit 94e always operates, and the differential input unit 94f operates only when the low power signal NAPX is inactivated. Since the differential input unit 94f stops operating during the low power consumption mode, the power consumption is reduced. The differential amplifier circuit 94a sets the output node NOUT3 to a low level when the reference voltage VPRREFL is higher than the precharge voltage VPR.

  The differential amplifier circuit 94b has a current mirror part 94g made of nMOS and a pair of differential input parts 94h and 94i made of pMOS. The inputs of the differential input sections 94h and 94i both receive the reference voltage VPRREFH and the precharge voltage VPR. The differential input section 94g is connected to the power supply line VDD via a pMOS that is always on, and the differential input section 94i is connected to the power supply line VDD via a pMOS that is turned on when the low power signal NAPX is deactivated. It is connected.

  The differential input unit 94h always operates, and the differential input unit 94i operates only when the low power signal NAPX is inactivated. Since the differential input unit 94i stops operating during the low power consumption mode, the power consumption is reduced. The differential amplifier circuit 94b sets the output node NOUT4 to a low level when the reference voltage VPRREFH is lower than the precharge voltage VPR.

  The VPR generator 94c includes a pMOS and an nMOS connected in series between the power supply line VDD and the ground line VSS. The gate of the pMOS is connected to the output node NOUT3. The gate of the nMOS is connected to the output node NOUT4. The precharge voltage VPR is output from the drains of the pMOS and nMOS. The precharge voltage VPR is used as an equalize voltage of a bit line pair in the memory core 38 and a plate voltage of the memory cell.

  By deactivating the differential input portions 94f and 94i during the low power consumption mode, the response of the precharge voltage generation circuit 94 to the change of the precharge voltage VPR becomes worse. However, as described later, since the read / write operation and the refresh operation are not executed during the low power consumption mode, there is no problem even if the response of the precharge voltage generation circuit 94 is lowered.

  FIG. 33 shows details of the oscillation circuit 104. The oscillation circuit 104 includes a ring oscillator 104a in which an odd number of stages of CMOS inverters are connected in cascade, and a buffer 104b for taking out an oscillation signal OSCZ from the ring oscillator 104a. A broken line frame in the figure is a switch for adjusting the number of stages of the ring oscillator 104a (self-refresh cycle). These switches are turned on and off by fusing a polysilicon fuse or by a photomask layout pattern in the wiring layer. In this example, the number of stages of the ring oscillator 104a is set to seven. The sources of the pMOS and nMOS of the CMOS inverter are connected to the internal power supply line VII and the ground line VSS via the pMOS load and the nMOS load, respectively. The gates of the pMOS load and the nMOS load are controlled by control voltages PCNTL and NCNTL, respectively.

  The oscillation circuit 104 includes a pMOS and an nMOS that are controlled by the low power signal NAPX. When the low power signal NAPX is activated, these pMOSs are turned on, so that a predetermined node of the ring oscillator 104a is fixed to a high level, and when these nMOSs are turned off, the nMOS of the CMOS inverter and the ground line VSS Is disconnected. As a result, the oscillation circuit 104 stops operating during the low power consumption mode.

  FIG. 34 shows a generation circuit 116 for the control voltages PCNTL and NCNTL built in the oscillation circuit 104. The generation circuit 116 includes a pMOS, a pMOS diode, and a resistor connected in series between the internal power supply line VII and the ground line VSS, and a resistor connected in series between the internal power supply line VII and the ground line VSS. nMOS diode, nMOS, MOS capacitor arranged between a node generating control voltage PCNTL and internal power supply line VII, and MOS capacitor arranged between a node generating control voltage NCNTL and ground line VSS And have.

  The control voltage PCNTL is generated from the connection node between the pMOS diode and the resistor, and changes corresponding to the fluctuation of the internal power supply voltage VII. The control voltage NCNTL is generated from a connection node between the nMOS diode and the resistor, and changes in response to a change in the ground voltage VSS. Therefore, the source-gate voltages of the pMOS and nMOS of the CMOS inverter shown in FIG. 33 are always constant, and the oscillation period of the ring oscillator 104a is constant regardless of the fluctuation of the internal power supply voltage VII. The MOS capacitor prevents high-frequency noise generated in the internal power supply line VII and the ground line VSS from affecting the control voltage PCNTL and the control voltage NCNTL. As a result, fluctuations in internal power supply voltage VII and ground voltage VSS are cancelled, and oscillation signal OSCZ is always generated at a predetermined cycle while oscillation circuit 104 is operating (during the self-refresh mode).

  The pMOS and nMOS are turned off when the low power signal NAPX is activated. That is, the generation circuit 116 is inactivated during the low power consumption mode. At this time, the control voltages PCNTL and NCNTL become low level and high level, respectively.

  In the DRAM described above, as in the first embodiment, the low power entry circuit 84 shown in FIG. 22 activates the low power signal NAPX (low level when receiving a low level chip enable signal CE2 from the outside). And the chip is shifted to the low power consumption mode.

  By the activation of the low power signal NAPX, the reference voltage generating circuit 24 shown in FIG. 23 lowers the levels of the reference voltages VRFV, VPREF, VPREFL, and VPREFH. The VPP detection circuit 90 shown in FIG. 28 deactivates the differential input unit 90e, and simultaneously lowers the level of the control voltage VPP2 applied to the differential input unit 90d. The unit 108 of the booster circuit 92 and the unit 112 of the substrate voltage generation circuit 100 shown in FIG. The VBB detection circuit 98 shown in FIG. 31 deactivates the detection unit 98b, activates the detection unit 98a, and raises the detection level of the substrate voltage VBB. That is, the substrate voltage detection signal VBBDET is activated when the substrate voltage VBB rises to −0.5V. The differential amplifier circuits 94a and 94b of the precharge voltage generation circuit 94 shown in FIG. 32 inactivate the differential input portions 94f and 94i, respectively. The oscillation circuit 104 illustrated in FIG. 33 stops operating. The generation circuit 116 shown in FIG. 34 is deactivated.

  FIG. 35 shows operations of the oscillation circuit 104 and the frequency dividing circuit 102. When the low power signal NAPX is activated, the oscillation circuit 104 sets the oscillation signal OSCZ to a low level. Since the oscillation of the oscillation signal OSCZ stops, the frequency dividing operation by the frequency dividing circuit 102 stops, and the self-refresh timer signal SRTZ becomes low level. For this reason, the power consumption of the frequency dividing circuit 102 becomes substantially zero.

  As described above, the operation of the plurality of control circuits is stopped or the capability is reduced, so that the power consumption in the low power consumption mode is significantly reduced as compared with the related art. Since some of the control circuits continue to operate in a state where the capability is lowered, normal operation can be started immediately after the release from the low power consumption mode.

  As described above, in this embodiment, the self-refresh oscillation circuit 104 is stopped during the low power consumption mode, and the operation in the self-refresh mode is stopped. As a result, the power consumption during the low power consumption mode can be reduced. Since the refresh is not executed, the internal voltage generation circuit 86 may be operated with an ability to compensate for the power (leakage current) consumed by the peripheral circuit 40. As a result, the power consumption during the low power consumption mode can be reduced.

  Internal voltages VPP, VBB, and VPR are supplied to internal circuits (peripheral circuit 40, memory core 38, etc.) even during the low power consumption mode. Therefore, the peripheral circuit 40 and the memory core 38 can be operated immediately after the release of the low power consumption mode. Since the operations of the unit 108 of the booster circuit 92 and the unit 112 of the substrate voltage generation circuit 100 are stopped during the low power consumption mode, the power consumption during the low power consumption mode can be further reduced.

  During the low power consumption mode, the connection between the internal power supply line VII and the stabilization capacitor 96a is maintained, and the connection between the internal power supply line VII and the internal circuit (the peripheral circuit 40 and the memory core 38) is cut off. Since the supply of power to the peripheral circuit 40 is stopped, the leakage current of the peripheral circuit 40 is eliminated and the power consumption can be reduced to zero. After the release of the low power consumption mode, when the internal power supply line VII and the internal circuit are connected, a voltage corresponding to the electric charge stored in the stabilization capacitor is applied to the internal circuit via the internal power supply line VII. Therefore, after the low power consumption mode is released, before the internal power supply voltage generation circuit 96 generates a predetermined internal power supply voltage VII, a voltage corresponding to the charge stored in the stabilization capacitor 96a is applied to the internal circuit. Can do. As a result, the internal circuit can operate immediately after the release of the low power consumption mode.

  During the low power consumption mode, the differential input section 90e in the differential amplifier circuit 90a of the VPP detection circuit 90 and the differential input sections 94f and 94i in the differential amplifier circuits 94a and 94b of the precharge voltage generation circuit 94 are deactivated. Therefore, the power consumption of the differential amplifier circuits 90a, 94a, 94b can be reduced. Since the operations of the unit 108 of the booster circuit 92 and the unit 112 of the substrate voltage generation circuit 100 are stopped during the low power consumption mode, transient variations in the boost voltage VPP and the substrate voltage VBB can be suppressed. That is, since the difference between the maximum value and the minimum value of the boost voltage VPP and the substrate voltage VBB can be reduced, leakage current can be reduced.

  By reducing the levels of the reference voltages VPREF, VRFV (VII), VPRREFH, and VPRREFL generated by the reference voltage generation circuit 24, the absolute levels of the detection levels of the VPP detection circuit 90, the VBB detection circuit 98, and the precharge voltage generation circuit 94 are reduced. The values were reduced, and the levels (absolute values) of the boosted voltage VPP, the substrate voltage VBB, and the precharge voltage VPR generated by the booster circuit 92, the substrate voltage generation circuit 100, and the precharge voltage generation circuit 94 were decreased. Since the leakage current can be reduced by reducing the voltage, power consumption can be reduced.

  In the above-described embodiment, the example in which the present invention is applied to the DRAM has been described. The present invention is not limited to this, and may be applied to, for example, SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), or FCRAM (Fast Cycle RAM).

  The semiconductor manufacturing process to which the present invention is applied is not limited to the CMOS process, but may be a Bi-CMOS process.

  In the second embodiment described above, the example in which the low power entry circuit 50 is formed by connecting a plurality of delay circuits 54c in series has been described. The present invention is not limited to this. For example, a low power entry circuit may be formed using a latch circuit controlled by the STTCRX signal. In this case, the circuit scale is reduced.

  In the above-described third embodiment, the example using the dedicated low power consumption mode signal / LP has been described. For example, by pulling up the / LP signal inside the chip and not providing a terminal for the / LP signal, this DRAM can be supplied even to users who do not need the low power consumption mode. The / LP signal may be connected to the power supply voltage VDD by bonding or fusing. Alternatively, the / LP signal may be connected to the power supply voltage VDD by switching the photomask of the wiring layer.

  In the fifth embodiment described above, the example in which the boosted voltage VPP is compared with the power supply voltage VDD has been described. The present invention is not limited to this. For example, the boosted voltage VPP may be compared with a reference voltage VREF generated by stepping down the power supply voltage VDD.

  In the sixth embodiment described above, when the low power consumption mode is released, the start signal generation circuit 82 operates as a timer for generating the period T2, and the STTPZ signal (reset signal) for initializing the internal circuit in this period T2 ) Was activated. The present invention is not limited to this. For example, when the low power consumption mode is canceled, a counter that operates during normal operation is operated as a timer, and the internal circuit is initialized during a period when the counter is counting a predetermined number. A reset signal may be activated. As the counter, for example, a refresh counter indicating the refresh address of the memory cell can be used.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

The inventions described in the above embodiments are organized and the following supplementary notes are disclosed.
(Appendix 1) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
A semiconductor memory device comprising: an entry circuit that receives a control signal from the outside, deactivates the internal voltage generation circuit, and shifts the chip to a low power consumption mode.
(Appendix 2) In the semiconductor memory device according to Appendix 1,
A word line connected to the memory cell;
2. The semiconductor memory device according to claim 1, wherein the internal voltage generation circuit includes a booster circuit that generates a boost voltage supplied to the word line.
(Supplementary note 3) In the semiconductor memory device according to supplementary note 1,
2. The semiconductor memory device according to claim 1, wherein the internal voltage generation circuit includes a substrate voltage generation circuit that generates a substrate voltage supplied to the substrate.
(Appendix 4) In the semiconductor memory device according to Appendix 1,
Comprising a memory core having a plurality of memory cells;
The semiconductor memory device, wherein the internal voltage generation circuit includes an internal power supply voltage generation circuit that generates an internal power supply voltage that is lower than the power supply voltage and is supplied to the memory core.
(Appendix 5) In the semiconductor memory device according to Appendix 1,
A memory core having a memory cell and a bit line connected to the memory cell;
The semiconductor memory device, wherein the internal voltage generation circuit includes a precharge voltage generation circuit for generating a precharge voltage to be supplied to the bit line.
(Appendix 6) In the semiconductor memory device according to Appendix 1,
A semiconductor memory device comprising: an external voltage supply circuit that supplies the power supply voltage to the predetermined internal circuit as the internal voltage in the low power consumption mode.
(Appendix 7) In the semiconductor memory device according to Appendix 1,
The entry circuit receives a reset signal for deactivating a predetermined internal circuit from the outside and shifts the chip to a low power consumption mode.
(Appendix 8) In the semiconductor memory device according to Appendix 1,
The entry circuit receives a plurality of control signals from the outside, and shifts the chip to a low power consumption mode when the state of these control signals is a low power consumption command.
(Supplementary note 9) In the semiconductor memory device according to supplementary note 8,
The entry circuit receives a reset signal for deactivating a predetermined circuit in the chip and a chip enable signal for activating each circuit of the chip during a read / write operation from the outside, and the state of these signals is a low power consumption command. A semiconductor memory device, wherein the chip is shifted to a low power consumption mode.
(Supplementary note 10) In the semiconductor memory device according to supplementary note 9,
The semiconductor memory device, wherein the entry circuit shifts to a low power consumption mode when the reset signal is inactivated for a predetermined period and when the chip enable signal is activated for a predetermined period.
(Supplementary note 11) In the semiconductor memory device according to supplementary note 8,
The entry circuit receives the plurality of control signals during the low power consumption mode, and cancels the low power consumption mode when the state of these control signals requests to release the low power consumption mode. A semiconductor memory device.
(Supplementary note 12) In the semiconductor memory device according to supplementary note 1,
The entry circuit receives the predetermined level or transition edge of the low power consumption mode signal and shifts the chip to the low power consumption mode.
(Supplementary Note 13) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
An entry circuit that receives a control signal from the outside, deactivates the internal voltage generation circuit, and shifts the chip to a low power consumption mode;
The entry circuit receives the control signal during the low power consumption mode, and cancels the low power consumption mode when the state of the control signal requests to release the low power consumption mode. A semiconductor memory device.
(Supplementary note 14) In the semiconductor memory device according to supplementary note 13,
A reset signal for initializing an internal circuit is activated during a period when the internal voltage is lower than a predetermined voltage when the low power consumption mode is released.
(Supplementary Note 15) In the semiconductor memory device according to Supplementary Note 14,
The semiconductor memory device, wherein the predetermined voltage is a reference voltage generated by stepping down the power supply voltage.
(Supplementary note 16) In the semiconductor memory device according to supplementary note 13,
A semiconductor memory device, wherein a reset signal for initializing an internal circuit is activated during a period when a boosted voltage generated internally is lower than a predetermined voltage when the low power consumption mode is released.
(Supplementary note 17) In the semiconductor memory device according to supplementary note 16,
The semiconductor memory device, wherein the predetermined voltage is the power supply voltage.
(Supplementary note 18) In the semiconductor memory device according to supplementary note 16,
The semiconductor memory device, wherein the predetermined voltage is a reference voltage generated by stepping down the power supply voltage.
(Supplementary note 19) In the semiconductor memory device according to supplementary note 13,
When the low power consumption mode is released, a reset signal for initializing an internal circuit is activated for a period in which at least one of the internal voltage and an internally generated boosted voltage is lower than a predetermined voltage, respectively. A semiconductor memory device.
(Supplementary note 20) In the semiconductor memory device according to supplementary note 13,
A timer for measuring a predetermined time at the release of the low power consumption mode;
A semiconductor memory device, wherein a reset signal for initializing an internal circuit is activated during a period measured by the timer.
(Supplementary note 21) In the semiconductor memory device according to supplementary note 20,
The timer has a CR time constant circuit,
The semiconductor memory device, wherein the predetermined time is measured based on a propagation delay time of a signal propagated to the CR time constant circuit.
(Supplementary note 22) In the semiconductor memory device according to supplementary note 20,
The timer has a counter that operates during normal operation,
The semiconductor memory device, wherein the predetermined time is measured based on a count value of the counter.
(Supplementary note 23) In the semiconductor memory device according to supplementary note 22,
The semiconductor memory device, wherein the counter is a refresh counter indicating a refresh address of a memory cell.
(Supplementary Note 24) A self-refresh control circuit for automatically refreshing memory cells at a predetermined cycle;
An internal voltage generating circuit for receiving a power supply voltage from the outside and generating an internal voltage to be supplied to a predetermined internal circuit;
When the control signal is received from the outside, the self-refresh control circuit is deactivated, and the internal voltage generation circuit has a low ability to supply the internal voltage, and the chip is shifted to a low power consumption mode. A semiconductor memory device.
(Supplementary Note 25) In the semiconductor memory device according to Supplementary Note 24,
The internal voltage generation circuit includes a plurality of units for generating the internal voltage,
A part of the unit is stopped during the low power consumption mode.
(Supplementary Note 26) A stabilization capacitor that is connected to a power supply line and stores a part of the electric charge supplied to the power supply line;
An internal circuit connected to the power line,
When the control signal is received from the outside, the connection between the power supply line and the stabilization capacitor is maintained, the connection between the power supply line and the internal circuit is cut off, and the chip is shifted to the low power consumption mode. A semiconductor memory device.
(Supplementary note 27) In the semiconductor memory device according to supplementary note 26,
It has an internal voltage generation circuit that receives power supply voltage from the outside and generates internal voltage.
The semiconductor memory device, wherein the internal voltage is supplied to the internal circuit through the power line.
(Supplementary Note 28) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
A semiconductor memory device characterized in that when a control signal is received from the outside, the capability of the internal voltage detection circuit is lowered and the chip is shifted to a low power consumption mode.
(Supplementary note 29) In the semiconductor memory device according to supplementary note 28,
The internal voltage detection circuit includes a plurality of units for detecting the level of the internal voltage,
A part of the unit is stopped during the low power consumption mode.
(Supplementary Note 30) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
When the control signal is received from the outside, the absolute value of the internal voltage generated by the internal voltage generation circuit is reduced by reducing the detection level of the internal voltage in the internal voltage detection circuit, thereby reducing the consumption of the chip. A semiconductor memory device, which is shifted to a power mode.
(Supplementary note 31) In the semiconductor memory device according to supplementary note 30,
A reference voltage generating circuit for generating a reference voltage;
The internal voltage detection circuit detects the level of the internal voltage by comparing the internal voltage and the reference voltage,
A semiconductor characterized in that the level of the internal voltage in the internal voltage detection circuit is lowered by lowering the level of the reference voltage generated by the reference voltage generation circuit when a control signal is received from the outside. Storage device.
(Supplementary Note 32) An internal voltage generation circuit that receives an external power supply voltage and generates an internal voltage to be supplied to a predetermined internal circuit is provided.
A method for controlling a semiconductor memory device, comprising: deactivating the internal voltage generation circuit when a control signal is received from the outside, and shifting the chip to a low power consumption mode.
(Supplementary note 33) In the method for controlling a semiconductor memory device according to supplementary note 32,
A method of controlling a semiconductor memory device, wherein a plurality of control signals are received from the outside, and the chip is shifted to a low power consumption mode when the state of these control signals is a low power consumption command.
(Supplementary Note 34) In the method for controlling a semiconductor memory device according to Supplementary Note 33,
Low power consumption when a reset signal that inactivates a predetermined circuit in the chip is inactivated for a predetermined period, and a chip enable signal that activates each circuit of the chip during a read / write operation is activated for a predetermined period Enter power mode,
A method of controlling a semiconductor memory device, wherein the reset signal is deactivated for a predetermined period at power-on.
(Supplementary Note 35) An internal voltage generation circuit that receives an external power supply voltage and generates an internal voltage to be supplied to a predetermined internal circuit is provided.
When receiving a control signal from the outside, the internal voltage generation circuit is deactivated, and the chip is shifted to a low power consumption mode.
A semiconductor memory device, wherein the low power consumption mode is canceled when the control signal is received during the low power consumption mode and the state of the control signal requires the cancellation of the low power consumption mode Control method.
(Supplementary Note 36) In the method for controlling a semiconductor memory device according to Supplementary Note 35,
A method for controlling a semiconductor memory device, comprising: activating a reset signal for initializing an internal circuit during a period when the internal voltage is lower than a predetermined voltage when the low power consumption mode is released.
(Supplementary Note 37) A self-refresh control circuit that automatically refreshes memory cells at a predetermined cycle;
An internal voltage generating circuit for receiving a power supply voltage from the outside and generating an internal voltage to be supplied to a predetermined internal circuit;
When the control signal is received from the outside, the self-refresh control circuit is deactivated, and the internal voltage generation circuit has a low ability to supply the internal voltage, and the chip is shifted to a low power consumption mode. A method for controlling a semiconductor memory device.
(Supplementary Note 38) A stabilization capacitor that is connected to a power supply line and stores a part of the electric charge supplied to the power supply line;
An internal circuit connected to the power line,
When the control signal is received from the outside, the connection between the power supply line and the stabilization capacitor is maintained, the connection between the power supply line and the internal circuit is cut off, and the chip is shifted to the low power consumption mode. A method for controlling a semiconductor memory device.
(Supplementary Note 39) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
A control method of a semiconductor memory device, wherein when a control signal is received from the outside, the capability of the internal voltage detection circuit is lowered and the chip is shifted to a low power consumption mode.
(Supplementary Note 40) An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
When the control signal is received from the outside, the absolute value of the internal voltage generated by the internal voltage generation circuit is reduced by reducing the detection level of the internal voltage in the internal voltage detection circuit, thereby reducing the consumption of the chip. A method for controlling a semiconductor memory device, wherein the method is shifted to a power mode.

  In the semiconductor memory device of Appendix 2, the entry circuit receives an external control signal, stops the operation of the booster circuit, and stops generating the boost voltage supplied to the word line. In the low power consumption mode, the booster circuit that constantly consumes power stops, so that power consumption is greatly reduced.

  In the semiconductor memory device of appendix 3, the entry circuit receives an external control signal, stops the operation of the substrate voltage generation circuit, and stops the generation of the substrate voltage supplied to the substrate. In the low power consumption mode, the substrate voltage generation circuit that constantly consumes power stops, so that power consumption is greatly reduced.

  In the semiconductor memory device of appendix 4, the entry circuit receives an external control signal, stops the operation of the internal power supply voltage generation circuit, and stops the generation of the internal power supply voltage supplied to the memory core. In the low power consumption mode, the internal power supply voltage generation circuit that constantly consumes power stops, so that power consumption is greatly reduced.

  In the semiconductor memory device of appendix 5, the entry circuit receives the control signal from the outside, stops the operation of the precharge voltage generation circuit, and stops the generation of the precharge voltage supplied to the bit line. In the low power consumption mode, the precharge voltage generation circuit that constantly consumes power stops, so that power consumption is greatly reduced.

  In the semiconductor memory device of appendix 9, the entry circuit receives a reset signal and a chip enable signal from the outside. When the entry circuit recognizes that the state of these control signals is a low power consumption command, the entry circuit shifts the chip to the low power consumption mode. For this reason, the chip can be shifted to the low power consumption mode by command input.

  In the semiconductor memory device of appendix 10, when the reset signal is inactivated for a predetermined period, and the chip enable signal is further activated for a predetermined period in this state, the mode is shifted to the low power consumption mode. For this reason, even when a glitch occurs in the reset signal or the chip enable signal due to power supply noise or the like, it is possible to prevent erroneous shift to the low power consumption mode.

  In the semiconductor memory device according to attachment 11, the entry circuit receives a plurality of control signals from the outside during the low power consumption mode. The entry circuit releases the chip from the low power consumption mode when the state of the control signal requires the low power consumption mode to be released. For this reason, the low power consumption mode can be canceled by inputting a command.

  In the semiconductor memory device of appendix 19, when the low power consumption mode is released, a reset signal for initializing the internal circuit is received for a period in which at least one of the internal voltage and the boosted voltage generated internally is lower than a predetermined voltage. Activated. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be reset more reliably, and malfunction of the internal circuit can be prevented.

  In the semiconductor memory device of appendix 21, the timer has a CR time constant circuit. The timer measures a predetermined time based on the propagation delay time of the signal propagated to the CR time constant circuit. Therefore, the activation period of the reset signal can be set with a simple circuit.

  In the semiconductor memory devices of appendix 22 and appendix 23, when the low power consumption mode is released, a reset signal for initializing the internal circuit is activated during a period in which the counter operating during normal operation is counting a predetermined number Is done. For this reason, when shifting from the low power consumption mode to the normal operation mode, the internal circuit can be surely reset, and malfunction of the internal circuit can be prevented. As the counter, for example, a refresh counter indicating the refresh address of the memory cell is used.

  In the semiconductor memory device according to attachment 25, the internal voltage generation circuit includes a plurality of units for generating the internal voltage. Since some of the units stop operating during the low power consumption mode, the power consumption during the low power consumption mode can be further reduced.

  In the semiconductor memory device according to attachment 27, the internal voltage generation circuit receives a power supply voltage from the outside and generates an internal voltage. The internal voltage is supplied to the internal circuit through a power line. For this reason, the voltage corresponding to the electric charge stored in the stabilization capacitor can be applied to the internal circuit after the low power consumption mode is released.

  In the semiconductor memory device according to attachment 29, the internal voltage detection circuit includes a plurality of units for detecting the level of the internal voltage. Since some of the units stop operating during the low power consumption mode, the power consumption during the low power consumption mode can be further reduced.

In the semiconductor memory device according to attachment 31, the reference voltage generation circuit generates a reference voltage. The internal voltage detection circuit detects the level of the internal voltage by comparing the internal voltage with the reference voltage.
The semiconductor memory device lowers the detection level of the internal voltage in the internal voltage detection circuit by lowering the level of the reference voltage generated by the reference voltage generation circuit when receiving a control signal from the outside. As a result, the level of the internal voltage is lowered and the off current of the transistors and the like in the internal circuit is reduced, so that power consumption can be reduced.

  In the method for controlling a semiconductor memory device according to attachment 34, the chip enable signal is deactivated until the power supply voltage becomes a predetermined voltage at power-on. This prevents erroneous shift to the low power consumption mode at power-on.

It is a state transition diagram of the semiconductor memory device of the present invention. It is a block diagram which shows the basic principle of 1st Embodiment. It is a block diagram which shows 1st Embodiment. FIG. 4 is a circuit diagram showing details of a booster circuit and a precharge voltage generation circuit of FIG. 3. FIG. 4 is a circuit diagram showing details of an internal power supply voltage generation circuit and a substrate voltage generation circuit of FIG. 3. FIG. 4 is a circuit diagram showing details of a main part of the memory core of FIG. 3. FIG. 6 is a timing chart showing operations at the time of power-on, entry to a low power consumption mode, and exit in the first embodiment. It is a block diagram which shows the example which used the semiconductor memory device of 1st Embodiment for the mobile phone. It is explanatory drawing which shows the use condition of the mobile telephone shown in FIG. It is a flowchart which shows the control state of the mobile telephone shown in FIG. It is a block diagram which shows 2nd Embodiment. FIG. 12 is a circuit diagram showing details of the low power entry circuit of FIG. 11. FIG. 13 is a timing chart showing an operation of the low power entry circuit of FIG. 12. It is a block diagram which shows 3rd Embodiment. It is a circuit diagram which shows the VII starting circuit in 4th Embodiment. It is a circuit diagram which shows the VII starting circuit in 4th Embodiment. It is a timing diagram which shows the operation | movement at the time of the entry to the low power consumption mode in 4th Embodiment, and an exit. It is a circuit diagram which shows the level detection circuit in 5th Embodiment. FIG. 16 is a timing diagram illustrating operations during entry to a low power consumption mode and during exit according to a fifth embodiment. It is a circuit diagram which shows the starting signal generation circuit in 6th Embodiment. It is a timing diagram which shows the operation | movement at the time of the entry to the low power consumption mode in 6th Embodiment, and an exit. It is a block diagram which shows 7th Embodiment. FIG. 23 is a circuit diagram showing details of the reference voltage generation circuit of FIG. 22. FIG. 23 is a circuit diagram showing details of an internal power supply voltage generation circuit of FIG. 22. It is a block diagram showing a booster circuit, a VPP detection circuit, a substrate voltage generation circuit, and a VBB detection circuit. FIG. 26 is a circuit diagram showing details of a unit of the booster circuit of FIG. 25. FIG. 26 is a circuit diagram showing details of a unit of the booster circuit of FIG. 25. It is a circuit diagram which shows the detail of the VPP detection circuit of FIG. FIG. 26 is a circuit diagram showing details of a unit of the substrate voltage generation circuit of FIG. 25. FIG. 26 is a circuit diagram showing details of a unit of the substrate voltage generation circuit of FIG. 25. It is a circuit diagram which shows the detail of the VBB detection circuit of FIG. FIG. 23 is a circuit diagram showing details of a precharge voltage generation circuit of FIG. 22. It is a circuit diagram which shows the detail of the oscillation circuit of FIG. FIG. 24 is a circuit diagram showing details of a generation circuit built in the oscillation circuit of FIG. 23. FIG. 16 is a timing diagram illustrating operations of an oscillation circuit and a frequency dividing circuit according to a seventh embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 VII starting circuit 12 VDD starting circuit 14 Low power entry circuit 16 Command decoder 18 Internal voltage generating circuit 20 Chip body 22 Low pass filter 24 Reference voltage generating circuit 26 VDD supply circuit 28 Booster circuit 30 Precharge voltage generating circuit 32 Internal power supply voltage generating Circuit 34 Substrate voltage generation circuit 36 VSS supply circuit 38 Memory core 40 Peripheral circuit 50 Low power entry circuit 52 Command decoder 62 Low power entry circuit 70 VII activation circuit 72 Release detection circuit 72a Detection circuit 72b Level shifter 72c Flip flop 74 Level detection circuit 74a Differential amplifier circuit 74b Inverter train 76 Power-on circuit 78 OR circuit 80 Level detection circuit 80a, 80c Differential amplifier circuit 80b, 80d Inverter train 80e NAND gate 82 Startup signal generator Circuit 82a CMOS inverter 82b MOS capacitor 82c Differential amplifier circuit 84 Low power entry circuit 86 Internal voltage generation circuit 88 Chip body 88
90 VPP detection circuit 92 Booster circuit 94 Precharge voltage generation circuit 96 Internal power supply voltage generation circuit 98 VBB detection circuit 100 Substrate voltage generation circuit 102 Dividing circuit 104 Oscillation circuit 104
106 Oscillator 108, 110 Unit 112, 114 Unit 116 Generation Circuit
AD address signal
BL, / BL bit line
/ CE1, CE2 Chip enable signal
CE2X chip enable signal
CN control signal
DQ data input / output signal
/ LP Low power mode signal
LPLS pulse
MC memory cell
NAPX, NAPPX Low power signal
NCNTL control voltage
OSCZ oscillation signal
PCNTL control voltage
PLS1 to PLS6 pulse signal
REL release signal
SRTZ timer signal
STTCRX start signal
STTPZ, STT start signal
STTVII start signal
ULP low power signal
VBB board voltage
VDD supply voltage
VII Internal power supply voltage
VPP boost voltage
VPPEN Boost enable signal
VPR precharge voltage
VPREF, VPRREFL, VPRREFH, VRFV reference voltage
VREF reference voltage
VSS Ground voltage
WL0, WL1 Word line
VBBDET Board voltage detection signal

Claims (29)

A semiconductor memory device having a low power consumption mode having a dynamic memory cell, wherein the memory cell does not hold data by prohibiting a refresh operation and generation of an internal voltage by an internal voltage generation circuit is stopped In operation method,
And wherein said other than the control signals supplied to perform the access operation of the memory cell in response to a dedicated external control signal for shifting to the low power consumption mode shifts to the low power consumption mode Method of operating a semiconductor memory device. The operation method of the semiconductor memory device according to claim 1.
A method of operating a semiconductor memory device, wherein the semiconductor memory device shifts to the low power consumption mode during an idle mode period. The operation method of the semiconductor memory device according to claim 1.
The method of operating a semiconductor memory device, wherein the semiconductor memory device shifts to the low power consumption mode in response to the external control signal changing from a first voltage to a second voltage. The operation method of the semiconductor memory device according to claim 3.
A method of operating a semiconductor memory device, characterized in that the low power consumption mode is maintained while the external control signal is at the second voltage. The operation method of the semiconductor memory device according to claim 4.
A method of operating a semiconductor memory device, wherein the low power consumption mode is canceled in response to a change in the external control signal from the second voltage to the first voltage. By prohibiting the refresh operation, the dynamic memory cell does not hold data, and the memory cell access operation to the semiconductor memory device having the low power consumption mode in which the generation of the internal voltage by the internal voltage generation circuit is stopped by outputting the dedicated external control signal for shifting to the low power consumption mode other than the control signals supplied to perform, and characterized by shifting the semiconductor memory device in the low power consumption mode For controlling a semiconductor memory device. A control signal having a dynamic memory cell and having a low power consumption mode in which the memory cell does not hold data by prohibiting a refresh operation, and a control signal supplied to execute an access operation of the data terminal and the memory cell A first memory having a dedicated control terminal for shifting to the low power consumption mode other than the terminal receiving the power;
A flash memory cell;
And a second memory having a data terminal connected to the data terminal of the first memory. A dynamic type memory cell and a dedicated control terminal for shifting to a low power consumption mode other than a terminal for receiving a control signal supplied to execute an access operation of the memory cell are provided and supplied to the control terminal. A control method of a first memory having the low power consumption mode in which the memory cell does not hold data by prohibiting a refresh operation in response to an external control signal and a second memory having a flash memory cell. There,
Before the first memory is transferred to the low power consumption mode, and transfers the data held in the dynamic memory cells of said first memory to the fresh memory cells of the second memory,
After the first memory is released from the low power consumption mode, the transfer of data held in the flash memory cells of the second memory to the dynamic memory cells of said first memory Characteristic control method. An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
A dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the internal voltage generation circuit is deactivated, and the chip is An entry circuit for shifting to a low power consumption mode. The semiconductor memory device according to claim 9.
A semiconductor memory device comprising: an external voltage supply circuit that supplies the power supply voltage to the predetermined internal circuit as the internal voltage in the low power consumption mode. The semiconductor memory device according to claim 9.
A semiconductor memory device comprising an external voltage supply circuit for supplying a ground voltage as the internal voltage to the predetermined internal circuit in the low power consumption mode The semiconductor memory device according to claim 9.
The entry circuit receives a reset signal for inactivating a predetermined internal circuit as the external control signal and shifts the chip to the low power consumption mode. The semiconductor memory device according to claim 9.
The entry circuit shifts the chip to the low power consumption mode in response to a predetermined level or transition edge of the external control signal. An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
A dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the internal voltage generation circuit is deactivated, and the chip is An entry circuit for shifting to a low power consumption mode,
The entry circuit receives the external control signal during the low power consumption mode, and cancels the low power consumption mode when the state of the external control signal requests to release the low power consumption mode. A semiconductor memory device. The semiconductor memory device according to claim 14.
A reset signal for initializing an internal circuit is activated during a period when the internal voltage is lower than a predetermined voltage when the low power consumption mode is released. The semiconductor memory device according to claim 14.
A semiconductor memory device, wherein a reset signal for initializing an internal circuit is activated during a period when a boosted voltage generated internally is lower than a predetermined voltage when the low power consumption mode is released. The semiconductor memory device according to claim 14.
A timer for measuring a predetermined time at the release of the low power consumption mode;
A semiconductor memory device, wherein a reset signal for initializing an internal circuit is activated during a period measured by the timer. A self-refresh control circuit for automatically refreshing memory cells at a predetermined cycle;
An internal voltage generating circuit for receiving a power supply voltage from the outside and generating an internal voltage to be supplied to a predetermined internal circuit;
The self-refresh control circuit is deactivated when a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside. In addition, a semiconductor memory device is characterized in that the internal voltage generating circuit has a low ability to supply the internal voltage, and the chip is shifted to the low power consumption mode. A stabilizing capacitor connected to the power line and storing a portion of the charge supplied to the power line;
Including a memory cell, and an internal circuit connected to the power line,
When a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the power line and the stabilization capacitor A semiconductor memory device characterized in that the connection is maintained and the chip is shifted to the low power consumption mode. An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
When an external control signal dedicated for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the capability of the internal voltage detection circuit is lowered. A semiconductor memory device, wherein the chip is shifted to the low power consumption mode. The semiconductor memory device according to claim 20, wherein
When the external control signal is received from outside, the absolute value of the internal voltage generated by the internal voltage generation circuit is reduced by lowering the detection level of the internal voltage in the internal voltage detection circuit, A semiconductor memory device, wherein the mode is shifted to the low power consumption mode. The semiconductor memory device according to claim 20, wherein
The internal voltage generation circuit includes a plurality of units for generating the internal voltage,
A part of the unit is stopped during the low power consumption mode. An internal voltage generating circuit for receiving an external power supply voltage and generating an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
When receiving a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell from the outside, the internal voltage generation circuit is deactivated, A method of controlling a semiconductor memory device, wherein a chip is shifted to the low power consumption mode. An internal voltage generating circuit for receiving an external power supply voltage and generating an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
When receiving a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell from the outside, the internal voltage generation circuit is deactivated, Shifting the chip to the low power consumption mode,
Receiving the external control signal during the low power consumption mode, and canceling the low power consumption mode when the state of the external control signal requires the low power consumption mode to be released. Storage device control method. A self-refresh control circuit for automatically refreshing memory cells at a predetermined cycle;
An internal voltage generating circuit for receiving a power supply voltage from the outside and generating an internal voltage to be supplied to a predetermined internal circuit;
The self-refresh control circuit is deactivated when a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside. In addition, a control method of a semiconductor memory device, wherein the internal voltage generation circuit has a low capability of supplying the internal voltage, and the chip is shifted to the low power consumption mode. A stabilizing capacitor connected to the power line and storing a portion of the charge supplied to the power line;
Including a memory cell, and an internal circuit connected to the power line,
When a dedicated external control signal for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the power line and the stabilization capacitor A method of controlling a semiconductor memory device, wherein the connection is maintained and the chip is shifted to the low power consumption mode. An internal voltage generation circuit that receives a power supply voltage from the outside and generates an internal voltage to be supplied to a predetermined internal circuit including a memory cell;
An internal voltage detection circuit that detects the level of the internal voltage and controls the internal voltage generation circuit based on the detection result;
When an external control signal dedicated for shifting to a low power consumption mode other than the control signal supplied to execute the access operation of the memory cell is received from the outside, the capability of the internal voltage detection circuit is lowered. A method of controlling a semiconductor memory device, wherein the chip is shifted to the low power consumption mode. 28. The method of controlling a semiconductor memory device according to claim 27.
When the external control signal is received from outside, the absolute value of the internal voltage generated by the internal voltage generation circuit is reduced by lowering the detection level of the internal voltage in the internal voltage detection circuit, A control method for a semiconductor memory device , wherein the mode is shifted to the low power consumption mode. 28. The method of controlling a semiconductor memory device according to claim 27.
The internal voltage generation circuit includes a plurality of units for generating the internal voltage,
Some of the units, the control method of the semiconductor memory device characterized by stopping the during the low power consumption mode.

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