JPH0785677A - Semiconductor storage device and data processing system - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device capable of coping with a data retention mode in which an external power source voltage can be lowered. CONSTITUTION:This device and system are controlled so that at the time of a normal operating mode, the lowered output of a power source voltage lowering circuit 12 is supplied to an internal circuit 14 by making the power source voltage lowering circuit 12 to be in an active state with an external power source voltage monitering circuit 11 being a control means, moreover, at the time of data retention mode, the power source voltage lowering circuit 12 is made to be in a non-active state and also an external power source Vdd1 is supplied to the internal circuit 14. Thus, the coping with the data retention made in which the external power source Vdd1 can be lowered is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a technique for improving a power supply system included therein, and more particularly to a technique effectively applied to a data processing system using a battery as a power source.

[0002]

2. Description of the Related Art A power supply voltage supplied to an external terminal of a MOS-LSI is usually set to 5 V in order to maintain TPTL compatibility, but such a MOS transistor is included by thinning the gate oxide film of the MOS transistor. The operating voltage of functional modules tends to be reduced to 3.3 volts. In an LSI including a functional module whose operating voltage is set lower than the external power supply voltage, a circuit for lowering the power supply voltage supplied from the outside is required. I am calling it.

By the way, in a DRAM (dynamic random access memory) including a dynamic memory cell, a part of 16MDRAM and 4MDRAM is provided with the power supply voltage down circuit as described above (for example, "HM511610" etc.).

As an example of a document describing a step-down circuit for stepping down a power supply voltage supplied from the outside, an example of a document "DRAM suitable for burn-in" issued by the Institute of Electronics, Information and Communication Engineers on November 21, 1991 is given. There is a voltage limiter.

[0005]

However, in the conventional DRAM having a built-in power supply step-down circuit, there is no data retention mode, and the current consumption in the data holding state is as high as 500 μA (the refresh time is 256).
ms), especially when applied to a battery-powered system. FIG. 9 shows the breakdown of the current consumption in that case. As shown in the figure, the current consumed by the power supply step-down circuit is 60% or more of the whole, so in order to reduce the current consumption during data retention,
First, the present inventor has found that it is necessary to reduce the current consumption of the power supply step-down circuit.

Further, in a DRAM mounted in a system capable of operating with a battery as a power source, such as a portable personal computer, there is a strong demand for a data retention mode for battery backup of internal information. As a result of a study made by the inventor, in a DRAM having a built-in power supply step-down circuit such as 16M DRAM, the external power supply voltage is 5
It was revealed that when the voltage drops from about 3 to about 3 when the battery is backed up, the power down circuit becomes inoperable, resulting in difficulty in data retention.

An object of the present invention is to provide a semiconductor memory device capable of coping with a data retention mode in which an external power supply voltage is lowered. Another object of the present invention is to reduce the current consumption of such a semiconductor memory device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a step-down means for stepping down the external power supply voltage to a predetermined voltage level, and a step-down output of the step-down means is supplied to a storage section while the step-down means is activated in the normal operation mode, and is supplied in the data retention mode. A semiconductor memory device is configured to include a control unit for controlling the voltage lowering unit to be inactive and supplying an external power supply voltage to the memory unit. At this time, the control means monitors the external power supply voltage and
When the external power supply voltage is lowered to a predetermined level, the external power supply voltage monitor circuit is configured to inactivate the step-down means and assert an internal control signal for supplying the external power supply voltage to the storage section. can do. Further, the control means includes a determination circuit that determines an external control signal to deactivate the step-down means and asserts an internal control signal for supplying an external power supply voltage to the storage section. You can also Furthermore, in a data processing system that can operate using a battery as a power source,
The semiconductor memory device configured as described above can be applied.

[0011]

According to the above-mentioned means, the control means activates the step-down means in the normal operation mode to supply the step-down output of the step-down means to the storage section, and deactivates the step-down means in the data retention mode. And operates to supply the external power supply voltage to the storage section. This makes it possible to deal with the data retention mode in which the external power supply voltage is lowered. In addition, deactivating the voltage lowering means in such control acts to reduce the current consumption of the semiconductor memory device.

[0012]

FIG. 1 shows a DRAM which is an embodiment of the present invention.

Although not particularly limited, the DRAM shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, and a battery is used as a power source like a portable personal computer. Will be installed in the system. Such a system has a data retention mode for battery backup of internal information, and the external power supply Vdd1 in that case is lowered from 5 V in normal operation to about 3 V. The internal circuit 14 includes a storage section formed of dynamic memory cells and its peripheral circuits, as described later in detail. Such an internal circuit 14 has an operating voltage of 3.3 V, which is lower than the external power supply Vdd1 due to the thinning of the gate oxide film of the MOS transistor. Such internal power supply Vd
d2 is a power supply step-down circuit 12 that steps down the external power supply Vdd1
And is supplied to the internal circuit 14 in the normal operation mode.

According to the prior art, the external power supply Vdd1 is
From 5 volts during normal operation to 3 during battery backup
When the voltage drops to about the volt level, the power supply step-down circuit 12 becomes inoperable, and as a result, data retention becomes difficult. However, in the present embodiment, the power supply step-down circuit 12 is activated in the normal operation mode. The step-down output of the power supply step-down circuit 12 is supplied to the internal circuit 14,
The above inconvenience is eliminated by providing a control means for controlling the power supply voltage down circuit 12 to be inactive in the data retention mode and supplying the external power supply Vdd1 to the internal circuit 14. The control means monitors the external power supply Vdd1 and monitors the external power supply Vd1.
The external power supply voltage monitor circuit 11 configured to assert the internal control signal DR * (* indicates signal inversion or low active) at a low level when d1 is lowered to a predetermined level is applied. When the internal control signal DR * is asserted to the low level, the power supply voltage down circuit 12 is deactivated, and the switch circuit 13 is turned on, so that the internal circuit 14 has an external power supply instead of the internal power supply Vdd2. Vdd1 is supplied. The external power supply Vdd1 at the time of data retention is not particularly limited, but is set to about 3 V to enable the operation of the internal circuit 14.

FIG. 2 shows a configuration example of the power supply voltage down circuit 12 and the switch circuit 13.

N-channel type MOS transistor Q13
And n-channel MOS transistor Q14 are differentially coupled, and their source electrodes are coupled to ground GND through n-channel MOS transistor Q15.
The reference voltage VL is applied to the gate electrode of the n-channel type MOS transistor Q14, and the internal power supply Vdd2 which is the output of the power supply step-down circuit 12 is fed back to the gate electrode of the n-channel type MOS transistor Q13. ing. N-channel type MOS transistor Q13 and n-channel type MOS transistor Q
The drain electrode of 14 is coupled to the external power supply Vdd1 via a p-channel MOS transistor Q11 and a p-channel MOS transistor Q12, respectively, and an n-channel MOS transistor Q13 and an n-channel M transistor are connected.
The differential output of the OS transistor Q14 is an n-channel type M
It is obtained from the drain side of the OS transistor Q14. This differential output is transmitted to the p-channel type MOS transistor Q17 in the subsequent stage. p-channel type MOS transistor Q17, n-channel type MOS transistor Q18,
The n-channel MOS transistor Q19 is connected in series between the external power supply Vdd1 and the ground GND, and the internal power supply V is connected from the coupling point of the p-channel MOS transistor Q17 and the n-channel MOS transistor Q18.
dd2 is obtained. Internal power supply Vdd2 and ground GND
A series circuit of a resistor R and a capacitor C for reducing noise on the power supply line is inserted between the and.

Although not particularly limited, a p-channel type MOS transistor Q20 which is on / off controlled by the internal control signal DR * is applied to the switch circuit 13. The internal control signal DR * is an n-channel MOS transistor Q15, a p-channel MOS transistor Q1.
6, n-channel type MOS transistor Q19 and p-channel type MOS transistor Q20 are applied to the gate electrodes. When the internal control signal DR * is at high level, the n-channel type MOS transistor Q1
5, the n-channel type MOS transistor Q19 is turned on, and the p-channel type MOS transistor Q16,
The p-channel MOS transistor Q20 is turned off. In such a state, the power supply step-down circuit 12 is activated and the internal power supply Vdd2 corresponding to the reference voltage VL is supplied.
Are formed and are supplied to the internal circuit 14.

On the other hand, when the external power supply Vdd1 is lowered to a predetermined monitor level as shown in FIG. 4, the external power supply voltage monitor circuit 11 asserts the internal control signal DR * at a low level, As a result, the n-channel type MOS transistor Q15 and the n-channel type MOS transistor Q19 are turned off, and the p-channel type MOS transistor Q16 and the p-channel type MO transistor Q16.
The S transistor Q20 is turned on. n-channel MOS transistor Q15, n-channel MOS
By turning off the transistor Q19 and turning on the p-channel type MOS transistor Q16, the power supply step-down circuit 12 is deactivated, thereby significantly reducing the current consumption. Further, when the p-channel MOS transistor Q20 is turned on, the external power supply Vdd1 is replaced by the internal circuit 1 instead of the internal power supply Vdd2.
4 can be supplied to the power supply terminal. The external power supply Vdd
The period T11 from 1 being lowered until it reaches a predetermined holding voltage depends on the system specifications.

FIG. 3 shows a structural example of the internal circuit 14.

Reference numeral 24 is a memory cell array in which a plurality of dynamic memory cells are arranged in a matrix. Select terminals of the memory cells are connected to word lines in each row direction, and data input terminals of the memory cells are arranged in each column direction. Coupling to complementary data lines. Each complementary data line is commonly connected to the complementary common data line via a Y selection switch circuit 27 including a plurality of column selection switches which are coupled to the complementary data line in a one-to-one relationship. Although not particularly limited, an address multiplex system is adopted, and row and column address input signals are taken in from a common address terminal by shifting their timings. That is, the X address latch and X decoder 22
An address multiplexer 21 is arranged in front of the Y address latch and Y decoder 26, and an address signal taken in through the address buffer 20 is transferred by the address multiplexer 21 to the X address latch and X decoder 22 and the Y address latch. And the Y decoder 26. In order to smoothly perform such address input, two types of clock signals, RAS * (row address strobe) and CAS * (column address strobe), are applied from the outside. Since only one read or write operation is possible during one memory cycle (one cycle of the RAS * clock), the row address is at the falling edge of the RAS * clock and the column address is at the falling edge of the CAS * clock. Are taken into the internal circuit, and it is possible to judge whether the relevant cycle is a write cycle or a read cycle depending on the state of the write enable signal WE *. The control unit 25 performs such determination and operation control of each unit.

The word driver 23 drives the word line to the selection level based on the decoding of the X address latch and the X decoder arranged in the preceding stage. Then, the Y selection switch circuit 27 is driven based on the Y address latch and the decoded output of the Y decoder 26, thereby enabling data read or data write from the specified memory cell.

A sense amplifier 29 is coupled to the memory cell array 24 so that the memory cell information is amplified by this sense amplifier. In this case, the data input / output circuit 28 includes a main amplifier and the like, and the read data can be externally transmitted via the main amplifier.

According to this embodiment, the following operational effects can be obtained.

(1) By the external power supply voltage monitor circuit 11 as the control means, the power supply voltage down circuit 1 in the normal operation mode
2 is activated to supply the step-down output of the power supply step-down circuit 12 to the internal circuit 14. The power supply step-down circuit 12 is deactivated in the data retention mode and the external power supply Vdd1 is supplied to the internal circuit 14. Therefore, it is possible to cope with the data retention mode in which the external power supply Vdd1 is lowered.

(2) Further, as shown in FIG. 9, since the current consumed by the power supply step-down circuit is 60% or more of the whole, the power supply step-down circuit 1 is controlled by the above-mentioned control.
By making 2 inactive, the current consumption of the DRAM at the time of data retention is greatly reduced, which is particularly advantageous in a system using a battery as a power source. Current consumption is 2 / compared with conventional DRAM
It has been confirmed by the present inventor that the number is reduced to 5. In addition, considering that the power supply voltage is reduced to 3/5, the power consumption during data retention is
It is reduced to 1/5 of RAM {(≈ (2/5) × (3/5)}. Such an effect is a low current designed DRAM.
Is remarkable in.

(3) Power supply step-down circuit 1 in the normal operation mode
2 is activated to supply the step-down output of the power supply step-down circuit 12 to the internal circuit 14 to deactivate the power supply step-down circuit 12 in the data retention mode and to supply the external power supply Vdd1 to the internal circuit 14. By applying the external power supply voltage monitor circuit 11 as the above, the transition from the normal operation mode to the data retention mode can be accurately detected based on the fluctuation of the external power supply Vdd1, and the control is ensured.

FIG. 5 shows another embodiment of the present invention.

In FIG. 5, the power supply step-down circuit 12 is activated in the normal operation mode to supply the step-down output of the power supply step-down circuit 12 to the internal circuit 14, and the power supply step-down circuit 12 is deactivated in the data retention mode. The control means for supplying the external power supply Vdd1 to the internal circuit 14 is formed by the mode determination circuit 51 and the timer 52. The mode determination circuit 51 detects an external control signal, for example, a signal (capacitor CB resistance R) waveform for realizing an automatic refresh mode. Then, as shown in FIG. 6, when CAS * and RAS * are asserted to the low level, the timer 52 is operated in synchronization with the falling waveform edge of the RAS *. Timer 52
Asserts the internal control signal DR * to a low level after a period T13 preset according to the specifications has elapsed. By asserting the internal control signal DR * to low level,
As in the case of the above embodiment, the power supply step-down circuit 12 is deactivated and the switch circuit 13 is turned on, so that the external power supply Vdd1 lowered by the data retention mode is replaced by the internal power supply Vdd2. Circuit 1
4 is supplied. The period T13 is C in the system.
It is determined in consideration of the time from the assertion of the BR signal to the transition to the data retention mode. Therefore, if the data retention mode is set at the same time as the assertion of the CBR signal, it is not necessary to set the period T13, and thus the timer 52 is unnecessary.

Thus, the mode determination circuit 51 and the timer 5 are
2 is provided and the internal control signal DR * is asserted, the same effect as the above embodiment can be obtained.

Further, in the above embodiment, the switch circuit 1
Although the p-channel MOS transistor Q20 is applied to the inverter 3 described above, an inverter 71 for inverting the internal control signal DR * and an n-channel MOS transistor whose operation is controlled by its output are shown in FIG.
It can also be formed by the transistor Q70.
In this case, by applying a p-channel type MOS transistor Q70 having a low threshold voltage,
It is advisable to suppress the voltage drop there as much as possible. In addition, as shown in FIG.
The transistor Q20 and the n-channel type MOS transistor Q70 can be connected in parallel with each other. Even with this configuration, the function of the switch circuit 13 is achieved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and it goes without saying that various modifications can be made without departing from the gist of the invention. Yes.

For example, when the chip enable signal capacitor CE * is at the high level and the output enable signal OE * is asserted at the low level, the normal operation mode is switched to the data retention mode. The mode change circuit 51 may detect a change in the state of the control signal. Alternatively, the DRAM may be provided with a dedicated refresh terminal, and the mode determination circuit 51 may detect the signal level transmitted from the system to the dedicated terminal to deal with the mode transition.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
Although the case of application to M has been described, the present invention is not limited thereto, and can be widely applied to various semiconductor memory devices and various data processing devices such as microcomputers incorporating the same.

The present invention can be applied on condition that at least a power supply system for supplying power to the storage unit is included.

[0035]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, in the normal operation mode, the step-down means is activated to supply the step-down output of the step-down means to the memory section, and in the data retention mode, the step-down means is deactivated and the external power supply voltage is supplied to the memory section. Thus, it is possible to cope with the data retention mode in which the external power supply voltage is lowered. Further, in such control, the step-down means is inactivated, so that the current consumption of the semiconductor memory device and further the power consumption thereof are significantly reduced.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of a DRAM according to an embodiment of the present invention.

FIG. 2 is an electrical connection diagram of a power supply step-down circuit and a switch circuit included in the DRAM.

FIG. 3 is a configuration block diagram of an internal circuit included in the DRAM.

FIG. 4 is a timing diagram for explaining an operation of a power supply system included in the DRAM.

FIG. 5 is a configuration block diagram of a DRAM according to another embodiment of the present invention.

6 is a timing chart for explaining an operation of a power supply system included in the DRAM shown in FIG.

FIG. 7 is an electrical connection diagram of a main part of a DRAM according to another embodiment of the present invention.

FIG. 8 is an electrical connection diagram of a main part of a DRAM according to another embodiment of the present invention.

FIG. 9 is an explanatory diagram of current consumption in a conventional DRAM.

[Explanation of symbols]

 11 External Power Supply Voltage Monitor Circuit 12 Power Supply Step-Down Circuit 13 Switch Circuit 14 Internal Circuit 51 Mode Judgment Circuit 52 Timer 71 Inverter Q11 p-channel MOS Transistor Q12 p-channel MOS Transistor Q13 n-channel MOS Transistor Q14 n-channel MOS Transistor Q15 n Channel MOS transistor Q16 p-channel MOS transistor Q17 p-channel MOS transistor Q18 n-channel MOS transistor Q19 n-channel MOS transistor Q20 p-channel MOS transistor Q70 n-channel MOS transistor Q81 p-channel MOS transistor Q82 n-channel type MOS transistor R resistance C capacitor Vdd1 external Source Vdd2 internal power DR * internal control signal

Claims (6)

[Claims] 1. In a semiconductor memory device including a storage unit for storing data and a power supply system for supplying power to the storage unit, the power supply system lowers an external power supply voltage to a predetermined voltage level. And the step-down means for activating the step-down means in the normal operation mode to supply the step-down output of the step-down means to the storage section. A semiconductor memory device comprising: a control unit for controlling the supply to the storage unit. 2. The control means monitors the external power supply voltage and, when the external power supply voltage is lowered to a predetermined level, deactivates the step-down means and stores the external power supply voltage in the storage section. 2. The semiconductor memory device according to claim 1, further comprising an external power supply voltage monitor circuit that asserts an internal control signal for supply. 3. The control means includes a determination circuit for determining an external control signal to deactivate the step-down means and asserting an internal control signal for supplying an external power supply voltage to the storage section. Item 2. The semiconductor memory device according to item 1. 4. A first control transistor for deactivating the step-down means when the internal control signal is asserted, and the external power supply voltage for storing the external power supply voltage when the internal control signal is asserted. And a second control transistor for applying to a power supply terminal of the device.
The semiconductor memory device described. 5. The semiconductor memory device according to claim 1, wherein the memory section includes a dynamic memory cell. 6. A data processing system including a battery for supplying the external power supply voltage, and the semiconductor memory device according to claim 1, 2, 3, 4 or 5.