JPH06275076A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a semiconductor memory device in a waiting state. CONSTITUTION:The read and write operation by a memory cell array and a peripheral circuit 3, and the waiting state performing no write and no read operation are set based on control signals RAS' and CAS'. First and second voltage supply circuits 4, 5 or first and second current supply circuits 8, 9 are interposed between the memory cell array and the peripheral circuit 3 with power source Vcc through a selection circuit 6. A control signal detection circuit 7 selecting the voltage or current supply circuits 4, 8 by the selection circuit 6 when the write and read operation are set, and selecting the second voltage or current supply circuits 5, 9 by the selection circuit 6 when the waiting state is set is provided. In the waiting state, the voltage supplied to the memory cell array and the peripheral circuit 3 is stepped down, or the current is suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power consumption reduction circuit for reducing power consumption of a semiconductor memory device.

In recent years, various semiconductor memory devices have come to be used also in portable electronic devices. In such electronic devices, the battery capacity has been reduced in order to reduce the size and weight. Therefore, it is necessary to reduce the power consumption of the semiconductor memory device used in such a portable electronic device.

[0003]

2. Description of the Related Art Conventionally, in order to reduce the power consumption of a semiconductor memory device, measures have been mainly taken to reduce the power consumption in a standby state. That is, in the normal usage of the semiconductor memory device, the time in the standby state waiting for the control signal for performing the data write operation and the data read operation is longer than the time in the active state in which the data write operation or the data read operation is performed.

In an SRAM, for example, a current flows in each memory cell in the cell array even in the standby state, and some peripheral circuits of the cell array must always maintain the active state, which consumes the current.

In addition, some DRAMs consume current for the refresh operation of cell information even in the standby state, and some peripheral circuits of the cell array need to be kept active at all times as in the SRAM. Is consumed.

Therefore, in the above semiconductor memory device, a measure has been taken to reduce the power consumption mainly by suppressing the current consumption in the standby state.

[0007]

In the semiconductor memory device as described above, the power consumption in the standby state has been reduced to almost the limit by the above measures.

However, in order to reduce the battery capacity, it is necessary to further reduce the power consumption of the semiconductor memory device. An object of the present invention is to further reduce the power consumption of the semiconductor memory device in the standby state.

[0009]

FIG. 1A is an explanatory view of the principle of the invention of claim 1. That is, a write operation and a read operation by the memory cell array and the peripheral circuit 3,
The standby state where the write operation and the read operation are not performed,
In the semiconductor memory device set based on the control signals RAS and CAS, a first voltage supply circuit 4 having a small voltage drop and a voltage drop between the memory cell array and the peripheral circuit 3 and the power supply Vcc. Large second voltage supply circuit 5
And the control signal RAS via the selection circuit 6.
When the write operation and the read operation are set by the bar and CAS bar, the selection circuit 6 selects the first voltage supply circuit 4, and the control signals RAS and CAS set the standby state. At this time, the control signal detection circuit 7 for selecting the second voltage supply circuit 5 by the selection circuit 6
Is provided.

FIG. 1B is an explanatory view of the principle of the invention of claim 2. That is, in the semiconductor memory device, the write operation and the read operation by the memory cell array and the peripheral circuit 3 and the standby state in which the write operation and the read operation are not performed are set based on the control signals RAS bar and CAS bar. And a first current supply circuit 8 having a large supply current between the peripheral circuit 3 and the power supply Vcc,
The second current supply circuit 9 having a small supply current is the selection circuit 6
When the write operation and the read operation are set by the control signals RAS and CAS, the selection circuit 6 selects the first current supply circuit 8, and the control signal RAS and A control signal detection circuit 7 is provided for selecting the second current supply circuit 9 by the selection circuit 6 when the standby state is set by the CAS bar.

Further, as shown in FIG. 2, the first voltage supply circuit and the selection circuit are composed of an N-channel MOS transistor Tr1 connected between the power source Vcc and the memory cell array and the peripheral circuit 3, and The second voltage supply circuit and the selection circuit are two N-channel MO connected in series between the power source Vcc and the memory cell array and the peripheral circuit 3.
The control signal detection circuit 7 is composed of S-transistors Tr2 and Tr3, and the control signal detection circuit 7 turns on the transistor Tr1 when the control signals RAS and CAS are both at the H level for a predetermined time or longer, and otherwise, the transistor Tr2. , Tr3 is turned on.

[0012]

According to the first aspect of the present invention, during the write operation and the read operation, the memory cell array and the peripheral circuit 3 are supplied with the power supply voltage from the first voltage supply circuit to perform the write operation and the read operation.

In the standby state, the memory cell array and the peripheral circuit 3 are supplied with a power supply voltage lower than the power supply voltage supplied during the write operation and the read operation from the second voltage supply circuit, and the power consumption is reduced.

In the second aspect, during the write operation and the read operation, the current is supplied to the memory cell array and the peripheral circuit 3 from the first current supply circuit, and the write operation and the read operation are performed.

In the standby state, the memory cell array and the peripheral circuit 3 are supplied with a current smaller than the current supplied during the write operation and the read operation from the second current supply circuit, and the power consumption is reduced.

In the third aspect, the control signal detection circuit 7 turns on the N-channel MOS transistor Tr1 during the write operation and the read operation, and the power source Vcc is supplied to the memory cell array and the peripheral circuit 3 through the transistor Tr1. To be done.

On the other hand, in the standby state, the N-channel MOS transistors Tr2 and Tr3 are turned on, the power supply Vcc is stepped down by the threshold value of the transistors Tr2 and Tr3 and supplied to the memory cell array and the peripheral circuit 3.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIG.
Follow the instructions below. FIG. 2 shows a power consumption reduction circuit for reducing the power consumption of the semiconductor memory device in the standby state.

The control signals RAS bar and CAS bar are used as signals for controlling the operation of the semiconductor memory device. In the standby state of the semiconductor memory device, the control signals RAS bar and CAS bar are both at H level. Becomes

The control signals RAS and CAS are N
It is input to the AND circuit 1a. The NAND circuit 1a
Is output to the NAND circuit 1b through the inverter circuit 2a and the even-numbered stages of the inverter circuit 2
It is input to the NAND circuit 1b via b and 2c.

The output signal of the NAND circuit 1b is input to the gates of the N-channel MOS transistors Tr1 via the inverter circuits 2d and 2e, and to the gates of the N-channel MOS transistors Tr2 and Tr3 via the inverter circuit 2d. .

In the memory cell array and the peripheral circuit 3, the transistor Tr1 or the transistors Tr2, T is provided.
The power supply Vcc is supplied via r3. That is, the power supply Vcc is supplied to the drain of the transistor Tr1, and the source of the transistor Tr1 is the memory cell array and the peripheral circuit 3.
Is connected to the power supply line of.

A power supply Vcc is supplied to the drain of the transistor Tr2, the source of the transistor Tr2 is connected to the drain of the transistor Tr3, and the transistor Tr3 is connected.
Is connected to the memory cell array and the power supply line of the peripheral circuit 3. The transistors Tr1 to T
The threshold value of r3 is the same.

Next, the operation of the power consumption reduction circuit thus constructed will be described. Now, in the active state in which the write operation and the read operation are performed, both the control signals RAS bar and CAS bar do not constantly become H level. That is, if at least one of the control signals RAS and CAS is at L level, the NAND circuit 1a
The output signal of becomes H level.

Then, the output signal of the inverter circuit 2a becomes L level, the output signal of the NAND circuit 1b becomes H level, the output signal of the inverter circuit 2d becomes L level,
The output signal of the inverter circuit 2e becomes H level.

As a result, the transistor Tr1 is turned on, the transistors Tr2 and Tr3 are turned off, and the memory cell array and the peripheral circuit 3 are supplied with the voltage reduced from the power source Vcc by the threshold value Vth of the transistor Tr1 as a power source. .

Therefore, the circuit configuration from the NAND circuit 1a to the inverter 2d constitutes a detection circuit for detecting whether or not the control signals RAS and CAS are both at the H level for a predetermined time or longer.

The transistors Tr1 to Tr3 form a voltage supply circuit for supplying different power supply voltages to the memory cell array and the peripheral circuit 3, and the inverter circuit 2e and the transistors Tr1 to Tr3 select the voltage supply circuit. Is configured.

On the other hand, when both the control signals RAS and CAS become H level, the output signal of the NAND circuit 1a becomes L level and the output signal of the inverter circuit 2a becomes H level.

Here, the control signals RAS, CAS
The bar is over a certain time, that is, the inverter circuits 2b, 2
When the H level is maintained for the operation delay time of c or longer, both the input signals of the NAND circuit 1b become the H level.

Then, the output signal of the NAND circuit 1b is L
The output signal of the inverter circuit 2d becomes H level, and the output signal of the inverter circuit 2e becomes L level.
As a result, the transistor Tr1 is turned off, the transistors Tr2 and Tr3 are turned on, and the memory cell array and the peripheral circuit 3 have two stages of transistors Tr from the power source Vcc.
2, a voltage lowered by the threshold value 2Vth of Tr3 is supplied as a power source.

As described above, in the power consumption reducing circuit, both the control signals RAS and CAS are not at the H level for a certain time, that is, in the active state of the semiconductor memory device, the memory cell array and the peripheral circuit 3 are provided. Is supplied from the power source Vcc as a power source with a voltage lowered by the threshold value Vth of the transistor Tr1.

When the semiconductor memory device is in a standby state and both the control signals RAS and CAS are at the H level for a certain time or more set by the inverter circuits 2b and 2c, the memory cell array and the peripherals. The circuit 3 is supplied with a voltage lower than the power supply Vcc by the threshold value 2Vth of the transistors Tr2 and Tr3 as a power supply.

Therefore, in the standby state, the power supply voltage supplied to the memory cell array and the peripheral circuit 3 can be made lower than that in the active state to reduce the power consumption. In the above embodiment, the threshold voltage of the transistors Tr1 to Tr3 is used to adjust the power supply voltage supplied to the memory cell array and the peripheral circuit 3.
It may be configured to adjust the current supplied to the.

In this case, for example, transistors of different sizes are used for the power supply Vcc, the memory cell array and the peripheral circuit 3.
The current can be adjusted by interposing the transistor and the transistor and selectively turning on the transistor.

[0036]

As described above in detail, the present invention exhibits an excellent effect that the power consumption of the semiconductor memory device in the standby state can be further reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing an embodiment of the present invention.

[Explanation of symbols]

 3 peripheral circuit and cell array 4 first voltage supply circuit 5 second voltage supply circuit 6 selection circuit 7 control signal detection circuit 8 first current supply circuit 9 second current supply circuit RAS bar, CAS bar control signal Vcc power supply

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location 6866-5L G11C 11/34 371 G

Claims (3)

[Claims] 1. A control signal (RAS) for controlling a write operation and a read operation by a memory cell array and a peripheral circuit (3) and a standby state in which the write operation and the read operation are not performed.
A memory cell array and peripheral circuit (3) and a power supply (Vc).
Between c), a first voltage supply circuit (4) with a small voltage drop and a second voltage supply circuit (5) with a large voltage drop.
When the control signal (RAS bar, CAS bar) sets the write operation and the read operation, the first voltage supply circuit (1) and the second voltage supply circuit (6) are interposed by the selection circuit (6). 4) is selected, and the control signal (R
A control signal detection circuit (7) for selecting the second voltage supply circuit (5) by the selection circuit (6) when the standby state is set for the AS bar and the CAS bar) is provided. Semiconductor memory device. 2. A control signal (RAS) for controlling a write operation and a read operation by the memory cell array and the peripheral circuit (3) and a standby state in which the write operation and the read operation are not performed.
A memory cell array and peripheral circuit (3) and a power supply (Vc).
Between c), a first current supply circuit (8) having a large supply current and a second current supply circuit (9) having a small supply current.
When the control signal (RAS bar, CAS bar) sets the write operation and the read operation with the intervening and through the selection circuit (6), the selection circuit (6) causes the first current supply circuit ( 8) to select the control signal (R
A control signal detection circuit (7) for selecting the second current supply circuit (9) by the selection circuit (6) when the standby state is set for the AS bar and the CAS bar) is provided. Semiconductor memory device. 3. The first voltage supply circuit and the selection circuit,
An N-channel MOS transistor (Tr1) connected between a power source (Vcc) and the memory cell array and peripheral circuit (3). The second voltage supply circuit and the selection circuit are provided with a power source (Vcc) and the memory. Two N-channel MOSs connected in series between the cell array and the peripheral circuit (3)
The control signal detecting circuit (7) turns on the transistor (Tr1) when the control signals (RAS bar, CAS bar) are both at the H level for a certain period of time or more. 2. The semiconductor memory device according to claim 1, wherein the transistors (Tr2, Tr3) are turned on at other times.