JPH1145563A - Semiconductor integrated circuit and semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit technique capable of preventing a malfunction by executing initialization and deciding the potential of a floating node of an internal circuit without the input of an RAS or CAS signal from the outside. SOLUTION: A semiconductor chip is internally provided with a power source voltage level detecting circuit 11 for detecting the level of a power source voltage, a pulse generating circuit 12 and a counter circuit 13. The semiconductor integrated circuit is so constituted that the clock formed by the pulse generating circuit 12 after the detection of the rise of the power source voltage is inputted to the circuit for receiving the signal, such as RAS signal or CAS signal, subjected to the initialization regulation by as much as a prescribed number of pulses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit technology, and more particularly to a technology effective when applied to a power-on initialization in a semiconductor integrated circuit.
The present invention relates to a technique which is effective when used in a semiconductor memory device having an address latch circuit such as a (dynamic random access memory).

[0002]

2. Description of the Related Art Address multiplex type semiconductor memories and synchronous memories, such as dynamic RAMs (hereinafter referred to as DRAMs), have a large number of input latch circuits and flip-flop circuits mounted on peripheral circuits. . In such a semiconductor integrated circuit, immediately after the power is turned on, the internal nodes of the latch circuit and the flip-flop circuit, particularly the feedback loop, are in a floating state, so that the potential becomes uncertain. Then, a malfunction may occur. Therefore, for example, in the case of a DRAM, the initialization specifies immediately after power-on.

Specifically, a so-called R which performs a refresh operation only with a RAS (row address strobe) signal is used.
RA in AS-only refresh mode DRAM
As shown in FIG. 10, in a DRAM which swings the S signal for at least eight cycles (one cycle is about 100 ns), and in which the CAS (column address strobe) signal falls before the RAS signal, the DRAM enters the refresh mode. It is stipulated that the CAS signal be swung for eight cycles or more. As a result, in the DRAM, the potential of the floating node in the latch circuit or flip-flop circuit is determined by performing the refresh operation, and a malfunction is prevented when a normal signal is input thereafter.

[0004]

The above-mentioned conventional initialization system is a system in which a clock of a RAS or CAS signal is inputted from the outside. Therefore, the clock of the RAS or CAS signal must be formed by an external circuit. There has been a technical problem that a user who uses the memory has a large design burden and leads to an increase in system cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit technology capable of performing initialization without externally inputting a clock of a RAS or CAS signal, determining the potential of a floating node of an internal circuit, and preventing malfunction. Is to provide.

Another object of the present invention is to provide a semiconductor integrated circuit technology capable of reducing the design burden on the user and reducing the cost of the system.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a power supply voltage level detection circuit for detecting a power supply voltage level, a pulse generation circuit and a counter circuit are provided inside a semiconductor chip, and after the rise of the power supply voltage is detected, the pulse generation circuit is formed. A signal (pulse or clock) is configured to be input to a required circuit by a predetermined number of pulses. here,
The required circuit is, in the DRAM, an internal circuit such as a timing control circuit or an address buffer circuit that receives a signal for which initialization such as a RAS signal or a CAS signal is specified.

According to the above-mentioned means, since it is not necessary to input a signal for initialization from the outside when the power is turned on, the design burden on the user can be reduced and the cost of the system can be reduced.

In the above case, there is provided a selection circuit for selectively supplying either a signal for which initialization is prescribed, such as a RAS or CAS signal, or a signal generated by the pulse generation circuit. Preferably, the selection circuit is controlled by the output of a counter circuit that counts the number of pulses of the signal from the generation circuit so that a predetermined number of pulses of the signal from the pulse generation circuit are supplied to a required circuit when the power is turned on. As a result, it is only necessary to add the initialization circuit of the present invention without making any change to the conventional circuit, and the design can be changed very easily.

The pulse generating circuit may be configured so that the operation thereof is stopped after the selection circuit cuts off the supply of the signal from the pulse generating circuit at the output of the counter circuit. Thus, an increase in power consumption can be prevented.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of an initialization circuit 10 according to the present invention. In FIG. 1, reference numeral Vcc denotes a power supply voltage externally supplied to the semiconductor chip, 11 denotes a power supply voltage level detection circuit for detecting the level of the power supply voltage Vcc, and 12 denotes a clock having a predetermined pulse width. The generated pulse generating circuit, 13 is a counter circuit for counting the number of pulses of the clock RPLB generated by the pulse generating circuit 12, and 14 is an initialization rule for the clock RPLB or an externally supplied RAS signal or CAS signal. And a selection circuit (selector) for selecting one of the signals and supplying the selected signal to an internal circuit.

Next, the initialization circuit 10 of the present embodiment
Will be described with reference to the timing chart of FIG.

In this embodiment, when the power supply voltage Vcc is supplied and gradually rises and reaches a predetermined detection level Vref, the power supply voltage level detection circuit 11 detects the power supply voltage Vcc and the output SETB changes from a high level to a low level. Since the power supply voltage level detection circuit 11 is also driven by the power supply voltage Vcc supplied to the chip from the outside,
As the power supply voltage rises, its output SETB rises,
When the power supply voltage Vcc reaches the detection level Vref, it changes to a low level. Since the pulse generation circuit 12 is also driven by the power supply voltage Vcc, the oscillation operation is enabled as the power supply voltage rises, and the output is once set to a high level. SET
The oscillation operation starts when B changes from the high level to the low level.

The clock generated by the pulse generating circuit 12 is counted by a counter circuit 13, and the counter circuit 1
When 3 counts a predetermined number of pulses (for example, 7), the output signal CF changes from low level to high level.
The counter circuit 13 is configured such that its output signal CF is initially at a low level, and the selection circuit 14 controlled by this signal CF is brought into a state of supplying the clock RPLB output from the pulse generation circuit 11 to an internal circuit. It is configured to: Therefore, immediately after the power supply voltage Vcc rises and the pulse generation circuit 11 starts oscillating, the output clock RPLB is supplied to the internal circuit. And, in the internal circuit, this clock RPLB is 7
While supplied over the cycle, the potential of the floating node of the latch circuit or flip-flop circuit is determined.

On the other hand, when the counter circuit 13 counts seven pulses of the clock generated by the pulse generation circuit 12, the output signal CF changes from the low level to the high level. Therefore, the selection circuit 14 controlled by the signal CF is used.
Is the clock RP output from the pulse generation circuit 11
The LB is cut off, and an RAS signal or the like input from the outside is supplied to the internal circuit instead. As a result, the chip enters a normal operating state. As a result, there is no need to input a signal for initialization from the outside when the power is turned on, so that the design burden on the user is reduced and the cost of the system can be reduced.

In this embodiment, the output signal CF of the counter circuit 13 is also supplied to the pulse generation circuit 12, and when the output signal CF of the counter circuit 13 changes to a high level, the oscillation of the pulse generation circuit 12 is started. The operation is configured to be stopped. This can prevent an increase in power consumption due to the provision of the initialization circuit 10.

FIG. 3 shows a specific embodiment of the pulse generation circuit 12. The pulse generation circuit of this embodiment includes inverters INV1 to INV5 connected in cascade and delay circuits DELAY1 and DELAY2, and the output of the last inverter INV5 is the first inverter INV5.
A ring oscillator OSC connected so as to be fed back to the input of V1, an output signal SETB from the power supply voltage level detection circuit 11, and an output signal C from the count circuit 13
The control circuit includes an exclusive OR gate G1 having F as an input signal and an inverter INV0 for inverting the output of the exclusive OR gate G1.

The p-channel MOSFET Q1 and the n-channel MO constituting the last-stage inverter INV5
N channel MOSFET Q between SFET Q2
3 are connected in series and the inverter I
A p-channel MOSFET Q4 is connected between the output node No of NV5 and the power supply voltage Vcc.
The output signal of the inverter INV0 of the control circuit is supplied to the gate terminals of the FETs Q3 and Q4. When the power is turned on, as described above, the output signal CF from the count circuit 13 is at a low level. Therefore, when the output signal SETB from the power supply voltage level detection circuit 11 is at a high level, the output of the inverter INV0 is at a low level. ,
The MOSFET Q3 is turned off, the Q4 is turned on, the ring oscillator OSC does not oscillate, and the output of the pulse generation circuit 12 is set to high level.

When the level of the power supply voltage Vcc rises and reaches a predetermined level, the output signal SETB from the power supply voltage level detection circuit 11 changes to a low level, so that the output of the inverter INV0 changes to a high level and the MOSF
ET Q3 is turned on and Q4 is turned off, and the ring oscillator OSC starts oscillating. Therefore, the inverter I
NV1 to INV5 and delay circuits DELAY1, DEL
After a time T1 determined by the delay time of AY2, the output of the ring oscillator OSC changes to the high level, and thereafter, the inversion is repeated every T1. When the output of the pulse generation circuit 12 has been inverted for seven cycles, the counter circuit 13
Changes to a high level, the inverter I
The output of NV0 changes to low level and MOSFET Q
3 is turned off, Q4 is turned on, the ring oscillator OSC stops oscillating, and the output is fixed at a high level.

FIG. 4 shows delay circuits DELAY1, DELAY.
2 is shown below. Delay circuits DELAY1, DELAY
2 are inverters INV11, INV12, NAN, respectively.
It comprises a D gate G2, an inverter INV13, and capacitors C1 and C2 connected to output terminals of the inverters INV11 and INV12, respectively, and resistors R1 and R2 connected between MOSFETs of the inverters INV11 and INV12, respectively. , Resistor R1,
By appropriately setting R2 and capacitances C1 and C2, R2
It is set to have a delay time determined by the time constant of 1 and C1, and the time constant of R2 and RC2. The delay circuits DELAY1 and DELAY2 have the time constants of R1 and C1 when the input IN is at a high level, and the input I
When N is at a low level, the operation is performed so that the time constants of R2 and C2 greatly contribute to the delay time. Specifically, the delay time is set so that the cycle of the formed pulse is a cycle (for example, 100 nS) corresponding to one cycle of the cycle defined in the initialization of the RAS.

FIG. 5 shows a specific example of the unit counter COUNT constituting the counter circuit 13. Each unit counter COUNT is provided with an input NAND gate G21.
And the master-slave flip-flops FF1 and F
F2, a feedback inverter G22 between the flip-flops FF1 and FF2, an output logic NAND gate G23, and an output inverter G24. RS
Is a reset terminal for permitting the operation of the circuit. In the embodiment, the output signal SETB of the power supply voltage level detection circuit 11 is inputted. When the SETB is at a low level, the signal is connected between one of the input terminals of the NAND gate G22 and the ground point. Is turned off, and the operation is enabled. Ci is a count input terminal to which the count output of the preceding unit counter is input. Input NAND gate G21
Is a two-input NAND gate and an output logic NAND gate G
23 is a three-input NAND gate.

As shown in FIG. 6, the counter circuit 13 of this embodiment is configured by cascading three unit counters COUNT of FIG.
The count input terminal Ci of NT1 is fixed at a high level "H" such as Vcc. Also, each unit counter has
The clock RPLB from the pulse generation circuit 12 is commonly input, and is input to the first-stage NAND gate G21 together with the input signal to the count input terminal Ci. The output of the NAND gate G21 and a signal obtained by inverting the output by the inverter G24 are flip-flops. It is supplied as an operation clock of FF1 and FF2. Flip-flop FF1, FF
2 is composed of two clocked inverters and one ordinary inverter. The input signal to the count input terminal Ci and the signals from the flip-flops FF1 and FF2 are input to the output logic NAND gate G23.

FIG. 7 shows a specific example of the selection circuit 14. The selection circuit of this embodiment includes a clocked inverter G having an externally input RAS signal as an input signal.
31, a clocked inverter G32 which receives the clock PRLB from the pulse generation circuit 12 as an input signal, and an inverter G3 which inverts the signal CF from the counter circuit 13
3 and a clocked inverter G3
1 and G32 operate complementarily using the signal CF and its inverted signal as a control clock, and output the RAS signal or the clock PRL.
It operates to invert any signal of B and transmit it to the internal circuit. The above clocked inverters G31, G3
2 instead of p-channel MOSFET and n-channel M
A so-called transmission gate in which OSFETs are connected in parallel may be used.

Since the circuit for detecting the power supply voltage level is conventionally generally incorporated in the DRAM, the present invention is applied to the DR.
In application to AM, it is not necessary to newly provide the power supply voltage level detection circuit 11 constituting the initialization circuit of the embodiment. As shown schematically in FIG. 8, the power supply voltage level detecting circuit basically includes a resistor voltage dividing circuit composed of resistors R11 and R12 connected in series between a power supply voltage Vcc and a ground point, and a voltage dividing circuit. And a comparator CMP for comparing the set voltage with a reference voltage Vref as a preset detection level. Heretofore, various types of power supply voltage level detection circuits have been proposed, and in the implementation of the present invention, any circuit type can be used as long as it can be formed on a semiconductor chip. can do. For example, it is possible to use the on-resistance of the MOSFET as the resistors R11 and R12 constituting the voltage dividing circuit of FIG.

FIG. 9 shows a schematic configuration of a DRAM as an example of a semiconductor integrated circuit suitable for applying the present invention. In FIG. 9, reference numeral 21 denotes a power supply terminal to which a power supply voltage Vcc supplied from the outside is applied, 22 denotes a memory array having a storage capacity of, for example, 16 Mbits, and 23A and 23B denote externally input row addresses ( An address input buffer circuit for amplifying and waveform-shaping a row address) signal and a column address (column address) signal and supplying the amplified signal to a predetermined internal circuit. Reference numeral 24 denotes a refresh counter for generating an address for refreshing a memory cell. is there. A row decoder 25 decodes an internal complementary address signal supplied from the address input buffer circuit 23A or the refresh counter 12 and selects a corresponding word line in the memory array 22.

26 is the address input buffer circuit 23
A column decoder that decodes the internal complementary address signal supplied from B and selects a corresponding bit line in the memory array 22. Reference numeral 27 denotes an I / O bus to which a sense amplifier for amplifying data read to a bit line and a plurality of bit lines are commonly connected via a column switch. Reference numeral 28 denotes a write data signal which is supplied to the memory array 22 via the sense amplifier & I / O bus 27 or the sense amplifier & I / O bus 2.
7, a data input / output buffer circuit for outputting data read from the memory array 22 to the outside through
Reference numeral 29 denotes a timing control circuit that forms a timing signal to be supplied to an internal circuit based on various control signals and a clock signal input from the outside.

The control signals externally input to the memory of this embodiment include a row address strobe signal / RAS for giving the timing of taking in a row address to the address input buffer 23A, and an address input buffer 2
A column address strobe signal / CAS for giving a timing of taking in a column address to the 3B, a write control signal / WE for indicating that writing is valid,
There is a chip select signal / CS or the like for indicating that the memory is selected. Control signals with "/" preceding each code indicate that the low level is an effective level. In this embodiment, the initialization circuit 10 of the embodiment is provided between the input terminal of the RAS signal and the timing control circuit 29.

As described above, in the above embodiment, the rise of the power supply voltage is detected by providing the power supply voltage level detection circuit for detecting the power supply voltage level, the pulse generation circuit and the counter circuit inside the semiconductor chip. After that, the signal generated by the pulse generating circuit is configured to be inputted to a circuit for receiving a predetermined number of pulses of a signal such as a RAS signal or a CAS signal for which initialization has been performed. It is not necessary to input this signal, which has the effect of reducing the design burden on the user and reducing the cost of the system.

A selection circuit is provided for selectively supplying either a signal for which initialization is specified, such as a RAS or CAS signal, or a signal generated by the pulse generation circuit, and a pulse of the signal is provided. This circuit is controlled by the output of the counter circuit that counts the number of pulses, and the signal from the pulse generation circuit is supplied to the required circuit by the predetermined number of pulses when the power is turned on. Instead, it is sufficient to simply add the initialization circuit of the present invention, and there is an effect that the design can be changed very easily.

Further, the pulse generation circuit is configured so that the operation is stopped after the selection circuit cuts off the supply of the signal from the pulse generation circuit at the output of the counter circuit, so that the power consumption is increased. There is an effect that it can be prevented.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say. For example, each of the pulse generation circuit 12, the counter circuit 13, and the selection circuit 14 shown in FIGS. 3 to 7 is one embodiment, and any circuit form may be used as long as the circuit has the same function.

In the above description, the invention made mainly by the present inventor is referred to as DRA, which is a field of application in which the background was used.
Although M has been described as an example, the present invention is not limited to this, and can be used in general for a semiconductor integrated circuit equipped with a latch circuit and a flip-flop circuit.

[0036]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, initialization can be performed without inputting a clock from the outside, the potential of the floating node of the internal circuit at power-on can be determined and malfunction can be prevented, and the design burden on the user can be reduced. The cost of the system can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an initialization circuit according to the present invention.

FIG. 2 is a timing chart showing the operation timing of the initialization circuit of the embodiment.

FIG. 3 is a circuit configuration diagram showing a specific example of a pulse generation circuit.

FIG. 4 is a circuit configuration diagram showing a specific example of a delay circuit constituting a pulse generation circuit.

FIG. 5 is a circuit configuration diagram showing a specific example of a unit counter constituting the counter circuit.

FIG. 6 is a block diagram illustrating a configuration of a counter circuit.

FIG. 7 is a circuit configuration diagram showing a specific example of a selection circuit.

FIG. 8 is a circuit configuration diagram showing a schematic configuration of a power supply voltage level detection circuit.

FIG. 9 is a block diagram showing a schematic configuration of a DRAM as an example of a semiconductor integrated circuit suitable for applying the present invention.

FIG. 10 is a timing chart showing the timing of an initialization method in a conventional DRAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Initialization circuit 11 Power supply voltage level detection circuit 12 Pulse generation circuit 13 Counter circuit 14 Selection circuit 21 Power supply terminal 22 Memory array 23A, 23B Address input buffer circuit 24 Refresh counter 25 Row decoder 26 Column decoder 27 Sense amplifier and I / O bus 28 Data input / output buffer circuit 29 Timing control circuit

Claims (4)

[Claims] 1. A power supply voltage level detection circuit comprising: a power supply voltage level detection circuit for detecting a power supply voltage level; a pulse generation circuit; and a counter circuit for counting the number of pulses of a signal generated by the pulse generation circuit. After the circuit detects the rise of the power supply voltage, the signal generated by the pulse generation circuit is required for a predetermined number of pulses required for determining the potential of the portion where the potential is uncertain immediately after the power is turned on to the internal circuit. A semiconductor integrated circuit configured to be supplied to a circuit. And a selection circuit for selectively supplying either a predetermined input signal or a signal generated by the pulse generation circuit, wherein the selection circuit is controlled by an output of the counter circuit. After supplying a signal formed by the pulse generation circuit for a predetermined number of pulses to a required circuit when power is turned on, the predetermined input signal can be supplied to the required circuit. Item 2. The semiconductor integrated circuit according to item 1. 3. The pulse generation circuit is configured such that after the selection circuit switches from a signal output from the pulse generation circuit to the predetermined input signal, the operation thereof is stopped by an output of the counter circuit. 3. The semiconductor integrated circuit according to claim 2, wherein: 4. A power supply voltage level detection circuit for detecting a power supply voltage level, a pulse generation circuit, a counter circuit for counting the number of pulses of a signal formed by the pulse generation circuit, and a timing for taking in an address signal. A selection circuit for selectively supplying either an address strobe signal or a signal generated by the pulse generation circuit, wherein the selection circuit is controlled by an output of the counter circuit and has a predetermined function when power is turned on. A semiconductor memory device characterized in that a signal generated by the pulse generation circuit for a number of pulses is supplied to a required circuit, and then the address strobe signal can be supplied to an internal required circuit.