JP3096541B2 - Internal step-down circuit for semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an internal step-down circuit mounted on a semiconductor integrated circuit such as a dynamic random access memory (DRAM).

[0002]

2. Description of the Related Art In order to reduce the power consumption of a semiconductor integrated circuit and to ensure the reliability of its internal elements, the development of a semiconductor integrated circuit having an internal step-down circuit has been actively developed. The internal step-down circuit generates an internal step-down voltage based on the external power supply voltage VCC, and supplies the internal step-down voltage to the internal elements. For example, according to the circuit described in Japanese Patent Application Laid-Open No. 63-244217, an internal step-down voltage with little dependence on VCC can be obtained.

On the other hand, Japanese Patent Laying-Open No. 64-13292 discloses a DRAM having a self-refresh function at the time of battery backup requiring power saving operation. In this DRAM, the transition from the normal operation mode to the self-refresh mode is activated by special application timing of RAS (row address strobe) and CAS (column address strobe) from the outside. However, in the past, even during self-refresh requiring power saving operation, the internal elements were driven at the same voltage as during normal operation.

[0004] Now, Masashi Horiguchi et al., IEICE Technical Report ICD91-129 (1991, 25th edition).
Pp. 32) proposes a DRAM voltage limiter suitable for burn-in. According to this voltage limiter,
Normally, a stable internal step-down voltage is obtained, and a voltage for a burn-in acceleration test higher than the internal step-down voltage is automatically supplied to the internal elements simply by increasing VCC. For this purpose, the voltage limiter includes a first reference voltage generation circuit (VRN regulator) for generating an internal step-down voltage for normal operation and a first trimmer for adjusting the internal step-down voltage. In addition, a second reference voltage generating circuit (VRB regulator) for generating a high voltage for a burn-in acceleration test and a second trimmer for adjusting the high voltage are provided.

[0005]

SUMMARY OF THE INVENTION In a conventional DRAM,
As described above, even during self-refresh, the internal elements are operated at the same voltage as during normal operation, so that the power consumption of the DRAM during battery backup cannot be sufficiently reduced.

A DRA equipped with the above voltage limiter
Since M has two independent reference voltage generating circuits, the current consumption and the layout area are increased. In addition, the provision of the two trimmer parts has spurred an increase in current consumption and layout area.

An object of the present invention is to reduce current consumption and layout area of an internal voltage down converter suitable for burn-in for a semiconductor integrated circuit.

[0008]

In order to achieve the above object, the invention according to claims 1 to 6 is directed to a single reference voltage generating circuit having two constant voltage generating circuits whose outputs are fed back to each other. One internal step-down voltage is generated based on one output. Claims 7 to 10
According to the invention, two internal step-down voltages are output from a single internal step-down circuit.

[0009]

According to the present invention, the first reference voltage independent of the external power supply voltage output from the single reference voltage generation circuit is provided.
And a second reference voltage depending on the external power supply voltage, an internal step-down voltage for normal operation and a high voltage for burn-in acceleration test are obtained. In addition, since the two constant voltage generating circuits are fed back to each other so that the first and second reference voltages have a correlation with each other, the first and second reference voltages are simultaneously applied by a single trimmer. Can be corrected.

According to the present invention, two internal step-down voltages, each of which takes into account the burn-in acceleration test, can be used in a single semiconductor integrated circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an internal step-down circuit according to an embodiment of the present invention and a DRAM equipped with the internal step-down circuit will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a circuit diagram of an internal step-down circuit for a DRAM according to a first embodiment of the present invention. The internal step-down circuit 20 shown in FIG. 1 is a circuit for outputting an internal step-down voltage Vint as a supply voltage to the internal elements of the DRAM, and includes a reference voltage generating circuit 10, two differential amplifiers 11, 13, Two P-type MOS transistors Qp as output drivers
17, Qp19. The reference voltage generation circuit 10
A reference voltage (first reference voltage) Vref for normal operation;
Reference voltage (second reference voltage) V for burn-in acceleration test
and refbi. The first differential amplifier 11 has Vrefb
Let i be the first input and let Vint be the second input. Second
Differential amplifier 13 has Vref as a first input and Vint
Is the second input. The gate of Qp17 is controlled by the output of the first differential amplifier 11, and the gate of Qp19 is controlled by the output of the second differential amplifier 13. VCC is an external power supply voltage, and VSS is a ground power supply voltage.

The reference voltage generation circuit 10 is a CMOS-structured circuit for generating Vref having little dependency on Vcc and Vrefbi having dependency on Vcc. Specifically, two P-type MOS transistors Qp16, Qp are connected from VSS to VCC.
By forming a constant voltage source (MOS diode) with each of p14 and a constant current source with one P-type MOS transistor Qp13, the first voltage which does not depend on VCC but depends on VSS can be obtained.
To generate a reference voltage Vref of
Two P-type MOS transistors Qp10, Qp toward SS
11 constitutes a constant voltage source (MOS diode) and one N-type MOS transistor Qn10 constitutes a constant current source, thereby generating a second reference voltage Vrefbi which does not depend on VSS but depends on VCC. It is like that. Q
p10,11,14,16 all form a diode with the gate and drain short-circuited, and the gate of Qn10 and Q
The source of p14 is short-circuited, and the gate of Qp13 and the drain of Qp11 are short-circuited. Qp10,11,
13, 14, 16 and Qn10 are all operated in the saturation region. 10
3 is an output node for Vrefbi, and 104 is an output node for Vref. 102 is a connection node between Qp10 and Qp11, and 105 is a connection node between Qp14 and Qp16.

Here, the principle of operation of the reference voltage generating circuit 10 will be briefly described. Assuming that Vref is substantially constant, the gate potential of Qn10 operating in the saturation region has a constant value Vref, and its source potential is VSS. Therefore, Qn10
Is almost constant. As a result,
Qn10 operates as a constant current source, and the drain current Idn10 of Qn10 becomes substantially constant. Qp10, Qp11 and Qp
n10 and respective drain currents Idp10, Idp11, Id
The drain potential of Qp11 when n10 is equal (equal to its gate potential) is Vrefbi in a steady state. Therefore, Idp10 and Idp at steady state
11 is almost constant. On the other hand, each Q operates in the saturation region.
Since p10 and Qp11 are diodes each formed by a MOS transistor whose gate and drain are short-circuited, Idp10 and Idp11 are substantially determined by their respective gate-source voltages. Idp10 and Idp11
Are substantially constant as described above, Qp10 and Qp
The gate-source voltage of each of 11 is almost constant. From the above, the potential difference between Vrefbi and VCC (Qp10
Is equal to the potential difference between the source of Qp11 and the gate of Qp11. )
Is almost constant.

On the other hand, the gate-source voltage of Qp13 is V
Since the potential difference between refbi and VCC is substantially constant, Qp13 operating in the saturation region is a constant current source. That is, the drain current Idp13 of Qp13 is substantially constant even if VCC fluctuates. When the drain currents Idp13, Idp14, and Idp16 of Qp13, Qp14, and Qp16 are equal, the source potential of Qp14 is Vre in a steady state.
f. Therefore, Idp14 and Idp16 in the steady state are almost constant. On the other hand, Qp14 and Qp16, each operating in the saturation region, are diodes composed of MOS transistors with their gates and drains short-circuited, so that Idp14 and Idp16 are substantially determined by their respective gate-source voltages. Idp14 and I
When dp16 is substantially constant as described above, the gate-source voltage of each of Qp14 and Qp16 is substantially constant. From the above, the potential difference between Vref and VSS (Q
Equal to the potential difference between the source of p14 and the gate of Qp16. ) Is almost constant.

As described above, in the reference voltage generating circuit 10 adopting the feedback configuration as shown in FIG. 1, Vrefbi is lower than VCC by a predetermined potential, and becomes a constant reference voltage independent of VSS and dependent on VCC. . Also, Vre
f is higher than VSS by a predetermined potential, and becomes a constant reference voltage not depending on VCC but depending on VSS.

The six Ms constituting the reference voltage generating circuit 10
When all the OS transistors operate in the saturation region, Expression (1) holds.

Vref = − (2√βp1 * (√βp3 + √βp4) / (√ (βp1 * βp4) -4√ (βn0 + βp3))) Vtp− (4√ (βn0 * βp3) / (√ (βp1 * βp4) ) -4√ (βn0 + βp3)) Vtn + VSS (1) βp0, βp1, βp3, βp4, βp6, βn0: Qp10, 11, 13, 1
Vtp: threshold voltage of P-type MOS transistor Vtn: threshold voltage of N-type MOS transistor However, for simplicity, the threshold voltage of each P-type MOS transistor is assumed to be equal. did. Also, βp0
= Βp1 and βp4 = βp6, the equation (1) becomes βp0
And βp6 were not included. The expression of Vrefbi is omitted.

Next, the operation of the differential amplifiers 11 and 13 and the output drivers Qp17 and Qp19 in FIG. 1 will be described.
When Vint becomes lower than Vrefbi, Vin
The output voltage of the first differential amplifier 11 drops to increase t, turning on Qp17. And Vint is Vrefb
When it rises to i, the output voltage of the first differential amplifier 11 rises, turning off Qp17. Therefore, Vint is Vrefb
It rises to the same voltage as i. Similarly, the operation of the second differential amplifier 13 and Qp19 causes Vint to rise to the same voltage as Vref. That is, Vint is Vref and Vrefb
rise to the higher voltage with i.

FIG. 3 is a circuit diagram showing the V
FIG. 7 is a diagram illustrating the dependence of int on the external power supply voltage. Vref and V
The difference between SS and the difference between Vrefbi and VCC are set to desired values. In addition, when VCC is lower than 6 V (DRA
M includes the specified range of Vcc during normal operation of 4.5V to 5.5V. In (2), Vref is set higher than Vrefbi, so that Vint becomes equal to Vref independent of VCC.
On the other hand, in the range where VCC is 6 V or more (the range of VCC in the DRAM burn-in acceleration test), since Vrefbi is set higher than Vref, Vint becomes equal to Vrefbi depending on VCC. This Vint depending on Vcc allows DRA
The stress on the internal element of M can be increased.

As is apparent from the equation (1), variations in Vref and therefore in Vint occur due to manufacturing variations such as threshold voltage. FIG. 2 is a diagram showing a configuration example (fuse ROM unit) of a trimmer unit for adjusting Vint. According to FIG. 2, Qp16 in FIG. 1 is composed of six P-type MOS transistors Qp30 to Qp35 connected in series.
Qn10 is connected to six N-type MOs connected in series
Each is constituted by S transistors Qn30 to Qn. F0
F4 to F4 are fuses arranged between the source and drain of each of Qp31 to Q35, and F5 to F9 are fuses arranged between each source and drain of each of Qn31 to Q35. F0
When at least one of F4 is cut, the channel length of Qp16 is equivalently changed. Similarly, when at least one of F5 to F9 is cut, the channel length of Qn10 is equivalently changed. 301 to 310 are connection nodes between the transistors.

Vref depends on the gain coefficient β of each MOS transistor constituting the reference voltage generating circuit 10 as shown in equation (1), and the gain coefficient β is expressed by equation (2). You.

Β = μ * Cox * W / 2 * L (2) where μ is the carrier mobility, Cox is the gate oxide film capacitance, W is the channel width, and L is the channel length. Equation (1)
According to (2), it is understood that by changing the channel length L of the MOS transistor, the gain coefficient β can be changed, Vref can be changed, and Vint can be adjusted.

Next, Vref and Vrefb are cut by fuse cutting.
The fact that i can be corrected simultaneously will be described with reference to FIG. FIG. 4 is a diagram showing the dependency of Vint on the external power supply voltage, which is drawn for explaining the process of adjusting Vint. FIG. 4 shows a case where Vtp (the threshold voltage of the P-type MOS transistor) is a set value, and a case where Vtp is -0.0 from the set value.
Vref and Vrefb by 5V off and fuse cut
The dependence of Vint on VCC in the three cases, that is, when Vint is adjusted by simultaneously correcting i and Vint, is shown by a solid line,
This is indicated by a broken line and a dashed line.

When Vtp is lower than the set value by 0.05 V, Vint becomes higher than the set value when VCC is lower than 6 V, and Vint becomes lower than the set value when VCC is higher than 6 V. . In this case, of the five fuses F5 to F9 for Qn10 in FIG. 2, the number of fuses corresponding to the required correction amount are cut. Then, the gate length of Qn10 becomes equivalently longer than before the fuse is cut, and the drain current Idn10 decreases. As a result, Vrefbi increases. And at the same time, Vrefbi
, The drain current Idp13 of Qp13 decreases, and Vref decreases. That is, the characteristic of the broken line in FIG. 4 is corrected to the characteristic of the dashed line close to the characteristic of the solid line.

Conversely, if Vtp is higher than the set value, it is not shown, but if VCC is lower than 6 V, Vin
t becomes lower than the set value, and Vint becomes higher than the set value when VCC is 6 V or more. In this case, five fuses F0-F for Qp16 in FIG.
The fuses of the number corresponding to the required correction amount out of four are blown. Then, the gate length of Qp16 becomes equivalently longer than before the fuse is cut, and the drain current Idp16 decreases. As a result, Vref increases. At the same time, the drain current I of Qn10 with Vref as the gate input
dn10 decreases and Vrefbi decreases. That is, also in this case, Vref and Vrefbi can be simultaneously corrected by cutting the fuse, and desired characteristics close to the characteristics indicated by the solid line in FIG. 4 can be realized.

As described above, according to the present embodiment, a single reference voltage generating circuit 10 generates Vref and Vrefbi, which are fed back to each other, and generates an internal step-down circuit which generates Vint based on the higher of the two. Since the configuration of FIG. 20 is adopted, the current consumption and the layout area of the internal step-down circuit are different from the conventional case where the reference voltage generating circuit for the normal operation and the reference voltage generating circuit for the burn-in acceleration test are separately provided. Reduced. In addition, since the reference voltage generating circuit 10 employs a configuration of a trimmer unit that can simultaneously adjust Vref and Vrefbi, a trimmer unit for a normal operation and a trimmer unit for a burn-in acceleration test are separately provided. In contrast, the layout area of the trimmer portion is reduced. Also,
In the trimmer section of this embodiment, there is no through-current path through which a steady current flows between the external power supply and the ground power supply, so that the current consumption of the internal step-down circuit is further reduced.

Note that, instead of the above-described channel length adjustment method,
A method of adjusting the channel width W may be adopted. Specifically, the number of MOS transistors in parallel is changed. Instead of the fuse cutting method, a method of changing the serial number or the parallel number of MOS transistors based on a decode signal can be adopted.

In a DRAM, electric charges are stored in a capacitance (capacitor) of a memory cell, and information is stored according to the presence or absence of the electric charge. During a normal operation of the DRAM, a write voltage to this memory cell is supplied by a sense amplifier. In addition, peripheral circuits for writing and reading information and satisfying other functions are incorporated in the DRAM. According to this embodiment, DRA
The same Vint is supplied from the internal step-down circuit 20 of FIG. 1 to the sense amplifier and peripheral circuits in M. V which stepped down VCC
The reason why int is supplied to the sense amplifier is to ensure the reliability of the capacitance oxide film of the memory cell. The reason why Vint, which is obtained by stepping down VCC, is supplied to peripheral circuits is to secure reliability and reduce power consumption due to miniaturization of internal elements.

In order to increase the operating speed of peripheral circuits and ensure the reliability of memory cells during normal operation of the DRAM, it is necessary to lower the supply voltage to the sense amplifier compared to the supply voltage to the peripheral circuits. Becomes For example, VCC is 5
In the case of V, 4V is supplied to the peripheral circuit as the first internal step-down voltage Vint1 and 3.3V as the second internal step-down voltage Vint2 to the sense amplifier. According to the present embodiment, two internal step-down circuits each having the configuration of FIG. 1 are mounted in a DRAM, and one internal step-down circuit outputs Vint1 and the other internal step-down circuit outputs Vint2.

(Embodiment 2) In the second embodiment, a single internal step-down circuit can output two different internal step-down voltages Vint1 and Vint2.

FIG. 5 is a diagram showing a DR according to a second embodiment of the present invention.
FIG. 3 is a circuit diagram of an internal step-down circuit for AM. 5 includes two internal step-down voltages Vint1 and Vin.
a circuit for outputting t2, comprising a reference voltage generating circuit 6
0, four differential amplifiers 61 to 64, and four P-type MOS transistors Qp67 and Qp6 as output drivers.
8, Qp69 and Qp6a. The reference voltage generation circuit 60 includes a reference voltage (first reference voltage) Vref1 for normal operation and a reference voltage (second reference voltage) Vrefbi1 for a burn-in acceleration test for the first internal step-down voltage Vint1. And generate. In addition, the reference voltage generation circuit 60 includes a reference voltage (third reference voltage) Vref2 for normal operation and a reference voltage (fourth reference voltage) for a burn-in acceleration test for the second internal step-down voltage Vint2. Voltage) Vrefbi2. The first differential amplifier 61 has Vrefbi1 as a first input,
Let int1 be the second input. The second differential amplifier 62 is
Let refbi2 be the first input and Vint2 be the second input.
The third differential amplifier 63 has Vref1 as a first input,
Let int1 be the second input. The fourth differential amplifier 64 has V
Let ref2 be the first input and Vint2 be the second input. Q
The gate of p67 is connected to the output of the first differential amplifier 61 by Q
The gate of p68 is connected to the output of the second differential amplifier 62 by Q
The gate of p69 is connected to the output of the third differential amplifier 63 by Q
The gates of p6a are each controlled by the output of the fourth differential amplifier 64.

The reference voltage generating circuit 60 includes Vref1 and Vref2 having little dependence on VCC and Vrefbi1 and Vref having dependence on VCC.
This is a circuit having a CMOS configuration for generating refbi2.
Specifically, by arranging four P-type MOS transistors Qp66, Qp65, Qp64, and Qp63 in series from VSS to VCC, Vref independent of VCC and dependent on VSS is provided.
1, Vref2, and three P-type MOS transistors Qp60, Qp61, Qp from VCC to VSS.
By arranging p62 and one N-type MOS transistor Qn60 in series, V independent of VCC and independent of VSS.
refbi1 and Vrefbi2 are generated. Q
p60, 62, 65, and 66 all form a diode in which the gate and drain are short-circuited, and the gate of Qn60 and Q
The source of p64 is short-circuited, and the gate of Qp63, the gate of Qp61 and the drain of Qp62 are short-circuited. The gate of Qp64 is short-circuited to the drain of Qp65. That is, the reference voltage generation circuit 60 in FIG. 5 replaces Qp11 in the reference voltage generation circuit 10 in FIG.
In addition, the configuration is such that Qp14 is replaced by Qp64 and Qp65, respectively. Qp60, 61, 62, 63, 64, 65, 66 and Qn60 all operate in the saturation region. 610 is an output node for Vrefbi1, 603 is an output node for Vrefbi2, 604 is an output node for Vref1, and 611 is an output node for Vref2. 602 is a connection node between Qp60 and Qp61, and 605 is a connection node between Qp65 and Qp66.

Here, the operation principle of the reference voltage generating circuit 60 will be briefly described. Assuming that Vref1 is substantially constant, the gate potential of Qn60 operating in the saturation region is a constant value Vref1, and its source potential is VSS. Therefore, Qn60
Is almost constant. As a result,
Qn60 operates as a constant current source, and the drain current Idn60 of Qn60 becomes substantially constant. Qp60, Qp61 and Qp
The drain currents Idp60, Idp of p62 and Qn60, respectively.
The drain potential (equal to the gate potential) of Qp62 when 61, Idp62, and Idn60 are equal is Vrefbi2 in the steady state. Therefore, I in the steady state
dp60, Idp61, Idp62 are almost constant. on the other hand,
Since Qp60, Qp61 and Qp62 each operate in the saturation region, Idp60, Idp61 and Idp62 are substantially determined by their respective gate-source voltages. Idp60 and Id
When p61 and Idp62 are substantially constant as described above,
The gate-source voltages of Qp60, Qp61 and Qp62 are almost constant. From the above, the potential difference between Vrefbi2 and VCC (equal to the potential difference between the source of Qp60 and the gate of Qp61) is almost constant. Also, since Idp61 is constant regardless of VCC, the potential difference between Vrefbi1 and VCC is also substantially constant.

On the other hand, the gate-source voltage of Qp63 is V
Since the potential difference between refbi2 and VCC is substantially constant, Qp63 operating in the saturation region becomes a constant current source. That is, the drain current Idp63 of Qp63 is substantially constant even if VCC fluctuates. Qp63, Qp64, Qp65 and Qp
66 and the respective drain currents Idp63, Idp64, Idp
The source potential of Qp64 when 65 and Idp66 are equal is Vref1 in the steady state. Therefore, Idp64, Idp65 and Idp66 in the steady state are almost constant. On the other hand, since Qp64, Qp65 and Qp66 each operate in the saturation region, Idp64, Idp65 and Idp66 are substantially determined by their respective gate-source voltages. Id
When p64, Idp65 and Idp66 are almost constant as described above, the gate-source voltages of Qp64, Qp65 and Qp66 are almost constant. From the above, Vref1 and Vref1
The potential difference between SS (equal to the potential difference between the source of Qp64 and the gate of Qp66) is substantially constant, and the potential difference between Vref2 and VSS (the potential difference between the source of Qp65 and the gate of Qp66). Is almost constant.

As described above, in the reference voltage generating circuit 60 adopting the feedback configuration as shown in FIG. 5, Vrefbi1 and Vrefbi2 are each lower than VCC by a predetermined potential, and are not dependent on VSS but on a constant basis which depends on VCC. Voltage. Further, Vref1 and Vref2 are each higher than VSS by a predetermined potential, and become constant reference voltages not depending on VCC but depending on VSS. However, Vrefbi1> Vrefbi2 and Vref1> V
ref2.

Further, according to the configuration of the internal step-down circuit 30 of FIG. 5, Vint1 becomes Vref1 and Vrefbi1 due to the operation of the first and third differential amplifiers 61 and 63, Qp67 and Qp69.
And rise to the higher voltage. Similarly, the second and fourth
Vint2 rises to the higher voltage of Vref2 and Vrefbi2 due to the operation of the differential amplifiers 62 and 64, Qp68 and Qp6a.

FIG. 6 shows V in the internal voltage down converter 30.
FIG. 9 is a diagram illustrating the external power supply voltage dependence of int1 and Vint2.
As in the case of FIG. 3, Vin is in the range where VCC is lower than 6V.
Both t1 and Vint2 do not depend on VCC, and when VCC is in the range of 6 V or more, both Vint1 and Vint2 become high voltages that can apply stress to the internal elements that depend on VCC. However,
Vint1> Vint2. Adjustment of Vint1 and Vint2 can be achieved by the same operation of the fuse ROM section as in FIG.

FIG. 7 is a block diagram of a DRAM on which the internal voltage down converter 30 having the configuration of FIG. 5 is mounted. 7, 21 is a memory cell, 22 is a word line, 23 is a bit line, 24 is a sense amplifier for supplying a write voltage to the memory cell 21, and 25 is other peripheral circuits. The internal step-down circuit 30 supplies Vint1 to the peripheral circuit 25 and supplies Vint2 lower than Vint1 to the sense amplifier 24. Thereby, during the normal operation of the DRAM, the operation speed of the peripheral circuit 25 is increased, and the reliability of the capacitance oxide film of the memory cell 21 is ensured.

As described above, according to the present embodiment, two different internal step-down voltages V
int1 and Vint2 can be output. Therefore, two internal step-down circuits each having the configuration shown in FIG. 1 are mounted in the DRAM, and Vint1 is output from one internal step-down circuit and Vint2 is output from the other internal step-down circuit. Current consumption and layout area are reduced.

It should be noted that development from the configuration of FIG. 5 to a configuration for generating three or more internal step-down voltages will be easy for those skilled in the art.

Embodiment 3 In the third embodiment, two different internal step-down voltages Vint1, Vint2 (Vint1> Vint2) are obtained from a single internal step-down circuit.
One of which can be selectively output.

FIG. 8 shows a DR according to the third embodiment of the present invention.
FIG. 3 is a circuit diagram of an internal step-down circuit for AM. The internal step-down circuit 40 shown in FIG. 8 is a circuit for outputting one of Vint1 and Vint2 as one internal step-down voltage Vint. The internal step-down circuit 40 shown in FIG.
This is obtained by adding p6b and Qp6c. Qp6b and Q
p6c is arranged in series from Vint1 to Vint2. The gate of Qp6b is connected to Qp6c by the first control signal A.
Are respectively controlled by a second control signal B. 6
Reference numeral 12 denotes a connection node between Qp6b and Qp6c, and Vin
Output node for t.

In the internal step-down circuit 40 shown in FIG. 8, when the first control signal A is at a low level and the second control signal B is at a high level, Qp6b is turned on and Qp6c is turned off.
At this time, Vint output from internal step-down circuit 40 is Vint
It is equal to int1. Conversely, if the first control signal A is at a high level and the second control signal B is at a low level, Qp6b
Is in the off state and Qp6c is in the on state.
It is equal to int2. That is, according to the present embodiment, Vint1 and Vint2 each having the external power supply voltage dependency shown in FIG.
Can be arbitrarily switched as to which one is output as Vint.

FIG. 9 is a block diagram of a DRAM on which the internal voltage down converter 40 having the configuration of FIG. 8 is mounted. The internal step-down circuit 40 supplies a common Vint to the sense amplifier 24 and the peripheral circuit 25. In addition, Vint1 is used in the normal operation mode of the DRAM, and Vint1 is used in the self-refresh mode.
The lower Vint2 is each selected as Vint.

At the time of normal operation, the internal step-down circuit 40 supplies the sense amplifier 24 and the peripheral circuit 25 with V higher than Vint2.
int1 is supplied. Thereby, writing / writing of stored information
A high operation speed of the DRAM internal circuit for reading is guaranteed. If VCC is raised to 6V or more, D
It is also possible to execute a RAM burn-in acceleration test.

At the time of battery backup which does not require a high operation speed of the internal circuit, especially in the self-refresh mode, Vint2 lower than Vint1 is supplied from the internal step-down circuit 40 to the sense amplifier 24 and the peripheral circuit 25. Thus, power consumption of the DRAM can be reduced while retaining stored information. Specifically, not only the power consumption for the refresh operation but also the power consumption in the standby state where the refresh operation is not performed is reduced.

In FIG. 9, the supply voltage Vint to the sense amplifier 24 is the write voltage to the memory cell 21 as described above. The amount of charge stored as storage information in the capacitor of the memory cell 21 depends on the magnitude of Vint. When the amount of charge stored in the capacitor of the memory cell 21 changes, the retention time of the stored information changes, so that the time interval (refresh overhead time) at which the refresh operation must be performed changes. A fourth embodiment described below solves this problem.

(Embodiment 4) In the fourth embodiment, the fluctuation of the supply voltage to the sense amplifier in the DRAM is suppressed.

FIG. 10 is a block diagram of a DRAM having an internal voltage down converter according to a fourth embodiment of the present invention. The internal configuration of the internal step-down circuit 40 in FIG. 10 is as shown in FIG. The internal step-down circuit 40 supplies Vin to the peripheral circuit 25.
While supplying t, Vint2 is supplied to the sense amplifier 24.

Vint supplied from the internal step-down circuit 40 to the peripheral circuit 25 is DRA, as in the third embodiment.
M is Vint1 in the normal operation mode, and Vint2 is lower than Vint1 in the self-refresh mode. However, unlike the third embodiment, the sense amplifier 24
Is supplied in both the normal operation mode and the self-refresh mode.

According to this embodiment, the power consumption of the DRAM can be reduced by lowering the supply voltage Vint to the peripheral circuit 25 during the self-refresh operation without deteriorating the data holding characteristics of the memory cell 21. Specifically, according to the fourth embodiment, the current consumption at the time of battery backup of the DRAM (a value obtained by averaging the current consumption at the time of refreshing and the current consumption at the time of standby) is reduced according to the second embodiment (FIG. About 22% from 101 μA in case 7) to 79 μA
Reduced.

The internal step-down circuit 40 of FIG. 8 may be used for peripheral circuits, and a separate internal step-down circuit for a sense amplifier may be provided in the DRAM. In this case, the lower output voltage Vint2 of the internal step-down circuit 40 for the peripheral circuit,
The output voltage of the internal voltage down converter dedicated to the sense amplifier may be different from each other.

The supply voltage to internal elements (particularly, constituent elements of peripheral circuits) in the DRAM can be switched by the method shown in FIG. According to FIG.
In step 81, it is determined whether the mode is the normal operation mode or the self-refresh mode. If CAS (column address strobe) falls after RAS (row address strobe) falls, it is determined that the normal operation mode is set. Conversely, after the fall of CAS, RA
If S has fallen and a certain time has elapsed after the fall of RAS, it is determined that the mode is the self-refresh mode. In the case of the normal operation mode, in step 82, the external power supply voltage VCC is supplied to the DRAM internal elements without being reduced. In the case of the self-refresh mode, in step 83, the external power supply voltage VCC itself, which is the supply voltage to the internal elements during normal operation, is reduced. Instead of reducing VCC itself, the supply voltage to the internal elements is changed from VCC to an internal step-down circuit (for example, FIG. 1).
) May be switched to the output Vint.

In each of the above embodiments, the internal step-down circuit mounted on the DRAM has been described. However, the internal step-down circuit according to the present invention can be used in other types of semiconductor integrated circuits. For example, the internal step-down circuit of the present invention can be applied to a read power supply of an EEPROM.

[0056]

As described above, claims 1 to 6 are described.
According to the invention of 2), the outputs are fed back to each other.
Since one internal step-down voltage is generated based on two outputs of a single reference voltage generating circuit having two constant voltage generating circuits, consumption of the internal step-down circuit suitable for burn-in for a semiconductor integrated circuit is consumed. The current and the layout area can be reduced.

According to the invention of claims 7 to 10, since two internal step-down voltages are output from a single internal step-down circuit, the two internal step-down voltages taking into account the burn-in acceleration test are each single. It can be used in one semiconductor integrated circuit.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an internal step-down circuit for a DRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a trimmer unit for the internal step-down circuit of FIG. 1;

FIG. 3 is a characteristic diagram showing the dependence of an internal step-down voltage output from the circuit of FIG. 1 on an external power supply voltage.

FIG. 4 is a characteristic diagram for explaining a process of adjusting an internal step-down voltage output from the circuit of FIG. 1;

FIG. 5 is a circuit diagram of an internal step-down circuit according to a second example of the present invention.

FIG. 6 is a characteristic diagram showing external power supply voltage dependence of two internal step-down voltages output from the circuit of FIG. 5;

FIG. 7 is a block diagram of a DRAM equipped with the internal step-down circuit of FIG. 5;

FIG. 8 is a circuit diagram of an internal voltage down converter according to a third embodiment of the present invention.

FIG. 9 is a block diagram of a DRAM equipped with the internal step-down circuit of FIG. 8;

FIG. 10 is a block diagram of a DRAM equipped with an internal step-down circuit according to a fourth embodiment of the present invention.

FIG. 11 is a flowchart illustrating an example of a method of switching a supply voltage to an internal element in a DRAM according to the present invention.

[Explanation of symbols]

10, 60 Reference voltage generation circuit 11, 13, 61 to 64 Differential amplifier 20, 30, 40 Internal step-down circuit 24 Sense amplifier 25 Peripheral circuit F Fuse Qp P-type MOS transistor Qn N-type MOS transistor Vint Internal step-down voltage Vref Normal operation Reference voltage for time (first reference voltage) Vrefbi Reference voltage for burn-in acceleration test (second reference voltage) VCC External power supply voltage VSS Ground power supply voltage

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H01L 27/04 H01L 27/04 B 27/10 481 (56) References JP-A-60-45997 (JP, A) 1-185461 (JP, A) JP-A-4-145509 (JP, A) JP-A-4-212786 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/4074

Claims (10)

(57) [Claims] 1. An internal step-down circuit mounted on a semiconductor integrated circuit so as to generate an internal step-down voltage in the semiconductor integrated circuit, wherein a reference voltage generator for generating first and second reference voltages is provided. And an output circuit for outputting the internal step-down voltage based on the first and second reference voltages generated by the reference voltage generation circuit, wherein the reference voltage generation circuit is based on a ground power supply voltage. A first constant voltage generation circuit for generating the first reference voltage, and a second constant voltage generation circuit for generating the second reference voltage based on an external power supply voltage. The first and second constant voltage generating circuits each include a constant current source and a constant voltage source, and each other constant voltage generating circuit so that the first and second reference voltages have a correlation with each other. It is controlled by the output of Internal buck circuit. 2. The internal step-down circuit according to claim 1, wherein said reference voltage generating circuit further comprises a trimmer means for simultaneously correcting said first and second reference voltages so as to adjust said internal step-down voltage. An internal step-down circuit comprising: 3. The internal step-down circuit according to claim 1, wherein said reference voltage generating circuit is constituted by a combination of CMOS transistors. 4. The internal step-down circuit according to claim 3, wherein said reference voltage generating circuit includes a fuse ROM for changing characteristics of said CMOS transistor so as to simultaneously correct said first and second reference voltages. An internal step-down circuit further provided. 5. The internal step-down circuit according to claim 1, wherein said first constant voltage generating circuit is arranged on an external power supply side so as to function as a constant current source.
An OS transistor, and at least one MOS on the ground power supply side, the gate and the drain of which are short-circuited and each of which is connected in series to the MOS transistor on the external power supply side so as to function as a constant voltage source.
And a second constant voltage generating circuit, wherein the second constant voltage generating circuit is arranged on a ground power supply side so as to function as a constant current source.
An OS transistor, and at least one MOS on the external power supply side which is short-circuited between the gate and the drain and connected in series to the MOS transistor on the ground power supply side so as to function as a constant voltage source.
A gate potential of a MOS transistor functioning as a constant current source in the first constant voltage generation circuit, and a gate potential of one of the MOS transistors functioning as a constant voltage source in the second constant voltage generation circuit. The gate potential of the MOS transistor supplied from one of the MOS transistors and functioning as a constant current source in the second constant voltage generation circuit is the MOS transistor among the MOS transistors functioning as the constant voltage source in the first constant voltage generation circuit. An internal step-down circuit supplied from one. 6. The internal step-down circuit according to claim 1, wherein the output circuit operates based on each of the first and second reference voltages generated by the reference voltage generating circuit and the internal step-down voltage. First and second differential amplifiers, the first and second differential amplifiers outputting the internal step-down voltage based on the higher voltage of the first and second reference voltages. An internal step-down circuit comprising: first and second output drivers controlled by respective outputs. 7. A semiconductor integrated circuit comprising:
An internal step-down circuit mounted on the semiconductor integrated circuit so as to generate a second internal step-down voltage, wherein a reference voltage generating circuit for generating first to fourth reference voltages; A first output circuit for outputting the first internal step-down voltage based on the first and second reference voltages generated by the circuit; and a third and a fourth output circuit generated by the reference voltage generation circuit. A second output circuit for outputting the second internal step-down voltage based on a reference voltage, wherein the reference voltage generation circuit generates the first and third reference voltages based on a ground power supply voltage A first constant voltage generating circuit for generating the second and fourth reference voltages based on an external power supply voltage; and a first constant voltage generating circuit for generating the second and fourth reference voltages based on an external power supply voltage. The constant voltage generation circuit consists of a constant current source and a constant voltage source, respectively. And the first and second reference voltages are correlated with each other, and the third and fourth reference voltages are correlated with each other by the output of another constant voltage generating circuit. An internal step-down circuit characterized by being controlled. 8. The internal step-down circuit according to claim 7, wherein a supply voltage to an internal element of said semiconductor integrated circuit is changed to said first voltage.
And a switching means for arbitrarily selecting from the second internal step-down voltage. 9. The internal step-down circuit according to claim 7, wherein at least one of said first and second internal step-down voltages is output as a write voltage to a memory cell of a DRAM. circuit. 10. The internal step-down circuit according to claim 7, wherein at least one of said first and second internal step-down voltages is output as a read power supply of an EEPROM.