JPS59180253U - Control signal recording circuit - Google Patents
Control signal recording circuitInfo
- Publication number
- JPS59180253U JPS59180253U JP7394483U JP7394483U JPS59180253U JP S59180253 U JPS59180253 U JP S59180253U JP 7394483 U JP7394483 U JP 7394483U JP 7394483 U JP7394483 U JP 7394483U JP S59180253 U JPS59180253 U JP S59180253U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- recording circuit
- signal recording
- vertical synchronization
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図、第２図は共に従来例を示すブロック図、第３図
は本考案−実施例のブロック図、第４図は第３図の要部
波形図である。
主な図番の説明、１３・・・リトリガブルモノマルチ。1 and 2 are block diagrams showing a conventional example, FIG. 3 is a block diagram of an embodiment of the present invention, and FIG. 4 is a waveform diagram of the main part of FIG. 3. Explanation of main figure numbers, 13... Retriggerable mono multi.
Claims (1)
の抜けを補償するコントロール信号記録回路において、
前記垂直同期信号を入力するリトリガブルモノマルチを
備え、該モノマルチ出力によりコントロール信号の記録
を禁止することを特徴とするコントロール信号記録回路
。In a control signal recording circuit that has a signal source synchronized with a vertical synchronization signal and compensates for omission of the vertical synchronization signal,
A control signal recording circuit comprising a retriggerable monomulti to which the vertical synchronization signal is input, and inhibits recording of the control signal by outputting the monomulti.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7394483U JPS59180253U (en) | 1983-05-17 | 1983-05-17 | Control signal recording circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7394483U JPS59180253U (en) | 1983-05-17 | 1983-05-17 | Control signal recording circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59180253U true JPS59180253U (en) | 1984-12-01 |
Family
ID=30204054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7394483U Pending JPS59180253U (en) | 1983-05-17 | 1983-05-17 | Control signal recording circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59180253U (en) |
-
1983
- 1983-05-17 JP JP7394483U patent/JPS59180253U/en active Pending
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