JPS5995409U - Double deck simultaneous recording circuit - Google Patents

Double deck simultaneous recording circuit

Info

Publication number
JPS5995409U
JPS5995409U JP18998182U JP18998182U JPS5995409U JP S5995409 U JPS5995409 U JP S5995409U JP 18998182 U JP18998182 U JP 18998182U JP 18998182 U JP18998182 U JP 18998182U JP S5995409 U JPS5995409 U JP S5995409U
Authority
JP
Japan
Prior art keywords
double deck
recording circuit
simultaneous recording
deck simultaneous
recording
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18998182U
Other languages
Japanese (ja)
Inventor
今西　良孝
岩崎　安倫
Original Assignee
日本コロムビア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本コロムビア株式会社 filed Critical 日本コロムビア株式会社
Priority to JP18998182U priority Critical patent/JPS5995409U/en
Publication of JPS5995409U publication Critical patent/JPS5995409U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示すブロック図である。 １はプログラムソース、２はファンクションスイッチ、
３は増幅回路、５はＡデツキ、６はＢデツキ、７は同時
録音スイッチである。FIG. 1 is a block diagram showing one embodiment of the present invention. 1 is the program source, 2 is the function switch,
3 is an amplifier circuit, 5 is an A deck, 6 is a B deck, and 7 is a simultaneous recording switch.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ダブルデツキに複数のプログラムソースを入力し、録音
再生する装置において、複数のプログラムソースを切換
えるファンクションスイッチの前段よりそれぞれの録音
入力をスイッチを通１て供給することを特徴とするダブ
ルデツキの同時録音回路。A simultaneous recording circuit for a double deck, in which a plurality of program sources are input to the double deck for recording and playback, and the double deck simultaneous recording circuit is characterized in that each recording input is supplied through a switch from a stage preceding a function switch for switching between the plurality of program sources.
JP18998182U 1982-12-17 1982-12-17 Double deck simultaneous recording circuit Pending JPS5995409U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18998182U JPS5995409U (en) 1982-12-17 1982-12-17 Double deck simultaneous recording circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18998182U JPS5995409U (en) 1982-12-17 1982-12-17 Double deck simultaneous recording circuit

Publications (1)

Publication Number Publication Date
JPS5995409U true JPS5995409U (en) 1984-06-28

Family

ID=30409462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18998182U Pending JPS5995409U (en) 1982-12-17 1982-12-17 Double deck simultaneous recording circuit

Country Status (1)

Country Link
JP (1) JPS5995409U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6280254U (en) * 1985-11-11 1987-05-22

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5237912B2 (en) * 1972-08-25 1977-09-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5237912B2 (en) * 1972-08-25 1977-09-26

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6280254U (en) * 1985-11-11 1987-05-22

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