JPS59178766A - Read only memory - Google Patents

Abstract

PURPOSE:To improve the memory density of a memory by a method wherein a region of the other conductivity type is diffusion-formed in the surface layer of a semiconductor substrate of one conductivity type, and a metal is mounted on the diffused region through a connecting hole provided in an insulation layer adhered on the substrate surface, thus being made as a Schottky diode, which is arranged at the position of matrix intersection of the read only memory. CONSTITUTION:An N type region 2 and an N<+> type region 3 abutting against each other are diffusion-formed in the surface layer part of the P type Si substrate 1, the entire surface is covered with an SiO2 insulation film 9, and connecting holes 8 and 7 are bored by making them correspond to the regions 2 and 3, respectively. Next, a Schottky electrode of PtSi, etc. is mounted on the region 2 exposed in the connecting hole 8, and an Al ohmic electrode 4 is provided on the region 3 exposed in the hole 7, resulting in the formation of the Schottky diode. Thereafter, said diodes are respectively arranged at each intersection of many word lines A1-An led out of a word line decoder/drive circuit 1 with many data lines Ba-Bm led out of a data line decoder 2.

Description

[Detailed description of the invention] Technical field The present invention relates to read-only memories.

Prior Art Figure 1 shows the conventional readout method. FIG. 3 is a diagram illustrating a circuit related to a mesememory. In this dedicated memory, one metal oxide film semiconductor (abbreviated as MO) is used for each bit.
5)) The transistors are allocated. (A word line decoder/drive circuit 1 and a data line decoder 2 are connected to the yellow word lines A1 to An and the vertical data lines B l to B m, respectively. To set data to the transistors, It depends on the gate film thickness of the transistor, the presence or absence of l'L/n:17 contact, the level of threshold space pressure vth, etc. Among these, the most commonly used data setting structure is This configuration depends on the presence or absence of a drain contact.In such a configuration,
One MOS transistor is required for each bit of data, and a space for installing a drain contact is always required regardless of the presence or absence of data. Therefore, it is difficult to improve the level of consciousness.

OBJECTIVES It is an object of the present invention to provide a read-only memory with improved storage density.

Embodiment FIG. 2 is a diagram showing the configuration of a read-only memory and circuits related to the read-only memory according to an embodiment of the present invention.

A Schottky diode D is selectively arranged at the intersection point V of the matrix formed by the horizontal word lines A1 to An and the vertical data lines Bl to Bm. If the word green decoder/driver ω1 circuit l is one of the words MAL to An, for example, the word line Al is set to fl-1li, the data line B] Electric current is generated. When another word line A2 becomes high potential, that word line A2
No Schottky diode is placed at the intersection point 11 between the data line B1 and the data line I31.
No current flows through. In this way, the contents of the memory are read out.

The connected polarity of Schottky diode D is
The direction shown in FIG. 2 may be reversed, and the polarities applied to the word lines A1 to An are reversed in polarity. In addition, 4tl Schottky diodes 1 having mutually opposite polarities are placed at the intersections of the word lines A1 to An and the data lines B1 to Bm.
2 (for example, Schottky diodes in FIG. 2) may be used to detect the connected and unconnected states of the word lines A1 to An and the data lines B1 to Bm. A diode having a polarity opposite to that of the Schottky diode D may be placed at the intersection where D is not placed.

Figure 3 is a cross-section [lI] diagram showing the specific configuration of Schottky diode D, and Figure 4 is its equivalent circuit 1%1
There is f. Silicon base of P type which is one conductivity type] On the surface of anti-1, there is a diffusion head of N type impurity which is conductivity type 2,
3 is formed. In this embodiment, the N-type impurity concentration in the diffusion region 3 may be higher than the impurity concentration in the other diffusion region 2 in order to make good contact with the electrode 4. Insulating material 9 such as S i02 having connection holes 7 and 8 is
Formed on the surfaces of the substrate 1 and the diffusion head 2. Connection holes 7, 8
An electrode 4 made of metal such as aluminum and making ohmic contact is connected to the electrode 4. Electrode 4,
It can be not only aluminum but also the metal of the pond,
Furthermore, polycrystalline silicon may be used.

The electrode 5 is a metal for forming a Schottky diode, and may be made of multiple layers of metal. This electrode 5 is
For example, it may have a multilayer structure of platinum silicide (PtSi)-titanium tungsten (TiW)-aluminum (A1).

FIG. 5 is a sectional view of another embodiment of the present invention, the equivalent circuit of which is shown in FIG. This embodiment is similar to the previous embodiment and corresponding parts are provided with the same reference numerals. A Schottky diode DI- is connected to the electrode 4 with a common connection F.

FIG. 7 is a cross-sectional view of yet another embodiment of the "Finished"
FIG. 8 is an equivalent circuit diagram thereof. Electrodes 50 to 5f are connected to word lines A1 to AnlC, and electrodes 4r and data line B1 are connected to each other.
~ Connected to Bm.

In the above-mentioned example, in order to lower the sheet resistance of the N-pear single-sheet head regions 2 and 3, the carbon content of impurities other than near the surface may be increased.

FIG. 9 shows another embodiment of the invention. In this example,
Schottky diode F D's cap F to data line B1
~Bm in common, and Ame-F is connected to the word line Al~An
It is connected to the.

As an embodiment of the pond of the present invention, Schottky diode-El
) is connected to the word line AINAnK, and
may be connected to the data line B l = B m, in which case the flow direction of the 1l-fl flow is reversed.

Data at the intersections of the matrix made up of word lines A1 to An and data lines B1 to Bm are stored in Schottky diodes! to word lines A1 to An, or data line B
This may be done by selectively connecting the Schottky diodes 1 to Bm, or the cutout Schottky diodes themselves may be selectively connected.

When a read-only memory having such a structure +i is realized by an integrated circuit, K is -word' line Al~A, n
Data lines Bl-Bm and all 2) metal wiring may be used, or - 10,000 lines may be made of metal, and the power lines may be made of polycrystalline silicon or silicide (a combination of polycrystalline silicon and metal). It is also possible to use a common diffusion region 2 as shown in FIG. 7 by omitting the parallel lines.

Figure 10 shows the signals from data lines B1 to B'm.
FIG. 2 is a diagram showing a specific configuration of a circuit for accommodating the patient. The famous data Kasuri Bl~Bm in Fig. 2 are the resistances R1~
Grounded via Rm. The signal-8 from the data lines B1 to Bm is a detection circuit L1 to Lm having a level discrimination function.
The level is discriminated by When a current flows through the data lines B1 to Bm through the Schottky diodes D, the detection circuits L1 to Lmld detect the high level signal. When no current flows through the data lines B1-Bm, the data lines B1-Bm remain at a low level.

FIG. 11 shows a configuration related to the data line decoder 2 according to another idea of the present invention. The data lines B1 to Bm are connected to a common line 11 through lv MOS transistors in the negative data line decoder 2, and are grounded through a resistor R. The level of the voltage V on the line 11 is discriminated by a detection circuit 12 which has a level discrimination function. According to this embodiment, the current flowing through the resistor R1f can be reduced by the action of the MOS transistor of the data green decoder 2, and only a single detection circuit 12 is required.

FIG. 12 shows a data line decoder 2 according to another embodiment of the present invention.
FIG. 2 is an electrical circuit diagram showing a configuration related to the above.

In this embodiment, M included in the data line decoder 2
OS) NlOS transistor 14', which is connected in common to the line 13 and serves as a switching element! i
: Grounded through. The signal from line 13 is connected to a detection port 15 with level discrimination functionality. Transistor 14H precharge (conducted by g, and at this time the detection circuit 15 is disabled). Charge it in advance by
At a subsequent timing, a current is caused to flow through the Nyoyot key diode Di. Data lines Bl-B during the precharge period
m is set to low level by a MOS) transistor 14,
After the precharge period ends, MOS transistor 1
4 is shut off, one detection circuit 15 is operated in its place, and all levels of data lines B'l-Bm are detected.

FIG. 13 shows a data line decoder 2 according to an embodiment of the present invention.
This is an electrical circuit diagram showing the configuration related to this.

Although this embodiment is similar to the embodiment of FIG.
What should be noted is that in the data line decoder 2, the data II
! IAB1 to Bm have a pair of MOS) run disk T.
It is connected to la-Tma and Tlb-Tlm, respectively. The MOS transistors Tla to Tma are commonly connected to a line 13 and grounded via a MOS transistor 14 . MOS transistors Tlb-Tmb are commonly connected to power supply voltage Vcc. The signals for selecting the MOS transistors Tla to +ma are the inverting circuits N1 to N1.
m is applied to the transistor TlbNTmb (MOS) through the metal. The unselected data lines D1 to Bm in the data line decoder 2 are set to -Jf and 71.0 by the power supply voltage Vcc. Ru. Therefore, the unselected data line Bl
-BmK does not allow almost any current to flow, and therefore, at least one electric current is good for the saw F2 wires A1 to An. The configuration of the decoder 2 shown in FIG.
The present invention can also be applied to the data line decoder 2 in FIG. 11 described above.

Although in the embodiment described above the data line decoder 2 is configured primarily in connection with the read-only memory of FIG. 2, in other embodiments the data line decoder 2 can be Appropriate and easy changes can be made accordingly. As yet another embodiment, a Schottky diode may be arranged at the famous point position of the matrix, and the circuit configuration around the Schottky diode may be configured so that no potential difference is generated between the two ends of the Schottky diode. Alternatively, the potential difference may be smaller than the potential difference across the other Schottky I-Os.

Effects As described above, according to the present invention, since Schottky diodes are selectively placed at each intersection position constituting the matrix, it is possible to reduce the general one-stop gap and achieve high density. It is possible to reduce the number of components required for each bit of data.

[Brief explanation of the drawing]

FIG. 1 is an electrical circuit diagram of the prior art, FIG. 2 is an electrical circuit diagram of an embodiment of the present invention, and FIG. 3 is a Schottky diode-F diagram.
The cross-sectional view of D, FIG. 4 shows the equivalent l'r! of the Schottky diode shown in FIG. 1, Figure 5 is a sectional view showing another configuration of Schottky diode D, and Figure 6 is 5.
An equivalent circuit diagram of the Schottky diode 1-D shown in the figure, FIG. 7 is a sectional view showing another configuration of the Schottky diode 1'D, and FIG. This is an electrical circuit related to the one-way decoder 2, such as a diode 120. ■...Two F-line decoder/driving circuit-2...Data line decoder, 1, 2...P-type silicon substrate, 2, 3,
,, N p diffusion l5jiS, 4 , 5 , 5 a ~
5 f-electrode, 7°8... connection hole, 9... insulating film,
A I-A n...Two F line-B l-B m...
Data error, D... Schottky diode agent Patent attorney Kei Nishi Part 2 Figure 2 Figure 9 Figure 10 Figure 11

Claims (1)

[Claims] Ikegata conductive type diffusion layer is made on the surface of the one-piece 7-conductor board, and metal is attached through the connection hole formed in the insulator 11 made on the surface of this board. This Schottky diode-1'woma l-I
A read-only memory characterized in that it is arranged at a J-lux intersection.