JPS60140750A - Read-only memory - Google Patents

Abstract

PURPOSE:To obtain a ROM, access time thereof is very short and the degree of integration thereof is high, by forming reverse condution type bit lines to the surface layer section of one conductive type semiconductor substrate through diffusion, forming a gate between these bit lines through a thin insulating film, coating the whole surface with an insulating film and boring an opening, and applying a word line to the gate while being extended on the insulating film. CONSTITUTION:Reverse conduction type bit lines BL are formed to the surface layer section of one conduction type semiconductor substrate S through diffusion, and a gate G is shaped through a thin insulating film OX while being held by these bit lines, thus constituting a MOS capacitance MC by these bit lines, insulating film and gate. An insulating film is applied on the whole surface, a through-hole C is bored made to correspond to the gate G, and a word line WL is applied to the gate G while being extended on the film. According to such constitution, pulse voltage is applied only to the word line WL selected by an address recorder, and a circuit ST initially setting the potential of the bit lines before starting access and a sense amplifier SA are connected to the bit lines BL.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a high-speed, highly integrated read-only memory (FIOM).
).

Configuration of conventional example and its problems ROM encodes data “O゛,” “1°” by photomask pattern for LSI manufacturing [Mask ROMJ and by applying voltage etc. after being manufactured into a product. Programmable ROM that allows coding
Although it is classified as J, here we will show the integration degree of the conventional example for the former mask ROM.

Consider response speed.

First, FIG. 1 is a plan view of a type of mask ROM emphasizing response speed, and FIG. 2 is a circuit diagram of the same type.

WL is the word line - BL, , BL2, BL, ,
BL4 each indicates a bit line. BL2 and BL4
The bit line is electrically connected to the through hole C formed in the impurity diffusion layer on the surface of the semiconductor substrate. The word line WL is usually formed of a conductive material on a thin insulating film on a substrate, and also serves as a gate of a MOSFET.

As shown in FIG. 2, the drain of a MOS transistor is connected to BL2 and BL4, but BLl.

It is not connected to BL3. When configuring ROM,
A sense amplifier SA and a load element ZL are attached to each bit line. For example, in this case, a resistor is provided between the load element and VDD. Initially, all word lines WL are set to below the threshold voltage of the MOS (MOS) transistor (and -MOS), so that no current flows through the load resistor regardless of whether or not it is connected to the drain of the transistor, and the potential of the bit line is -1N below VDD. It is. When the next word is selected and accessed, the WL constant potential becomes equal to or higher than the threshold potential - current flows through the MOS transistor in the bit where there is a through hole, and the potential of one bit line decreases. If this is detected by a sense amplifier and reproduced as a code, the operation of the ROM is completed.

It is said that the shorter the ROM access time Lace (the time between inputting an address signal and outputting data), the higher the performance, and -tacc generally consists of the following three components.

Lacc = t* + UB+ ts −■−・・−
・−・=−=(1) However, 1. ．． tA Time from near address signal input until pulse is applied to WL at address decoder output.

tB: Time for the bit line potential to change after a pulse is applied to WL.

t, s: The time it takes for the sense amplifier to detect a change in the potential of the (bi, ) line and finish reproducing it as output data.Here, we will evaluate 1B in FIG. 1. The total capacitance of the bit line is aB-1i (osl-transistor ON)
When the resistance is γON, the potential change of the bit line (if there is a through hole) has the following time constant.

τ1 ”” Tag −GB ~ tB ...Self...
...... (2) τ1 is usually several tens of nanoseconds, and the access time (7) Even when combined with other components tAN'S, the overall access time is around 100 nanoseconds. A ROM with a high speed can be obtained. On the other hand, with ROM 1)
The required area for the hit is the area around the through hole, Ac.

MOS) Area of the lunge stacker AM*v8B This is the sum of the area Ass of the diffusion layer portion and is relatively large.

A+=Ac+AM+Ass・・・・・・・・・−(3)
Next, FIG. 3 shows another conventional example of ROM.

However, in this figure, only three WLs are shown for the sake of simplicity, but in reality, about several dozen to one hundred WLs are arranged in parallel. In this case as well, WL is also used as the gate of the MOS transistor, as in the previous example. The circuit for one song is shown in Figure 4. In this case, all bits constitute MOS transistors, which are connected in series in the bit line direction. Coding (“0”.

The designation of "1°" is done by distinguishing the threshold voltage of the MOS transistor.In other words, in the bit corresponding to "1", the threshold voltage is negative (that is, even if the potential of WL is 0, the MOS transistor is ON). The threshold voltage corresponding to "0" is positive (that is, when the potential of -WL is O, the MOS transistor is turned off).

The ROM access operation is performed as follows. First, all WLs are set to a high potential (usually VDD), and then only the selected word line is set to 0 potential. For example, if WLl is set to 0 potential, -BL, , M, O8 corresponding to BL3)
The transistor is OFF and -BL2 is -ON. As in the case of Fig. 1, when a load element Zl is attached to the side opposite to V8S in the bit line direction, a current flows through each ZL and a potential drop occurs, and this is detected by all sense amplifiers SA, so the potential is low. has been detected. When the next word line selectively goes to ○ potential, the coding turns off the id (MOS) transistor at "o" and there is no current, so the voltage drop across ZL disappears and the voltage becomes "1".
For the bit corresponding to °
Therefore, there is still a voltage drop. When the sense amplifier identifies this difference and reproduces it as a code, the ROM operation is completed.

Evaluating the access time in this method.

The total capacitance of the parts connected in series in the line direction is cB (
This value is almost the same as the previous example).

It changes with the time constant of τ2=CB1ZLtB. However, the value of ZL must be set to a value similar to the sum of the ON resistances of the MOS transistors connected in series in the directions (bi, ), otherwise it will be difficult to detect "0°" and "1°", so τ2 z CB − N・γ0do〜shiB・・・・・・
(4) That is, -τ2 is about several tens of times as large as τ1. In fact, access to a ROM using this method often takes several microseconds. On the other hand, as shown in Figure 3, the area per bit A2 is only the area of the MO8) transistor, so A2 = AM, which is 1/4 to 1/4 of the previous example.
It is enough. The characteristics of the conventional example can be summarized above.

1. Although the density is not good, it is a type that can be accessed at relatively high speed (
NOR type: Figure 1) 2. Good integration, but slow access type (NAND type:
However, there is now a need for a ROM that can be accessed at high speed and has a high degree of integration.

Purpose of the Invention The present invention makes these possible, and is extremely fast (
A ROM (faster than the conventional NOR type) can be realized with a high degree of integration.

Structure of the Invention The present invention provides a structure in which a gate-type field-effect capacitor having a drain formed of an impurity diffusion layer of a second polarity is selectively placed on the surface of a semiconductor capacitor containing an impurity of a first polarity at the positions of lattice points in a matrix. forming a second polarity impurity diffusion layer array that connects the drains in a row, and disposing means for setting this potential and means for detecting the potential at one end of the diffusion layer array, and 1. A read-only memory comprising a wiring row that connects each gate of the insulated gate field effect capacitor in a row, and a means for applying a voltage to the wiring at one end of the wiring row.

DESCRIPTION OF THE EMBODIMENTS Each bit of the ROM of the present invention consists of a so-called MO3 capacity. FIG. 5 shows a configuration example, and FIG. 6 shows an equivalent circuit. Figure 6(a) is a plan view, [Yes]) is a detailed view thereof, (C
) is a thin cross-sectional view of the fiber taken along line xx′ of b. WL is a word line, and for example, metal wiring line -BL is a bit line, which is made up of a high concentration impurity diffusion layer on the surface of the semiconductor substrate S with a polarity opposite to that of the substrate. Each bit consists of an MO3 capacitor MO with a gate d and a thin insulating film OX and a semiconductor substrate.
OM Human data is coded by coding "0°", "1°'" or by creating a bit that does not constitute the MO3O3 capacitance.One end of the word line has a memory selected by an address decoder like a normal ROM. Norx drive circuit that applies pulse voltage only to WL (
(not shown) is provided, and a circuit ST and a sense amplifier SAi are installed at one end of the B,) line to initialize the potential of the B) line before access is started.

The output state of ST is controlled by a control signal CT.

When CT is "1", the output becomes the input reference voltage VR -C
When T is "o", it is in a high impedance state. Next, the operation of this configuration will be explained.

Before starting access without switching, the potential of the bit line is set using an ST circuit. The set potential V is.

When the word line potential VG before the start of access is applied to the gate of each MO8 capacitor (VGVR), this MO8
Select a value slightly lower than the threshold voltage of the capacitor. That is, at this time, all MO3 capacitors are in the OFF state.

Next, a WL (for example, WLl) is formed according to the input address signal.
) is selected, a pulse is applied to the WL by the WL drive circuit. By this pulse, all the MO8 capacitors connected to this WLl are turned on, and WLl and "1" are connected to each other.
It is capacitively coupled to the bit line coded . Therefore WL.

The voltage pulse located above reaches the sense amplifier SA directly via this capacitive coupling. The total capacity of each B, ) line is CB, each M
If the capacitance of the O8 capacitor when it is ON is Cox, the pulse signal amplitude vsig when input to the sense amplifier is Vs1g=VwL-COx/cB -+++++++
+(5) However, +VWL is the pulse amplitude above Wl.

(00”/CB) is about 1/3o to 1/2o fx (
7) If the T-Seph7 amplifier is appropriately designed, it can be detected sufficiently.

Comparing the access time and degree of integration of the ROM of the present invention with the conventional example, the access time (tacc) is broken down into three elements: tacc = ti + tB + ts, and ti and ts are the same as in the conventional example. On the other hand, regarding tB, the input signal is instantaneously divided into voltages and propagated to the sense amplifier due to capacitance division, as seen from equation (5) in terms of two equivalent circuits.

tB=o・・・・・・・・・・・・−・・・・・・・・・・
...-...+6). Therefore, access time is shorter than any conventional type.

Next, regarding the degree of integration, the area occupied per bit is 5.

A5 = AM + As s Therefore, it is considerably larger than the conventional example explained in FIG.

Note that the connection between the word line and bit line is not MO8 capacitance.
It is also possible to couple directly by capacitance, but in this case -
) The total capacitance OR of the line becomes larger (one capacitor is connected in parallel to each coupling part), the signal amplitude reaching the sense amplifier becomes smaller, and the time it takes to output the sense amplifier increases. It gets bigger, which is a disadvantage. However, if the word line and bit line are connected by the MO8 capacitor as in the present invention, the MO3 connected to the word line unrelated to access
By lowering the gate potential of the capacitor below the threshold voltage, the capacitance between unrelated word lines and each pictoline is almost eliminated.
CB becomes extremely small and a ROM with good characteristics can be obtained.

Effects of the Invention According to the present invention, it is possible to obtain a ROM with extremely short access time, sufficiently high degree of integration, and good characteristics.

[Brief explanation of the drawing]

Figure 1 is a memory cell pattern diagram of a conventional high-speed NOR type ROM, Figure 2 is an equivalent circuit diagram of the high-speed NOR type ROM shown in Figure 1, and Figure 3 is a diagram of a conventional high-density NANI) fiRO.
Memory cell pattern diagram of M - Figure 4 is an equivalent circuit diagram of the highly integrated NAN II type ROM shown in Figure 3, Figure 6 (a)
, (b) is an equivalent circuit diagram of an embodiment of the present invention. w t, (wLl, WL2, wL5)...
・Word line - BL...Beep) line, S...
・Semiconductor substrate, G...Gate, MO...
・uos volume z-c・・・Through hole-8T・・
...Potential setting circuit, SA...Sense amplifier. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure C Figure 2 Figure 3 Figure 4 Ot O OO ot

Claims (3)

[Claims] (1) On the surface of the semiconductor substrate containing impurities of the first polarity,
a second polarity impurity diffusion layer array in which insulated gate field effect capacitors having drains made of second polarity impurity diffusion layers are selectively arranged at matrix-like lattice point positions, and the second polarity impurity diffusion layer columns are coupled to the drains; a means for setting this potential and a means for detecting the potential are disposed at one end of the diffusion layer array, and
A read-only memory characterized in that a wiring row is formed that connects each gate of the insulated gate field effect capacitor in a row, and means is provided at one end of the wiring row for applying a voltage to the wiring. (2) Means for applying a voltage is disposed at one end of the second polarity impurity diffusion layer array, and means for setting the potential of this wiring and means for detecting the potential are also provided at one end of the wiring row. A read-only memory according to claim 1. (3) Claims characterized in that insulated gate field effect capacitors are formed at all lattice points in a matrix, and the wiring provided in one row is selectively coupled to the insulated gate field effect capacitors. The read-only memory described in paragraph 1.