JPS59178748A - Laser processing method - Google Patents

Laser processing method

Info

Publication number
JPS59178748A
JPS59178748A JP58052365A JP5236583A JPS59178748A JP S59178748 A JPS59178748 A JP S59178748A JP 58052365 A JP58052365 A JP 58052365A JP 5236583 A JP5236583 A JP 5236583A JP S59178748 A JPS59178748 A JP S59178748A
Authority
JP
Japan
Prior art keywords
laser
irradiation
integrated circuit
semiconductor integrated
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58052365A
Other languages
Japanese (ja)
Inventor
Mikio Hongo
幹雄 本郷
Takeoki Miyauchi
宮内 建興
Takao Kawanabe
川那部 隆夫
Morio Inoue
井上 盛生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58052365A priority Critical patent/JPS59178748A/en
Publication of JPS59178748A publication Critical patent/JPS59178748A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To enable to relieve an integrated circuit of defects with high yield by a method wherein the following processing is performed while measuring the characteristic of said circuit, when the wirings at a specific part of said circuit are connected or cut by irradiating this part with a laser, and then the laser processing condition is varied so as to obtain desired characteristic. CONSTITUTION:The characteristic of a chip 11 is measured by making probers 13a and 13b connected to a tester 14 abut against the pads 12a and 12b of the chip low resistant polycrystalline Si wirings 3 and 4, a high resistant polycrystalline Si wiring 5, and the Al electrode pads 12a and 12b are formed. At this time, the laser light 7 from a laser oscillator 15 is passed through a laser light intensity adjuster 18 controlled by a controlling device 16 and then condensed by means of an objective lans 19, resulting in irradiation on the wiring of the light. Thus constructed, the output of the laser light 7 is adjusted by rotating a deflection plate provided in the adjuster 18, and then these wirings are connected or cut so that the resistance value obtained by the tester 14 becomes a desired value.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は半導体集積回路にレーザ光を照射して処理を行
う方法に係り9%にレーザ光により半導体集積回路内の
配線を接続、あるL”は切断する方法に関するものであ
る。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of processing a semiconductor integrated circuit by irradiating it with laser light. relates to the method of cutting.

集積回路内の配線の一部を切断または接続(短絡)する
ことによシ、製作済の集積回路チップにプログラム(回
路変更)を行うことができる。従来、このプログラム(
回路変更)は。
By cutting or connecting (short-circuiting) some of the wiring within the integrated circuit, it is possible to program (circuit change) the fabricated integrated circuit chip. Traditionally, this program (
circuit change).

例えば、読み出し専用メモ+) (ROM )のフ゛ロ
グラム、あるいは最近ではメモリ素子の欠陥セルの救済
に利用されている。これらの従来法として (1)  レーザにより外部から光学的にエネルギを与
えてPo1y−5iあるいはAt、ニクロム等の配線の
特定部を切断する。
For example, it has been used to repair defective cells in read-only memory (ROM) or, more recently, in memory devices. These conventional methods include (1) applying optical energy from the outside using a laser to cut a specific portion of wiring made of Po1y-5i, At, nichrome, or the like;

(2)  レーザにより外部から光学的にエネルギを与
えてPo1y−5i配線(低抵抗部)の一部に設けられ
た高抵抗部(不純物が何もドープされていな(ても良い
)とその周辺部にレーザを照射して高抵抗部を低抵抗化
することより接続する。
(2) A high-resistance part (not doped with any impurity is allowed) and its surroundings is provided in a part of the Po1y-5i wiring (low-resistance part) by applying optical energy from the outside with a laser. The connection is made by irradiating the high resistance part with a laser to lower the resistance.

が知られている。It has been known.

いずれの方法でも、ROM等の場合には、あらかじめ決
められた部分や欠陥セルの救済に利用する場合にはメモ
リテスタ等での試験結果から決まる部分に、あらかじめ
設定された条件、即チ一定のレーザ・パワーおよび一定
のパ、ルス数を照射して、切断、接続等の処理を行って
いる。
In either method, in the case of ROM, etc., preset conditions, i.e., constant Processes such as cutting and connecting are performed by irradiating laser power and a certain number of pulses.

しかし、一般的にはレーザが照射される部分であるPo
1y−5z 、 AL、ニクロム等で形成された配線は
、Sin、、 PSG (リンガラス)、S乙5N輪S
iO等の単層あるいはそれらの複数の層からなるパッシ
ベーション膜で覆われた状態で処理され、必要に応じて
特に切断を行った場合には最終的なパッシベーション膜
を形成する。ここで配線部の上に形成されたパッシベー
ション膜を通してレーザを照射すると、パッシベーショ
ン膜厚の変動により、干渉効果のため反射率が太きく変
動し、結果的に配線部に入力するレーザパワーが変動し
てしまう。そのため、切断を行う場合には、一定条件で
レーザを照射しても、配線が切断できなかったり、基板
にまでダメージが生じたりしてしまう。また接続を行う
場合には一定条件でレーザを照射しても、接続できなか
ったり、配線が切断されてしまったりして。
However, in general, Po
Wiring made of 1y-5z, AL, nichrome, etc. is Sin, PSG (phosphorus glass), S5N ring S
It is processed while being covered with a passivation film consisting of a single layer of iO or a plurality of these layers, and if necessary, cutting is performed to form a final passivation film. If a laser is irradiated through the passivation film formed on the wiring section, the reflectance will fluctuate sharply due to the interference effect due to variations in the passivation film thickness, and as a result, the laser power input to the wiring section will fluctuate. I end up. Therefore, when cutting, even if the laser is irradiated under certain conditions, the wiring may not be cut or the substrate may be damaged. Also, when making connections, even if the laser is irradiated under certain conditions, the connection may not be made or the wiring may be cut.

歩留りが低いと込う問題があった。これを防ぐために、
バ、シベーション膜厚を一定にする努力がなされている
が、極めて困難であるのが現状である。
There was a problem with low yield. To prevent this,
Efforts have been made to keep the thickness of the scivation film constant, but it is currently extremely difficult.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来技術の欠点をなくし、R
OM (Read 0nly Memory)、  P
LA (Pro、q−rama、hlt Logic 
Array)  のプログラム、あるいはメモリ素子を
はじめ半導体集積回路の欠陥救済に適用可能なレーザ処
理を高歩留りで実施できる方法を提供することにある。
The object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and to
OM (Read Only Memory), P
LA (Pro, q-rama, hlt Logic
It is an object of the present invention to provide a method that can perform high-yield laser processing that can be applied to programs such as arrays or to repair defects in semiconductor integrated circuits including memory devices.

〔発明の概要〕[Summary of the invention]

本発明は、プロセス上のばらつきにより必要とするレー
ザ条件が被処理導体集積回路毎に異なっても、その半導
体集積回路の特性をモニタしながら、順次レーザ条件を
変えて照射し、最適な特性が測定されたところでレーザ
照射を完了することにより、高品質で、高歩留りに半導
体集積回路のレーザ処理を行うものである。
Even if the required laser conditions differ for each conductor integrated circuit to be processed due to process variations, the present invention enables irradiation by sequentially changing the laser conditions while monitoring the characteristics of the semiconductor integrated circuit to obtain the optimum characteristics. By completing laser irradiation at the point where the measurement has been completed, laser processing of semiconductor integrated circuits can be performed with high quality and high yield.

〔発明の実施例〕[Embodiments of the invention]

以下1図に従って本発明の実施例について説明する。ま
ず、本発明をレーザによる配線接続に適用した場合につ
いて述べる。第1図は一般的な配線接続部の構造を示す
図であf)−5i基板1に被着した5in2膜2により
基板1と絶縁された2つの1形Po1y−5i (多結
晶シリコン層)6゜4が極めて高抵抗の(例えば109
0カ以上)Poly−5L層(不純物がドープされてい
々くとも良い)からなる2層5を介在して対向して因る
配線構造を持ち、それらの上に絶縁膜8.絶縁膜9゜絶
縁膜10が形成されて因る。ここでn形層3゜4および
2層5は厚さが100〜5 Q Q nmであり?形層
3,4はリンまたはヒ素が、不純物濃度10’8/c、
7以上にドープされている。また絶縁膜8は、厚さが2
0−2020−200rL〜2000.J )の5 t
 O2膜、絶縁膜9はi−11−1Q%のリンを含む1
00100−1000a、1−1μm)の厚さのリンガ
ラス膜(PSG膜)、絶縁膜10は厚さがsho−40
00rLm(0,!5−4μm) の、5i02または
SiOまたけSiNの単独あるいはそれらの複数の膜か
ら成っている最終的な絶縁膜(Final Pa5si
vtuion膜)である。
An embodiment of the present invention will be described below with reference to FIG. First, a case will be described in which the present invention is applied to wiring connection using a laser. Fig. 1 is a diagram showing the structure of a general wiring connection part. f) Two 1-type Po1y-5i (polycrystalline silicon layers) insulated from the substrate 1 by a 5in2 film 2 deposited on the -5i substrate 1. 6°4 has extremely high resistance (for example, 109
0 or more) Poly-5L layers (which may be doped with impurities) have a wiring structure facing each other with two layers 5 interposed therebetween, and an insulating film 8. This is because the insulating film 9° and the insulating film 10 are formed. Here, the n-type layer 3°4 and the 2nd layer 5 have a thickness of 100 to 5 nm. The shaped layers 3 and 4 are made of phosphorus or arsenic, with an impurity concentration of 10'8/c,
It is doped to 7 or higher. Further, the insulating film 8 has a thickness of 2
0-2020-200rL~2000. J) of 5t
The O2 film and the insulating film 9 contain i-11-1Q% phosphorus.
The insulating film 10 has a thickness of sho-40.
00 rLm (0,!5-4 μm), the final insulating film (Final Pa5si
vtuion membrane).

第1図に示した配線接続部に対して、絶縁膜8.9.1
0に対して十分に透明な波長のレーザ光7をrL+形P
o1y−5i層3,4およびt層5に照射すると適正な
レーザ条件のもとでは、L層5にn・形層3,4または
PSGS2O2ちらが、あるいは両方からリンが拡散し
、L層5は低抵抗化する。この時、絶縁膜8,9.10
には、はとんど損傷を与えない。ここで、適正なレーザ
条件とは、例えばQスイッチYAGレーザの第2高調波
を用いて、1〜2パル、x T P o l y−5i
 配線部を断線に致らしめるパワー密度の1/2ノパワ
一密度で数パルスル数10パルス照射する条件である。
Insulating film 8.9.1
The laser beam 7 with a wavelength sufficiently transparent to 0 is rL+ type P.
When the o1y-5i layers 3, 4 and the T layer 5 are irradiated, under appropriate laser conditions, phosphorus diffuses into the L layer 5 from either the n-type layers 3, 4 or PSGS2O2, or both. becomes low resistance. At this time, insulating films 8, 9, 10
causes almost no damage. Here, appropriate laser conditions are, for example, using the second harmonic of a Q-switched YAG laser, 1 to 2 pulses, x T P o l y-5i
The condition is to irradiate several pulses and several ten pulses at a power density of 1/2 of the power density that causes the wiring part to break.

また、ここで、低抵抗化により接続された状態とは、高
抵抗Po l y−5i層(L層)5の抵抗値が105
Ω以下に低下した状態を言う。これはレーザ照射前の高
抵抗Po1y−5i層(L層)5の抵抗値10°Ω以上
と比較すると104以上の変化であり、完全に短絡状態
、即ち接続状態と見なして差支えない。
In addition, here, the state of connection due to low resistance means that the resistance value of the high resistance Poly-5i layer (L layer) 5 is 105
This refers to the state in which the resistance has decreased below Ω. This is a change of 104 or more compared to the resistance value of 10[Omega] or more of the high-resistance Po1y-5i layer (L layer) 5 before laser irradiation, and can be regarded as a completely short-circuited state, that is, a connected state.

しかしながら、半導体チップを製造する工程において、
絶縁膜8,9.IQの膜厚を常−に一定に保つことは極
めて回廊である。ここで絶縁膜8.9.IQの膜厚が変
化した場合について述べる。絶縁膜10をSL O2の
単層膜とすると、絶縁膜8.9.10ともに波長532
4,4 (YAGレーザの第2高調波)に対して屈折率
1.45と考えて差支えなく、吸収も無視できるから、
絶縁膜8,9゜10を全体として一層の絶縁膜と考える
ことができる。この時、 YAGレーザの第2高調波を
上記構造に垂直に入射した場合の絶縁膜の膜厚と反射率
の変化をSiの屈折率を43として第2図に示す。この
図かられかる様に2n= ’836.’iを周期に反射
率は約11%〜39%の範囲で変化する。(λは入射光
の波長、ルは絶縁膜の屈折率)即ち一一部の出力のレー
ザ7を照射した場合、実効的にPo1y−5i層3,4
.5で吸収されるレーザ拳エネルギは照射エネルギに対
して61%〜89%の範囲で変化することを示している
However, in the process of manufacturing semiconductor chips,
Insulating films 8, 9. It is extremely difficult to keep the IQ film thickness constant. Here, the insulating film 8.9. A case where the IQ film thickness changes will be described. If the insulating film 10 is a single layer film of SL O2, the wavelength of all insulating films 8, 9, and 10 is 532.
4,4 (second harmonic of YAG laser), it can be safely assumed that the refractive index is 1.45, and absorption can be ignored.
The insulating films 8, 9 and 10 can be considered as one insulating film as a whole. At this time, changes in the film thickness and reflectance of the insulating film when the second harmonic of the YAG laser is incident perpendicularly to the above structure are shown in FIG. 2, assuming that the refractive index of Si is 43. As you can see from this figure, 2n = '836. The reflectance changes in the range of about 11% to 39% with a cycle of 'i. (λ is the wavelength of the incident light, and L is the refractive index of the insulating film.) In other words, when irradiating the laser 7 with a part of the output power, the Po1y-5i layers 3 and 4 are effectively
.. 5 shows that the absorbed laser fist energy varies in the range of 61% to 89% with respect to the irradiation energy.

次に絶縁膜1oとして窒化シリコン膜の単層膜を用いた
場合について述べる。窒化シリコンの532島に対する
屈折率は約20である。前述のごとく絶縁膜8と絶縁膜
9は膜厚がそれぞれ2o〜200rLm 、  110
0−10007L、 Tあルカ光学的に?−1ffテア
リ、120〜1200n、m の絶縁膜と考えることが
できる。また絶縁膜10は500〜4ooorLrIL
  である。
Next, a case will be described in which a single layer film of silicon nitride film is used as the insulating film 1o. The refractive index for 532 islands of silicon nitride is approximately 20. As mentioned above, the insulating film 8 and the insulating film 9 have a film thickness of 20 to 200 rLm and 110 rLm, respectively.
0-10007L, T alka optically? -1ff tear, 120 to 1200nm, it can be considered as an insulating film. In addition, the insulating film 10 is 500 to 4ooorLrIL
It is.

ここで絶縁膜8.9の合計を6AOnm−絶縁膜1゜を
1400ルm とする。第3図に絶縁膜8,9を640
nmに固定して、絶縁膜10が120(1−1600n
mの範囲で変化した場合、第4図に絶縁膜10を140
01Lmに固定して、絶縁膜8.9が400〜8007
Lmの範囲で変化した場合の反射率の変化を示す。各々
Here, the total of the insulating film 8.9 is 6 A Onm - the insulating film 1° is 1400 lumen. Insulating films 8 and 9 are shown at 640 in Figure 3.
The insulating film 10 is fixed at 120 nm (1-1600 nm).
When the insulating film 10 is changed in the range of 140 m as shown in FIG.
Fixed to 01Lm, insulating film 8.9 is 400 to 8007
It shows the change in reflectance when changing within the range of Lm. Each.

12%〜61%、0.4%−61%の範囲で変化してい
る。
It varies in the range of 12% to 61% and 0.4% to 61%.

これらの膜厚と反射率の関係は1例えば、裳華房 金庫
、藤原 共著 「薄膜(応用物理学選書3 ) J P
、227から求めた。ff[Iち、絶縁膜8゜9.10
の膜厚により反射率が1%以下から61%まで変化する
。このことは、レーザ出力が一定でも−Po1y−5i
層3,4.5への実効的なレーザ入力は39%−99%
の間で変化することを意味しており、例えばレーザ出力
を1μJ一定で照射してもPo1y−8i層3,4.5
で吸収されるエネルギは039μJ〜099μJの範囲
でばらつく。このことは、レーザ出力が常に一定でも、
吸収エネルギが少ないため、低抵抗化が起こらない場合
や。
The relationship between these film thicknesses and reflectance is 1. For example, see "Thin Films (Applied Physics Selection 3)", co-authored by Kinko Shokabo and Fujiwara, JP
, 227. ff[I, insulating film 8°9.10
The reflectance varies from 1% or less to 61% depending on the film thickness. This means that even if the laser output is constant, -Po1y-5i
Effective laser input into layers 3, 4.5 is 39%-99%
For example, even if a constant laser output of 1 μJ is applied, the Po1y-8i layers 3, 4.5
The energy absorbed by this varies in the range of 039 μJ to 099 μJ. This means that even if the laser output is always constant,
Because the absorbed energy is small, resistance may not be lowered.

吸収エネルギが多すきてPo1y−5i層3.d、5が
損傷を受ける場合が生じ、接続の歩留りが低いと論う問
題が生じる。しかも、第3図および第4図に示した変化
は一方の膜厚を一定にした場合の特性であるが、実際に
は両方の膜厚が同時に変化するため、それぞれが1or
Lm変化するだけで1反射率が太きく変化する場合もあ
る。この他 n+型Po1y−5i層3,4の不純物濃
度、PSG9中のリン濃度、を層5の長さ等、チップ製
造上のばらつき、さらにレーザ出力のバラつきも考慮す
ると、歩留り低下は著しい。
Po1y-5i layer 3. absorbs a lot of energy. d, 5 may be damaged, resulting in a problem of low connection yield. Moreover, the changes shown in Figures 3 and 4 are the characteristics when one film thickness is kept constant, but in reality, both film thicknesses change simultaneously, so each has a 1or
There are cases where the reflectance changes significantly just by changing Lm. In addition, considering the impurity concentration of the n+ type Po1y-5i layers 3 and 4, the phosphorus concentration in the PSG 9, the length of the layer 5, etc., variations in chip manufacturing, and variations in laser output, the yield decreases significantly.

本発明の実施例によるレーザ処理方法を第5図に示す。A laser processing method according to an embodiment of the present invention is shown in FIG.

第5図においては説明を簡単にするため、1テツプ11
上に1ケ所の配線接続部が形成された場合を示している
。即ち、チップ11の上には低抵抗Po1y−5i 3
 、 4および高抵抗Po1y−5i5からなるPo1
y−5i配線が形成されており。
In Fig. 5, 1 step 11 is shown to simplify the explanation.
A case is shown in which one wiring connection portion is formed on the top. That is, on the chip 11 there is a low resistance Po1y-5i 3
, 4 and high resistance Po1y-5i5
y-5i wiring is formed.

その両端にはAt電極(バッド)12が設けられ。At both ends thereof, At electrodes (buds) 12 are provided.

コレらAl−電極12a 、  12bIc フo−ハ
13(Z 、  13bが接触しておp、テスタ14で
At電極間の抵抗値が測定できる構成になっている。な
お、第5図における配線接続部は第1図に示した構造と
同一であるが、簡単にするためにバ、シベーション膜等
は省略して示している。
These Al-electrodes 12a, 12b and Ic are in contact with each other, and the resistance value between the At electrodes can be measured with the tester 14.The wiring connection in FIG. The structure is the same as that shown in FIG. 1, but for the sake of simplicity, the parts such as the wafer and the scivation film are omitted from the illustration.

またレーザ発振器15から発振されたレーザ光7は制御
装置16によって駆動されるレーザ光強度調整器18を
通過して、対物レンズ19により集光されてPo1y−
5i配線上に照射される。ここで、テスタ14は常に一
定電圧を印加して−Po1y−5i配線部3,4.5に
流れる電流から抵抗値を測定する。レーザ発振器15は
1例えば、QスイッチYAGレーザの第2高調波を発生
するものであり、レーザ光強度調整器18は、偏光板を
回転させることにより透過率を連続的に変化させる形式
、ガラス円板上に円周方向に連続的に膜厚を変えた金属
蒸着膜により連続的に変化させる形式、あるいけ電気光
学効果による変調器等を用いることができる。
Further, the laser beam 7 oscillated from the laser oscillator 15 passes through a laser beam intensity adjuster 18 driven by a control device 16, and is focused by an objective lens 19.
5i wiring is irradiated. Here, the tester 14 always applies a constant voltage and measures the resistance value from the current flowing through the -Poly-5i wiring sections 3 and 4.5. The laser oscillator 15 is one that generates the second harmonic of a Q-switched YAG laser, for example, and the laser light intensity adjuster 18 is a glass circular type that continuously changes transmittance by rotating a polarizing plate. It is possible to use a method in which the thickness is continuously changed using a metal vapor deposited film that is continuously changed in the circumferential direction on a plate, or a modulator using an electro-optic effect.

ここで先ず、レーザ光強度調整器18の透過率が十分に
低い状態で、即ち十分に弱いレーザ出力で配線接続部に
一部バルヌ数だけ照射する。
First, in a state where the transmittance of the laser beam intensity adjuster 18 is sufficiently low, that is, with a sufficiently weak laser output, a portion of the wiring connection portion is irradiated by the Barne number.

照射後、テスタ14で抵抗値を測定し、設定した抵抗値
に達しない場合、制御装置16によりレーザ光強度調整
器18の透過率を少し増大させ、即ち−Po1y−5i
配線部に照射されるレーザ出力を増大させて一定パルス
数だけ照射する。再び、テスタ14により抵抗値を測定
し、設定抵抗値まで低下しない場合には、さらにPo1
y−5i配線部に照射されるレーザ出力を増大させなが
ら、一定パルス数ずつの照射を繰返えす。
After irradiation, the tester 14 measures the resistance value, and if the set resistance value is not reached, the control device 16 slightly increases the transmittance of the laser beam intensity regulator 18, that is, -Po1y-5i.
The laser power irradiated onto the wiring section is increased and irradiated with a fixed number of pulses. The resistance value is measured again by the tester 14, and if it does not decrease to the set resistance value, Po1 is further measured.
Irradiation is repeated with a constant number of pulses while increasing the laser output irradiated to the y-5i wiring section.

抵抗値が設定抵抗値せで低下した時点で、レーザ照射を
停止すれば良い。実験の結果この時の累積照射パルス数
とレーザ出力(相対値)および照射後の抵抗値の関係は
第6図に示すクロ〈である。第6図の特性図においてA
はレーザ出力を、Bは抵抗値を示している。
Laser irradiation may be stopped when the resistance value decreases to the set resistance value. As a result of the experiment, the relationship between the cumulative number of irradiation pulses, the laser output (relative value), and the resistance value after irradiation is as shown in FIG. In the characteristic diagram of Figure 6, A
indicates the laser output, and B indicates the resistance value.

これは、まず相対レーザ出力o5に設定して2゜パルス
照射し、その直後に測定した抵抗値が1090と照射前
と変化していないことを示す。次に相対レーザ出力を1
.0に設定して20パルス、相対レーザ出力を1.5に
設定して20パルスと順次、相対レーザ出力を0.5ず
つ増加させガから20パルスずつ照射したが、相対レー
ザ出力3.O1累積照射パルス数120パルスまで変化
が見られなかった。
This shows that first, the relative laser output was set to o5 and 2° pulse irradiation was performed, and the resistance value measured immediately after was 1090, which was unchanged from before the irradiation. Next, set the relative laser output to 1
.. The relative laser output was set to 0 for 20 pulses, the relative laser output was set to 1.5 for 20 pulses, the relative laser output was increased by 0.5, and the moth was irradiated with 20 pulses at a time, but the relative laser output was 3. No change was observed until the O1 cumulative irradiation pulse number reached 120 pulses.

しかし、相対レーザ出力3.5で20パルス(累積照射
パルス数140パルス)照射すると、抵抗値は1011
01で低下し、レーザ出力はそれ以後65に固定したi
tさらに照射を続けると累積照射パルス数280パルス
で約103Ω(1XΩ)マで低下した。
However, when irradiating 20 pulses (cumulative irradiation pulse number 140 pulses) with a relative laser output of 3.5, the resistance value is 1011
01, and the laser output was fixed at 65 from then on.
When irradiation was continued, the cumulative number of irradiation pulses was 280, and the resistance decreased to about 103Ω (1XΩ).

第6図は低抵抗化の特性を調べるため、300パルスま
で照射しているが、実際には104Ω以下が得られると
接続が完了したと考えることができるから、累積照射パ
ルス数180パルスを照射したところで照射を終了すれ
ば良い。なお、第6図に示した実験結果では十分に低い
相対レーザ出力から開始しているが、パッシベーション
膜厚のばらつきによる反射率のばらつきや、プロセス上
のばらつきを考慮して、低抵抗化が起こる可能性のある
最も低いレーザ出力から開始すれば良い。また、レーザ
出力の設定間隔は十分に小さい方が望ましいが、処理時
間の点から最適レーザ出力に対して配線部がダメージを
受けるレーザ出力までの間を3〜4分割する程度でも良
い。
In Figure 6, up to 300 pulses are irradiated to examine the characteristics of low resistance, but in reality, the connection can be considered complete when a resistance of 104Ω or less is obtained, so the cumulative number of irradiation pulses is 180. At this point, the irradiation can be finished. Note that although the experimental results shown in Figure 6 start with a sufficiently low relative laser output, a reduction in resistance occurs when considering variations in reflectance due to variations in passivation film thickness and variations in process. Just start with the lowest possible laser power. Further, it is desirable that the setting interval of the laser output is sufficiently small, but from the viewpoint of processing time, the interval between the optimum laser output and the laser output that causes damage to the wiring portion may be divided into 3 to 4.

また、第6図において相対レーザ出力35で20パルス
照射して抵抗値が1050捷で低下した後。
In addition, in FIG. 6, after 20 pulses were irradiated with a relative laser output of 35, the resistance value decreased by 1050 mm.

相対レーザ出力を変化させずに、照射を続けているが、
相対レーザ出力440に変化させて照射しても裏込。
Irradiation continues without changing the relative laser output, but
Even if the relative laser output was changed to 440 and irradiation was performed, back-filling occurred.

次に1本発明の処理方法を半導体メモリの冗長化手法(
欠陥ビットの救済)に適用した場合について第7図にそ
の具体的構成例を示し、説明する。すなわち、第7図に
示すように、半導体メモリチップ20の上に設けられた
バンプ(At等で形成された電極)21には−プローブ
カード22からプローブ23が押当てられ、メモリテス
タ24により、メモリチップ20の検査が行なわれる。
Next, we will introduce the processing method of the present invention as a semiconductor memory redundancy technique (
FIG. 7 shows a specific configuration example of the case where the present invention is applied to the repair of defective bits. That is, as shown in FIG. 7, a probe 23 from a probe card 22 is pressed against a bump (electrode made of At or the like) provided on a semiconductor memory chip 20, and a memory tester 24 presses a probe 23 from a probe card 22. The memory chip 20 is tested.

通常ウェハ状態でX−Yステージ等に軟量され、1チツ
プずつ、プローブカード22で検査を行うが、同図では
1チツプのみ示しである。メモリテスタ24での検査結
果に基づき、欠陥が発見された場合に、その欠陥を救済
するための特定の配線接続部にレーザを照射する。レー
ザ発振器15は、例えば、QスイッチYAGレーザと第
2高調波発生器から構成され、それから発振されたL/
−f[7id−レーザ光強度調整器18により任意に設
定された強度で対物レンズ19により集光されて、チッ
プ20上に照射される。また制御装置25は、レーザ光
強度調整器18の透過率調整の制御およびレーザ発振器
15のオン、オフ制御をメモリテスタ24の結果に基づ
−て行うようにしである。
Normally, the wafer is mounted on an X-Y stage or the like and inspected one chip at a time using a probe card 22, but only one chip is shown in the figure. When a defect is found based on the inspection result of the memory tester 24, a laser is irradiated to a specific wiring connection portion to remedy the defect. The laser oscillator 15 is composed of, for example, a Q-switched YAG laser and a second harmonic generator.
-f[7id- The laser beam is focused by the objective lens 19 at an intensity arbitrarily set by the laser beam intensity adjuster 18, and is irradiated onto the chip 20. Further, the control device 25 is configured to control the transmittance adjustment of the laser light intensity adjuster 18 and to control the on/off of the laser oscillator 15 based on the results of the memory tester 24.

第7図において−まずメモリテスタ24にょシ検査を打
込、チップ上に欠陥が発見された場合。
In FIG. 7, the memory tester 24 is first tested and a defect is found on the chip.

チップ(またはウェハ)が載置されているX−Yヌテー
ジ、あるいはガルバノメータ等にょるレーザ光走査装置
(これらは図示していない)により、欠陥を救済するた
めの配線接続部に位置決めする。ここで、制御装置25
により、レーザ光強度調整器18の透過案を十分に低く
、即ち十分に小さなパワー密度で配線接続部に一部パル
ヌ数1例えば20パルス照射する。
The chip (or wafer) is positioned at the wiring connection part for repairing the defect using an X-Y nutage on which it is mounted, or a laser beam scanning device such as a galvanometer (not shown). Here, the control device 25
As a result, a part of the wiring connection portion is irradiated with a transmission signal of the laser beam intensity adjuster 18 at a sufficiently low power density, that is, a Parnu number of 1, for example, 20 pulses.

レーザ照射後、再びメモリテスタ24による検査を行い
、欠陥部が救済されたかどうかを調べ、救済されていな
い場合には、制御装置25により。
After the laser irradiation, the memory tester 24 performs an inspection again to check whether the defective part has been repaired or not. If the defective part has not been repaired, the control device 25 performs an inspection.

レーザ光強度調整器1Bの設定を、透過率が増加する様
に変え、再び同一箇所に一部パルス数だけ照射する。照
射後、検査を行い欠陥部が救済される1で、制御装置2
4によりレーザ光強度調整器18の透過率の設定を順次
増大させ々から。
The settings of the laser beam intensity adjuster 1B are changed so that the transmittance increases, and the same spot is again irradiated with a partial number of pulses. After irradiation, an inspection is performed to repair the defective part 1, and the control device 2
4, the transmittance setting of the laser light intensity adjuster 18 is increased sequentially.

即ち、配線接続部に照射されるレーザエネルギーを順次
増大させながら、照射、検査を繰返えす。メモリテスタ
2Aによる横倉結果で、欠陥部が救済された時点でその
チップに対するレーザ照射は終了し、ウェハの場合には
−X−Yステージを1チツプ分移動させ、チップの場合
には新しいチップと交換して、検査からの手順を繰返え
す。ここで、1ケ所の欠陥を救済するために。
That is, the irradiation and inspection are repeated while sequentially increasing the laser energy irradiated to the wiring connection portion. According to Yokokura's results using Memory Tester 2A, when the defective part is repaired, the laser irradiation to that chip ends, in the case of a wafer, the -XY stage is moved by one chip, and in the case of a chip, a new chip is placed. Replace and repeat the procedure from inspection. Here, to remedy one defect.

複数ケ所を接続する必要がある場合には、検査と必要な
箇所の全てを−通り照射する手順を繰返えせは良い。
If multiple locations need to be connected, it is a good idea to repeat the inspection and irradiation procedure to all required locations.

次に別な実施例について示す。例えば、第2図に示した
様に、反射率の変化が比較的小さく、チップ製造上のプ
ロセスのばらつきも小さい場合には、配線接続部に照射
するレーザ出力を変化させhくとも、照射パルス数を変
えるだけで良い。
Next, another example will be described. For example, as shown in Figure 2, if the change in reflectance is relatively small and the variation in the chip manufacturing process is also small, the irradiation pulse Just change the numbers.

第8図に、レーザ出力を固定した場合の照射パルス数と
抵抗値の関係を、反射率が十分に低くかつ接続しやすい
場合をA曲線で9反射率が高くかつ接続しに〈因場合を
8曲線で示す。実験によれば接続しやすい場合には、6
0パルスで抵抗低下が始まり、80パルス照射後には1
040以下まで低下している。この後も20パルスずつ
照射し続けたところ、累積照射パルス数220・<ルス
でダメージが生じた。一方、接続しにくい場合は、30
0パルスで低下が見られ、340パルスで1040まで
低下した。即ち、レーザ出カ一定の1まで、一定パルス
数ずつ照射して、照射後の抵抗値、あるいは回路全体の
特性から目的の接続が行なわれたかどうかを判定し、接
続が不十分な場合には、さらに一定パルス数の照射およ
び測定または検査を繰返えすことによp、第5図あるい
は第7図で述べた方法と同一の効果を得ることができる
Figure 8 shows the relationship between the number of irradiation pulses and the resistance value when the laser output is fixed. Curve A shows the case where the reflectance is low enough and it is easy to connect. 8 curves. According to experiments, when connection is easy, 6
The resistance starts to decrease at 0 pulses and decreases to 1 after 80 pulses.
It has decreased to below 040. After this, when irradiation was continued at a rate of 20 pulses, damage occurred when the cumulative number of irradiation pulses was 220<rus. On the other hand, if it is difficult to connect,
A decrease was seen at 0 pulses, and decreased to 1040 at 340 pulses. In other words, the laser output is irradiated with a fixed number of pulses up to a constant level of 1, and the resistance value after irradiation or the characteristics of the entire circuit are used to determine whether the desired connection has been made. By further repeating irradiation with a fixed number of pulses and measurement or inspection, the same effect as the method described in FIG. 5 or FIG. 7 can be obtained.

以上1本発明をROMへの書込み、あるいは半導体メモ
リの欠陥セル救済を目的とした配線接続に適用した場合
について説明して来たが、同様の目的のため、配線切断
を行うために適用した場合も全く同じ効果が得られる。
Above, we have described the case in which the present invention is applied to wiring connection for the purpose of writing to ROM or relieving defective cells in semiconductor memory, but when it is applied to cutting wiring for the same purpose You can get exactly the same effect.

即ち、反射率が高すぎたりすると切断部への芙効的hレ
ーザφエネルギが低(なり切断できなかったp。
That is, if the reflectance is too high, the effective h laser φ energy to the cutting part will be low (and the cutting will not be possible).

反射率が低すぎると、切断部への実効的なエネルギが高
すぎ、基板に損傷を与えたりする。しかし、本発明を適
用して、確実に基板に損傷を与えないレーザエネルギー
から、1パルス照射し、断線の成否あるいは全体の特性
からの判断により、順次にレーザエネルギーを増大させ
ながら測定、検査とレーザ照射を繰返えすことにより、
基板への損傷のない確実な配線切断を行うことができる
ことは明らかである。
If the reflectance is too low, the effective energy applied to the cut will be too high and may damage the substrate. However, by applying the present invention, one pulse is irradiated with a laser energy that does not cause damage to the substrate, and measurement and inspection are performed while increasing the laser energy sequentially based on the success or failure of disconnection or judgment from the overall characteristics. By repeating laser irradiation,
It is clear that wiring can be cut reliably without damage to the board.

また、用いるレーザとして1本実施例でけQスイッチY
AGレーザの第2高調波を用いた場合について断切して
来たが、それに限定されるものでなく、パルス発振、C
’lF(連続)発振によらず1才だ波長にもよらず、同
じ効果が得られることは明らかである。
In addition, in this embodiment, a Q switch Y is used as a laser.
Although we have discussed the case of using the second harmonic of an AG laser, it is not limited to this, and pulse oscillation, C
It is clear that the same effect can be obtained regardless of the wavelength, regardless of the 'lF (continuous) oscillation.

〔発明の効果〕〔Effect of the invention〕

以上の説明からも明らかなように本発明によれば一半導
体集積回路の特性を測定しながら順次レーザの照射条件
を変えて照射し、最適な処理が得られた時点でレーザ照
射を完了することによって所期の特性を有する半導体集
積回路を得るものであるから、常に最適条件で高品質。
As is clear from the above description, according to the present invention, while measuring the characteristics of a semiconductor integrated circuit, the laser irradiation conditions are sequentially changed and the laser irradiation is completed when the optimum processing is obtained. This process produces semiconductor integrated circuits with the desired characteristics, so high quality is always achieved under optimal conditions.

高歩留りにレーザ処理が行なえる効果がある。The effect is that laser processing can be performed with high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の適用対象である半導体集積回路の配線
接続部の構成図、第2図〜第4図は半導体集積回路の膜
厚が変化した場合の反射率の変化を示す図、第5図は本
発明の詳細な説明する具体的な装置構成図、第6図は累
積照射パルス数およびレーザ出力と抵抗値の関係を示す
図、第7図は本発明の別な実施例を示す装置構成図、第
8図はレーザ出力を一定にした場合の照射パルス数と抵
抗値の関係を示す図である。 1−5i基板      2 ・5in2膜3、4  
・・n+形Po1y−5i層  5−・i層8.9.1
0・・・絶縁膜    7・・レーザ光13.23・・
・グローブ   1A、2A・・・テスタ15・・・レ
ーザ発振器 18・・・レーザ光強度調整器 19・対物レンズ 第17 第2凶 絶縁膜膜厚罰爪) 第、3図 ! 手U象膜1oの膜厚(几爪) 第47 季色縁膜890合有士師厚(7L m)第s区 第6図 累Jl各珪トマルス婁父 狛゛7図 第8図 Oyoo     200    300    40
0案オN!l!’A寸ノ寸λレス倭欠、
FIG. 1 is a configuration diagram of a wiring connection part of a semiconductor integrated circuit to which the present invention is applied, FIGS. 2 to 4 are diagrams showing changes in reflectance when the film thickness of the semiconductor integrated circuit changes, and FIG. FIG. 5 is a diagram showing a specific device configuration for explaining the present invention in detail, FIG. 6 is a diagram showing the relationship between cumulative irradiation pulse number, laser output, and resistance value, and FIG. 7 is a diagram showing another embodiment of the present invention. The apparatus configuration diagram, FIG. 8, is a diagram showing the relationship between the number of irradiation pulses and the resistance value when the laser output is kept constant. 1-5i substrate 2 ・5in2 film 3, 4
・・n+ type Po1y-5i layer 5-・i layer 8.9.1
0... Insulating film 7... Laser light 13.23...
-Gloves 1A, 2A...Tester 15...Laser oscillator 18...Laser light intensity adjuster 19 -Objective lens 17 (Second insulating film thickness penalty) Figure 3! Thickness of hand U quadrant 1o (Tsume) No. 47 Seasonal membranous membrane 890 Gouji Shishi thickness (7L m) S section No. 6 Figure 1 300 40
0 plan yes! l! 'A size λ less wa missing,

Claims (1)

【特許請求の範囲】 (1)  半導体集積回路の特定部分にレーザを照射し
、該半導体集積回路の被照射部の配線接続切断等を行な
うことによって特性を変化させ任意の特性を有する半導
体集積回路を得るレーザ処理方法において、前記半導体
集積回路の特性を測定しながら該半導体集積回路の所期
の特性が得られるまで順次レーザ処理条件を変化させて
レーザ照射を行なうことを特徴とするレーザ処理方法。 り2)  前記半導体集積回路の特性測定は、該半導体
集積回路全体の特性測定であることを特徴とする特許請
求の範囲第1項に記載のレーザ処理方法。 (3)  前記半導体集積回路の特性測定は、レーザ照
射部の特性測定であることを特徴とする特許請求の範囲
′5I−14虹1にすし一7’熟押大銭・(4)  前
記レーザ照射条件は、照射レーザ・エネルギーを充分に
低い値から順次増大させながら一部パルス数〔あるいは
一定時間)ずつ照射することを特徴とする特許請求の範
囲第1項に記載のレーザ処理方法。 、(5)  前記レーザ照射条件は、累積照射、<ルス
数(あるいは累積照射時間)を順次増大させることを特
徴とする特許請求の範囲第1項に記載のレーザ処理方法
[Scope of Claims] (1) A semiconductor integrated circuit having arbitrary characteristics whose characteristics are changed by irradiating a specific portion of the semiconductor integrated circuit with a laser and cutting or disconnecting wiring in the irradiated portion of the semiconductor integrated circuit. A laser processing method for obtaining a semiconductor integrated circuit, characterized in that while measuring the characteristics of the semiconductor integrated circuit, laser irradiation is performed while sequentially changing laser processing conditions until the desired characteristics of the semiconductor integrated circuit are obtained. . 2) The laser processing method according to claim 1, wherein the characteristic measurement of the semiconductor integrated circuit is a characteristic measurement of the entire semiconductor integrated circuit. (3) The characteristic measurement of the semiconductor integrated circuit is characterized in that the characteristic measurement of the laser irradiation part is performed.(4) The laser beam 2. The laser processing method according to claim 1, wherein the irradiation condition is that the irradiation laser energy is sequentially increased from a sufficiently low value and irradiation is performed in increments of a certain number of pulses (or for a certain period of time). (5) The laser processing method according to claim 1, wherein the laser irradiation condition is such that cumulative irradiation and <number of ruses (or cumulative irradiation time) are sequentially increased.
JP58052365A 1983-03-30 1983-03-30 Laser processing method Pending JPS59178748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58052365A JPS59178748A (en) 1983-03-30 1983-03-30 Laser processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58052365A JPS59178748A (en) 1983-03-30 1983-03-30 Laser processing method

Publications (1)

Publication Number Publication Date
JPS59178748A true JPS59178748A (en) 1984-10-11

Family

ID=12912775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58052365A Pending JPS59178748A (en) 1983-03-30 1983-03-30 Laser processing method

Country Status (1)

Country Link
JP (1) JPS59178748A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0325234A2 (en) * 1988-01-20 1989-07-26 Kabushiki Kaisha Toshiba Trimming element for microelectronic circuit
EP0388341A2 (en) * 1989-03-14 1990-09-19 International Business Machines Corporation Method and apparatus for causing an open circuit in a conductive line
JPH0541426A (en) * 1991-12-02 1993-02-19 Tokyo Electron Ltd Wafer probe for eprom and wafer prober for redundancy of memory chip

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0325234A2 (en) * 1988-01-20 1989-07-26 Kabushiki Kaisha Toshiba Trimming element for microelectronic circuit
EP0388341A2 (en) * 1989-03-14 1990-09-19 International Business Machines Corporation Method and apparatus for causing an open circuit in a conductive line
JPH0541426A (en) * 1991-12-02 1993-02-19 Tokyo Electron Ltd Wafer probe for eprom and wafer prober for redundancy of memory chip

Similar Documents

Publication Publication Date Title
JP3150322B2 (en) Wiring cutting method by laser and laser processing device
JPH07506221A (en) System and method for selective laser processing of material object structures in multi-material, multi-layer devices
JPS6122650A (en) Relief for defect and device thereof
JPH04267366A (en) Thin-film resistance and its manufacture
JP3689154B2 (en) Electronic circuit manufacturing method, semiconductor material wafer, and integrated circuit
JPS59178748A (en) Laser processing method
US4962294A (en) Method and apparatus for causing an open circuit in a conductive line
JPH11121576A (en) Equipment and method for repairing semiconductor wafer
JP2531453B2 (en) Laser processing equipment
JPS6267834A (en) Laser processing
US5126662A (en) Method of testing a semiconductor chip
KR0126101B1 (en) Forming method of repair mask
JPS5940548A (en) Semiconductor ic circuit and laser processing thereof
JP3261904B2 (en) Semiconductor device
JPH1190659A (en) Laser repairing device
JPS62176174A (en) Manufacture of photoelectric conversion device
JP2775005B2 (en) Laser cutting judgment method
JP3279296B2 (en) Semiconductor device
JP3558411B2 (en) Method for manufacturing semiconductor integrated circuit device
JPS62176173A (en) Manufacture of photoelectric conversion device
JPS5893257A (en) Connecting method and device for wirings
JPS609153A (en) Adjustment of resistance value of resistor inside semiconductor integrated circuit
JPH02215149A (en) Semiconductor device and its manufacture
JPS58171833A (en) Wiring connection by laser beam
JPH05206242A (en) Detecting equipment for void in semiconductor wafer