JPS59178678U - display device - Google Patents
display deviceInfo
- Publication number
- JPS59178678U JPS59178678U JP7224383U JP7224383U JPS59178678U JP S59178678 U JPS59178678 U JP S59178678U JP 7224383 U JP7224383 U JP 7224383U JP 7224383 U JP7224383 U JP 7224383U JP S59178678 U JPS59178678 U JP S59178678U
- Authority
- JP
- Japan
- Prior art keywords
- glass substrate
- display panel
- upper glass
- circuit board
- led out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は、本考案に用いられる薄型回路基板を作る方法
を示す平面図、第2図は、本考案の実施例を示す断面図
で、ある。
1・・・フィルム状絶縁基板、2・・・貫通孔、3・・
・支持部、4・・・薄型回路基板、5・・・導電路、6
・・・リード、7・・・半導体素子、8・・・上部ガラ
ス基板、9・・・下部ガラス基板、10・・・スペーサ
、11・・・液晶、12・・・偏光板、13・・・偏光
反射板、14.15・・・透明電極、16・・・電極、
17・・・半田。FIG. 1 is a plan view showing a method of manufacturing a thin circuit board used in the present invention, and FIG. 2 is a sectional view showing an embodiment of the present invention. 1... Film-like insulating substrate, 2... Through hole, 3...
- Support part, 4... Thin circuit board, 5... Conductive path, 6
...Lead, 7...Semiconductor element, 8...Upper glass substrate, 9...Lower glass substrate, 10...Spacer, 11...Liquid crystal, 12...Polarizing plate, 13...・Polarizing reflector, 14.15...transparent electrode, 16...electrode,
17...Solder.
Claims (1)
質が挾持され、前記上部ガラス基板の突出した部分に電
極が導出されて成る表示パネルと、0.3mm以下の絶
縁基板に、銅箔のエツチングによって複数の導電路及び
前記絶縁基板の側端から突出する複数のリードが形成さ
れ、更に、前記表示パネルを駆動するための半導体素子
あるいは電子部品等が固着された薄型回路基板とを備え
、前記表示パネルの背面に前記薄型回路基板を配置し、
前記複数のリードを前記上部ガラス基板の突出した部分
に導出された電極に半田付あるいは導電性接着剤で接着
することを特徴とする表示装置。A display panel in which a light-receiving display material is sandwiched between an upper glass substrate and a lower glass substrate, and an electrode is led out to a protruding portion of the upper glass substrate, and an insulating substrate with a thickness of 0.3 mm or less is coated with copper foil. A thin circuit board on which a plurality of conductive paths and a plurality of leads protruding from the side edges of the insulating substrate are formed by etching, and on which semiconductor elements or electronic components for driving the display panel are fixed; placing the thin circuit board on the back side of the display panel;
A display device characterized in that the plurality of leads are soldered or bonded with a conductive adhesive to electrodes led out from the protruding portion of the upper glass substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7224383U JPS59178678U (en) | 1983-05-13 | 1983-05-13 | display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7224383U JPS59178678U (en) | 1983-05-13 | 1983-05-13 | display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59178678U true JPS59178678U (en) | 1984-11-29 |
Family
ID=30202388
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7224383U Pending JPS59178678U (en) | 1983-05-13 | 1983-05-13 | display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59178678U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004246351A (en) * | 2003-01-22 | 2004-09-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic equipment |
-
1983
- 1983-05-13 JP JP7224383U patent/JPS59178678U/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004246351A (en) * | 2003-01-22 | 2004-09-02 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic equipment |
JP4689168B2 (en) * | 2003-01-22 | 2011-05-25 | 株式会社半導体エネルギー研究所 | Method for manufacturing semiconductor device |
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