JPS5917723A - Gate driving method of gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To improve the adaptability to the PWM control or the like, by providing a minimum turn-on time setting circuit in a gate control circuit of a gate turn-off thyristor and approximating the set time to the allowable minimum turn-on time as much as possible. CONSTITUTION:A snubber capacitor voltage Vcs is detected and is compared with a reference voltage Vref which is preliminarily set to a value which is higher than the steady state turn-on voltage of the gate turn-off thyristor but is sufficiently low. The time when the snubber capacitor voltage Vcs becomes lower than the reference voltage Vref is detected, and a pulse signal S7, which corresponds to a forecasted snubber constant and has a requested maximum time width, synchronized with a gate trigger signal S1 applied from the external is generated to set the minimum turn-on time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling a semiconductor device with a gate control pole,
In particular, the present invention relates to a gate drive method for a gate turn-off thyristor.

Generally, semiconductor switching elements such as thyristors or gate turn-off thyristors are widely used in power control devices such as choppers and inverters.

FIG. 1 shows an example of a power control device using semiconductor switching elements. In the figure, ■ is a DC power supply, 2 is a load circuit, and 6 is a chopper circuit.

The load circuit 2 has a load 3 connected in series to the DC power supply 1 and an inductance element, for example, a winding 4, and a freewheeling diode 5 is connected in parallel to the load circuit 2.

A gate turn-off thyristor (hereinafter referred to as GTO) 7 is used in the chopper circuit 6, and a snubber circuit 8 is added to this gate turn-off thyristor.

This is because by relaxing the dv/dt of the anode voltage that is reapplied when the gate of GTO7 is turned off, the power loss generated inside KGTO7 during this period is kept low, and GTO7 is safely turned off. belongs to.

The snubber circuit 8 is connected in parallel to a snubber capacitor 9 connected via a discharge resistor 10 between the anode electrode and the cathode electrode of G'r07, and the discharge resistor 10, and the snubber circuit 8 is connected in parallel to the snubber capacitor 9, and the snubber capacitor 9 is connected in parallel to the discharge resistor 10. The diode 11 is connected as shown in FIG.

Here, the controllable anode current (ITGQ), which is the maximum value of the turn-off anode current by the GTO 70 control electrode, is the capacitance of the snubber capacitor 9 (
It can be increased as Cs) is increased.

Generally, the snubber capacitor capacity added to a GTO is approximately one order of magnitude larger than that added to a conventional Zyrister. In particular, if you want to cut off a large current, you will have to increase the value even further.

However, increasing the capacitance value of the snubber capacitor in this way causes various drawbacks. One of them is
One example of this is that the minimum allowable on-time becomes longer. In other words, if the GTO is turned off in a time shorter than the allowable minimum on-time, the GTO will be destroyed, and the energization time width control range will become narrower.

This situation is shown in Figure 3. When the GTOK on-gate goose (PON shown in the figure) is applied and turned on, the anode current (the sum of the load current and the discharge current of the capacitor) flows, and the sunar current (the sum of the discharge current of the capacitor) flows. The voltage VC8 is attenuating. After this VC8 has been almost completely discharged, if a negative gate pulse (POFFZ in the figure) is applied to the GTO, the anode current IA2 and the anode voltage VA2 in FIG. On the other hand, in order to shorten the turn-off time (as shown in P.
. FFI), the voltage of the capacitor is high (・
When a turn-off gate current is applied, it remains at the anode of the GTO, as shown by VAI in the figure, and rises to the snubber capacitor voltage with an almost infinite d1/dt.

In addition, the waveform becomes a superimposed waveform of the orgasm voltage,
Power loss during turn-off becomes extremely large and the GTO is destroyed.

Furthermore, the application of dv//dt, which is close to infinity, causes false ignition, and the same <GTO is destroyed. Therefore, in order to safely turn off the GTO, the turn-off gate current must be applied after the charge accumulated in the snubber capacitor is sufficiently discharged. In other words, a minimum on-time must be ensured.

In order to solve the above problems, conventionally, a minimum on-time is set using a circuit as shown in FIG. 4, so that the on-time does not exceed the minimum allowable on-time of the GTO.

That is, in FIG. 4, 12 is a monostable multipipe rake, 13 is an OR gate that receives the output signal of the monostable multino(ibrator) 2, 14 is an amplifier, and 15 is an inverting amplifier. The minimum on-time is set by the monostable multi-gulator 12.

As shown in FIG. 5, when the output signal S1 of the gate trigger signal generator (not shown) is applied to the input terminal 12a,
In synchronization with this signal, a monostable multi-noise (ibrator 12) operates, and its output signal S2 is input to one input terminal of the OR gate, and the signal S1 applied to the input terminal 12a is directly input to the other input terminal. .

Therefore, at the output terminal of the OR gate, a pulse signal S3 having a time width equal to one of the input pulse of the input terminal 12a of the monostable multivibrator 120 and the output pulse of its output terminal, which has a wider pulse width, appears. . This output signal is amplified by an amplifier 14 to produce an off-gate pulse S4, and on the other hand, inverted and amplified by an inverting amplifier 15 to produce an off-gate pulse S5.
O can be fully operated.

However, in the above method, it is necessary to set the snubber capacitor to operate safely even when the discharge time constant (Rs, Cs) is at its maximum within a practically conceivable range.

In other words, the time corresponding to △t in Figure 5 is longer than the minimum allowable on-time of the element, and the on-time is set to the minimum, resulting in a loss of control flexibility in pulse width modulation control (PWM control). It has some drawbacks.

Another disadvantage is that in order to avoid the above-mentioned problems, the output pulse width of the monostable multivibrator must be adjusted every time the discharge time constant of the snubber capacitor changes.

In order to turn off the gate turn-off thyristor safely, the present invention provides a minimum on-time setting circuit in the gate control circuit of the gate turn-off thyristor, and furthermore, makes it possible to bring this setting time as close as possible to the minimum allowable on-time of the element. An object of the present invention is to provide a gate drive method for a gate turn-off thyristor that can improve compatibility with PWM control and the like.

Hereinafter, a method for driving a gate turn-off thyristor according to an embodiment of the present invention will be described with reference to FIGS. 6 to 8.

FIG. 6 shows a gate driving circuit implementing the gate driving method according to the first embodiment of the present invention.

In FIG. 6, parts that are the same as or equivalent to those in FIG. 4 are given the same reference numerals.

In the same figure, reference numeral 16 indicates that the output signal S2 of the monostable multivibrator is under the single power condition, and the output signal S7 is the output signal S7 of the monostable multivibrator.
and an AND gate input to the inverting amplifier 15.

17 has a snubber capacitor voltage V at one input terminal 17a.
This is a comparator which inputs CS, the reference voltage vref for turning off the GTO at the other input terminal 17b, and inputs the output signal S6 to the AND gate 16.

In the gate drive circuit of FIG. 6, in order to ensure the minimum allowable on-time of the element corresponding to the maximum snubber constant (Cs, Rs) that can be considered, the monostable multivibrator 12 is used to control the signal S2 of FIG. A pulse having a time width (13-1o) as shown is generated in synchronization with the gate trigger signal Sl.

In this state, the narrow gate trigger signal S1 is input to input terminal 1.
2a, the monostable multi-bi break 12 operates and outputs an output pulse signal S2.

At this point, the anode voltage vA of the GTO is kept at a high value determined by the power supply voltage, so the snubber capacitor voltage VC
8 is also at the same voltage.

Since the reference voltage Vref of the comparator 17 is set to a value slightly higher than the on-voltage of the GTO, the output signal S6 of the comparator 17 is at a high level.

The on-gate current amplified by the amplifier 14 is the GTO
When the voltage is applied to VCS, the GTO starts to turn on, the anode voltage A decreases, and the snubber capacitor voltage vcs decreases with a delay. In this case, the delay time is determined by the capacitance value (Cs) of the snubber capacitor and the resistance value (R
s) is determined by the time constants (Cs, Rs). This snubber voltage VC8 is applied to the comparator 1 at time t2.
70 reference voltage vref, the output signal S6 of the comparator 17 changes from high level to low level.

By taking the logical product (AND) of this output signal S6 and the output signal S2 of the monostable multivibrator 12,
The output signal S7 of the ant gate is a gate trigger signal S,
The snubber capacitor voltage VC rises in synchronization with the rise of VC.
It is possible to create a pulse that sets an on period (t2-tO) that stops at the time t2 when 8 becomes lower than the reference voltage (vref, ).

The off-pulse signal S9 is the output signal S7 of the ant gate 16.
is obtained by inverting and amplifying the signal using the inverting amplifier 15.

According to the game 1 driving method according to the first embodiment of the present invention,
The minimum on-time that must be ensured to safely gate turn off the GTO is optimized (minimum necessary).
can be set to narrow pulse width (for PWM control, etc.).
・When control is required, the scope of control can be expanded.

Further, according to the first embodiment, various snubber constants (Cs,
There is no need to re-set the conditions for Rs) each time the constant changes, and the optimum minimum on-time can be automatically determined.

FIG. 8 shows a gate control circuit for implementing the gate 1 driving method according to the second embodiment of the present invention.

In this gate drive circuit, an OR gate 18 is provided on the output side of the AND gate 16.

The OR gate 18 uses the gate trigger signal S1 and the output signal S7 of the AND gate 16 as input conditions, and inputs the output signal S8 to the amplifier 14 and the inverting amplifier 15V.

According to the gate driving method according to the second embodiment of the present invention, the trigger signal S1 is directly input to one input terminal of the OR gate 18, and the output signal S7 of the ant gate 16 is input to the other input terminal. Ru. Therefore, Antogame 1.
Since the trigger signal S1 is supplied to the OR gate 18 even if the output signal S7 of the gate 16 becomes a low level, the output signal -j'J8 of the OR gate 18 becomes a high level, and the ON signal S8 continues to be applied to the gate of the GTO. You can keep the flow flowing.

Furthermore, when a signal whose pulse width of the gate trigger signal S1 is longer than the pulse width of the output signal of the monostable multivibrator 12 is input, the signal SIa shown in the figure is directly input to the subsequent amplifier 14 and is amplified. and is output as an on signal S8a. When the output signal S8a of the OR gate stops, the off signal S is inverted and amplified from the dotted line portion of S9 in the figure and is applied to the GTO. The time can be set, and the same operation and effect as the gate driving method according to the first embodiment described above can be obtained. Furthermore, the 6th
It goes without saying that the effects of the present invention can also be obtained with a circuit that is a combination of the first embodiment shown in the figure and the second embodiment shown in FIG.

As explained above, in the gate driving method of the present invention, the snubber capacitor voltage is detected, and this detected voltage is set in advance to a value higher than the steady-state voltage of the GTO but sufficiently lower than the reference voltage I. ~, detects the point in time when the snubber condenser voltage becomes lower than this reference voltage, and generates an externally applied gate trigger signal with the maximum required time width corresponding to the expected snubber constant. This is a system that generates a pulse signal that is synchronized with the output voltage to set the minimum off time.

Therefore, according to the present invention, it is possible to improve the compatibility with PWM control, etc., and to provide a highly reliable gate driving method that can safely control the on/off of the GTO.

[Brief explanation of drawings]

Figure 1 is an electrical wiring diagram of a power control device using a gate turn-off thyristor; Figures 2 and 3 (A);
(B) is its characteristic diagram, FIG. 4 is a block diagram of a gate drive circuit of a conventional gate turn-off thyristor, FIG. 5 is a diagram showing its operation timing, and FIG.
FIG. 7 is a circuit diagram to which the gate drive method of the gate turn-off thyristor according to the embodiment is applied, FIG. 7 is a diagram showing its operation timing, and FIG. 8 is a circuit diagram to which the gate drive method according to the second embodiment of the present invention is applied. be. 12 Monostable multivibrator, 14 ・Amplifier, 15... Inverting amplifier, 16
・AND Gate, 17...Comparator, 18-OR Gate Application Agent Patent Attorney Kikuchi 5 Department

Claims (2)

[Claims] (1) Detect the snubber capacitor voltage of the snubber circuit of the gate turn-off thyristor, compare this detected voltage with a preset reference voltage at which the gate turn-off thyristor operates, and determine whether the snubber capacitor voltage is higher than the reference voltage. a first means for detecting a point in time when the gate trigger signal becomes low; and a second means for generating a signal having a maximum time width corresponding to the snubber constant of the snubber circuit and synchronized with the gate trigger signal; 1. A gate drive method for a gate turn-off thyristor, characterized in that the minimum on-time of the gate turn-off thyristor is set by the AND of each signal obtained by the first means and the second means. (2) Detect the snubber capacitor voltage of the snubber circuit of the gate turn-off thyristor, compare this detected voltage with a preset reference voltage at which the gate turn-off thyristor operates, and determine whether the snubber capacitor voltage is higher than the reference voltage. a first means for detecting the point in time when the snubber constant of the snubber circuit becomes low, and a second means for generating a signal having a maximum time width corresponding to the snubber constant of the snubber circuit and synchronized with the gate trigger signal applied from the gate trigger signal generator. 2 means, and the minimum on-time of the gate turn-off thyristor is set by the logical sum of the gate trigger signal and a signal obtained by ANDing each signal obtained by the first means and the second means. A gate driving method for a gate turn-off thyristor.