JPS59176922A - Multi-processing type delay circuit - Google Patents

Abstract

PURPOSE:To obtain an economical multiplex digital signal delay circuit by holding the 1-frame preceding data through a selector until the count value of a multi-processing type counter reaches the set value and then delivering the input signal as it is when the said count value reaches the set value. CONSTITUTION:A multiplex digital signal Ii of a multiplex degree (n) is supplied to a level change detecting circuit 1. The circuit 1 checks the level change of an input signal Ii-1 preceding the signal Ii by a frame for each channel and delivers the detection signal Vi to a multi-processing type counter 2. The count value Ai of the counter 2 obtained for each channel is compared 3 with the delay set amount D set to a comparator 3. The comparator 3 delivers the control signal Ci of a low level to a selector 4 when Ai>D is satisfied. Then the selector 4 selects the signal Ii and delivers a signal Oi. A shift register 5 supplies the signal Oi-1 delayed precedingly by a frame to the selector 4 when the signal Oi is inputted. The selector 4 keeps the signal Oi-1 and delays it until the value Ai of the counter 2 reaches the set amount D. When the value Ai reaches the amount D, the selector 4 delivers the input signal as it is.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a delay circuit that can delay multiplexed digital signals for an arbitrary period of time.

Conventionally, when delaying a digital signal, a very long shift register is used.

Alternatively, there is a method in which a retrigger type monostable multivibrator is used to delay the signal level by an arbitrary amount of time.

However, in the former method using a shift register, it takes 800xu(n
This method requires a bit shift register (multiplicity), which significantly increases the number of components, and the latter method using a retrigger type monostable multivibrator has the disadvantage that when the input digital signal is not multiplexed, is valid, but if the input signal is multiple digital signals.

Once decomposed into n signals, each n signal has n pj l-! The disadvantage is that it is necessary to input the I into the monostable multi-bi break in the form and to mix the signals output from the re-trigger mono-stable multi-bi break with multiple digital signals, and the number of parts increases as the degree of multiplicity increases. was there.

1. The object of the present invention is to solve the 1. conventional drawbacks.

It is an object of the present invention to provide a delay circuit capable of delaying multiple digital signals with an economical configuration with a small number of parts.

According to the present invention, a multiplexed digital signal is inputted, and a means for detecting a change in level between the input signal and an input signal one frame before for each channel, and a multiplex processing that is reset for each channel upon receiving this detection signal. a type counter, means for generating a control signal by comparing the d1 value for each channel outputted from the multiprocessing type counter with a preset value, and receiving the multiplex digital signal as a first input signal. The selector includes a selector and a shift register that inputs a signal whose output from the selector is delayed by one frame as a second input signal to the selector, and the selector inputs the first input signal according to the control signal. A multi-processing type delay circuit is obtained, which is characterized in that it switches and outputs the selector and the second input signal, and uses the output of the selector as the output signal of the circuit.

That is, in the multiprocessing type delay circuit of the present invention.

When the input multiplex digital signal does not change, it is taken out as an output signal, and when the level of the input signal changes, that is, when it rises or falls, the 2 selector continues to output the data from the previous frame, thereby changing the input. Try not to tell them. Then, at this change point, the multi-processing type counter is reset, and the selector continues to hold the data of -1- one frame before until the count value of this counter reaches a preset value, and the 3! When the honor value reaches a preset value, the selector 9 outputs the input signal as it is. In this way, a change in the input signal is transmitted to the output only after the multiprocessing counter is reset and the count value reaches a preset value.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiprocessing type delay circuit according to the present invention. In the figure, 1 is a multiplex digital signal Ii (I
i-Ii(1), ll(2),...

I i (71,)) is input, and for each channel, the level change between this input signal 1 and 1 Freno, the previous input signal 1-1, 1-nawa b level changes from high level to low level, or A level change detection circuit 2 detects a change from a low level to a high level, and 2 is a detection signal vj (V
i = Vi(1), Vi(2L --, Vi(1)
), 6 is the count value Ai for each channel output from the multiprocessing counter 2 (Ai=Ai(j), Ai(
2) Ai(n)) is compared with a preset delay setting time to determine the control signal Cj for each channel.
, (C1-C1(1), C1(2),...
, Ci(?z) ) is a selector that inputs the input signal 1 as one input signal, and 5 is the output signal 0i (Oi-Oi (1) , Oi ) of the selector 4.
(2) Input ,...,Ol(η)) to 1
The selector 4 is an n-bit shift register that outputs the output signal 01-1 of the Freno selector 4.

This output signal 01-1 is input as the other input signal, and the signal 11 and this signal 01-1 are switched and outputted by the control signal C1 output from the comparator 6.

Next, the operation of the circuit shown in FIG. 1 will be explained.

After the multiplex digital signal input to this circuit changes,
Assume that a sufficient amount of time has passed without any change in the input signal (1-1) of the immediately previous frame. At that time, in the previous frame, the count values A1-1 for each channel output from the multiprocessing counter 2 all hold the maximum value Amax, and the preset delay setting t D (D >"0"
), the 1 selector 4 selects and outputs ti-1 using the control signal C1-1, which is all low level, for each channel and is output from the comparator 6. Therefore 9 selector 4
The output signal 01-1 is the input signal 11-1 input to one side.
is equal to

In this state, now k (1≦
≦rl ) channel signal l1(k) (however.

1 (chai, ru may have multiple channels),
Assume that the channel signal and level of the input signal 1-1 of the straight curve frame change 1, for example, from a low level to a high level. At this time, the level change detection circuit 1 detects this change, and this detection signal Vi(k) causes the multi-processing counter 2's 1 (Char's 81 value Ai(k) to
The comparator 3 sets the control signal CI to high level when the count value A1 of the multiprocessing counter 2 is smaller than the delay setting value, so the comparator 3 sets the control signal CI to high level. The channel control signal C1(k) becomes the noise level at the moment when the count value Ai(k) of 0°' becomes 0°'.At this time, the shift register 5 is set to the noise level.

1 frame 1iJ of data o of output signal 01 of selector 4
Since the input signal T1-+ (-11,-+) is output, the 1 selector 4 switches the channel to the input signal T1-1 one frame earlier during the input signal generator 1 and outputs it.

Thereafter, while the count value Ai+t (kNτ>t≧1) of the multiprocessing counter 2 is smaller than the delay setting, the output Oi −4−j of the 9 selector 4 remains 01, The count value of the channel is counted in the multiprocessing counter 2, and at a certain time 1-τ, the count value Ai+r(1
') matches the delay setting (Ai + T (g)) = D)
When the control signal C1+τ(
k) becomes low level again.

The output signal 01+τ of the selector has the input signal ■1+7(Il
+r-Ii+t (r≧t≧0)) is output as is. Therefore, at this point, changes in the input are transmitted to the output for the first time.

Set the delay to get a delay of seconds.

D-125 x 1 leaf 6 = 8000 The deviation is good.

Father, if you increase the time it takes for multiprocessing counter 2 to count one count (for example, once every 1-7L seconds).

The delay time can be increased accordingly.

Note that the explanations above are based on the assumption that the input signal does not change from the time the level change detection circuit 1 detects the level change until the predetermined delay time τ elapses. If the time from when the detection circuit 1 detects a level change to when it detects the next level change is shorter than the delay time τ, the count value of the multi-processing counter 2 will change to the delay setting fR.
Since it is reset to °0'' again before reaching D, 1
If we focus on one channel.

This delay circuit operates similar to a retriggered, stable multi-by-break.

As is clear from the above explanation, according to the present invention, even when a long delay such as 1 second or 10 seconds is required, it is only necessary to change the delay setting amount, and since it is possible to handle digital signals with multiplexed inputs. This has the effect of being widely applicable to general digital circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiprocessing type delay circuit according to the present invention. DESCRIPTION OF SYMBOLS 1... Level change detection circuit, 2... Multiprocessing type counter, 3... Comparator, 4... Selector, 5... Shift register.

Claims (1)

[Claims] 1. Means for receiving a multiplex digital signal and detecting a change in level between the input signal and the input signal one frame before in channel 4o, and resetting for each channel upon receiving the detection signal. means for generating a control signal by comparing the count value of channel 4 output from the multi-processing counter with a preset value; The selector includes a selector input as a signal, and a shift register that inputs a signal obtained by delaying the output of the selector by one frame to the selector as a second input signal. A multi-processing type delay circuit, characterized in that the first input signal and the second input signal are switched and outputted, and the output of the selector is used as the output signal of the circuit.