JPH06303226A - Automatic phase control circuit - Google Patents

Abstract

PURPOSE:To automatically control the phase of input data and that of an input frame pulse as against an input clock. CONSTITUTION:Delay insertion circuits 4 and 5 giving stepwise micro delay to input data 1 and the input frame pulse 2 are provided. Flip flops 10 and 9 latching a delay frame pulse 7 outputted from the delay insertion circuit 5 by the positive phase and the inverse phase of an input clock 3 and a phase judgement circuit 13 inputting the respective outputs of the flip flops 9 and 10 are provided. An up down counter 14 is operated by an up pulse 20 and a down pulse 21, which the phase judgement circuit 13 outputs, and the delay quantity of the phase delay circuit is controlled by the output counter signal 22.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic phase control circuit for a data receiving circuit having input data, an input clock and an input frame pulse indicating the beginning of the data.

[0002]

2. Description of the Related Art An example of a conventional data receiving circuit will be described with reference to FIG. As shown in FIG. 6, the conventional data receiving circuit includes a flip-flop 44 which receives the input data 41 and the input clock 43, and a frame counter circuit 45 which receives the input frame pulse 42 and the input clock 43.
have. In the conventional data receiving circuit of this type, the phase relationship between the input data 41, the input frame pulse 42, and the input clock 43 is phase-controlled by the circuit at the preceding stage and input to the data receiving circuit.

[0003]

In this conventional data receiving circuit, the phase relationship between the input data and the input frame pulse and the input clock needs to be designed in detail to a phase that can be safely latched, and particularly in a high speed circuit. Then, there was a problem that it was difficult to estimate the phase difference. The present invention has been made to solve such a problem, and an object thereof is to obtain an automatic phase control circuit that automatically adjusts the phases of input data and an input frame pulse with respect to an input clock.

[0004]

According to the automatic phase control circuit of the present invention, in the data receiving circuit having the input data, the input clock and the input frame pulse indicating the beginning of the data, the input frame pulse is delayed step by step. A delay inserting circuit capable of performing the above delay, a first flip-flop for inverting the input clock and latching the delayed frame pulse output from the delay inserting circuit in the opposite phase, and a delay circuit for inputting the input clock to provide a delay A second flip-flop that latches in a positive phase, a frame counter circuit that counts one frame by the delayed frame pulse and the input clock, a phase determination pulse output by the frame counter circuit, and the first and second flip-flops. The phase judgment is performed by the reverse phase pulse and the positive phase pulse output from the A determination circuit, the output of the phase determining circuit in which includes an up-down counter for adjusting the delay amount of the delay insertion circuit.

[0005]

In the present invention, the fall and rise of the input clock are used to detect the phase difference from the frame pulse and control the phase difference to the optimum value without interruption.

More specifically, the result of latching the delayed frame pulse at the rising edge of the input clock at the frame pulse position and the result of latching at the falling edge half a clock before that are compared by the phase judgment circuit, and the delayed frame pulse is compared. It is determined which phase the pulse phase is currently at with respect to the falling edge and the rising edge of the clock, and outputs up and down signals according to the phase of the delayed frame pulse and the input clock to operate the up / down counter. This counter value is input to the delay insertion circuit, and a delay corresponding to the count value is given to the input data and the input frame pulse. By repeating this operation, it is possible to always adjust the input data and the input frame to the optimum phase.

[0007]

The present invention will be described below with reference to the drawings. 1 is a block diagram showing an embodiment of an automatic phase control circuit according to the present invention. FIG. 1 is a block diagram of a data receiving circuit having an automatic phase control circuit according to an embodiment of the present invention.
FIG. 2 is a block diagram showing a configuration example of the delay insertion circuit in FIG.

In FIG. 1, reference numeral 4 is a delay insertion circuit for inputting input data 1 and outputting delay data 6, and reference numeral 5 is a delay insertion circuit for gradually delaying an input frame pulse 2 indicating the beginning of data, 8 Is a delay circuit having the input clock 3 as an input, 9 is a flip-flop for inverting the delayed frame pulse 7 output from the delay inserting circuit 5 by the inverting circuit 15 and latching it in reverse phase, and 10 is a delay circuit 8. A flip-flop that gives a delay and latches in positive phase,
Reference numeral 11 is a frame counter circuit that counts one frame by the delayed frame pulse 7 output from the delay insertion circuit 5 and the input clock 3, and 13 is a phase determination pulse 12 output from the frame counter circuit 11 and outputs from the flip-flops 9 and 10. A phase determination circuit for performing a phase determination based on the reverse-phase pulse and the positive-phase pulse.

Next, the operation of the embodiment shown in FIG. 1 will be described. First, the input data 1 is input to the delay insertion circuit 4 and the delay data 6 is output. The input frame pulse 2 takes the form of a LOW pulse of one time slot (TS) at the beginning of the frame, is input to the delay insertion circuit 5, and outputs the delayed frame pulse 7. The delayed frame pulse 7 is used as a load signal, the input clock 3 is input as an input to the frame counter circuit 11, and the phase determination pulse 12 is output as a HIGH pulse of one time slot for each frame. The phase determination pulse 12 is supplied to the phase determination circuit 13.

Next, the delayed frame pulse 7 is flipped by the flip-flop 9 and the reverse-phase clock 16 obtained by inverting the input clock 3 by the inverting circuit 15 and the positive-phase delayed clock 17 obtained by slightly delaying the input clock 3 by the delay circuit 8. Latch by 10. The negative phase latch output 18 of the flip-flop 9 and the positive phase latch output 19 of the flip-flop 10 are input to the phase determination circuit 13 to determine the phase relationship of the input frame pulse 2 with respect to the input clock 3.
An up pulse 20 and a down pulse 21 are output depending on the combination of inputs. The up pulse 20 and the down pulse 21 operate the up / down counter 14 to output a count signal 22.

The count signal 22 is input to the delay inserting circuits 4 and 5, and the delay amounts of the delay inserting circuits 4 and 5 are simultaneously adjusted according to the count value. Further, as shown in FIG. 2, the delay insertion circuit is composed of a selector circuit 34 which is only selected by the count signal 32 and a plurality of delay elements 33 which give a minute delay. The delay amount is increased by counting up and delayed by counting down. A quantity reducing operation is performed to adjust the output delay signal 35 with respect to the input signal 31.

FIGS. 3, 4 and 5 are signal waveform diagrams for explaining the operation of FIG. 1 and show signal waveforms in each case of the embodiment. FIG. 3 shows a mode in which the amount of delay is decreased by the negative phase latch output 18: LOW and the positive phase latch output 19: LOW when the phase judgment pulse 12 rises, and FIG. When 12 rises, negative phase latch output 18: HIGH, positive phase latch output 1
9: LOW shows the mode of holding the delay amount as it is. FIG. 5 shows the case where the reverse phase latch output 1 when the phase determination pulse 12 rises.
8: HIGH, positive phase latch output 19: HIGH, showing a mode in the direction of increasing the delay amount.

In the operation of the embodiment, as shown in FIG. 3, when the input data 1 and the input frame pulse 2 are delayed with respect to the input clock 3, the output of the flip-flop 9 is LOW and the output of the flip-flop 10 is Output is LO
Since it becomes W, it is determined that the delayed frame pulse 7 is delayed with respect to the input clock 3, the down pulse 21 is output from the phase determination circuit 13, the count signal 22 is counted down by one, and the delay insertion circuit 4 is accordingly responded. And 5
The control works so as to reduce each delay amount of. When this operation is repeated and the phase relationship becomes the state shown in FIG. 4, the output of the flip-flop 9 becomes HIGH and the output of the flip-flop 10 becomes LOW, which is in the safe area, and the delay amount does not change. Further, as shown in FIG. 5, when the input clock 3 is delayed with respect to the input data 1 and the input frame pulse 2, the delay amount is controlled to increase.

[0014]

As described above, according to the present invention, the phase difference from the frame pulse is detected by utilizing the falling edge and the rising edge of the input clock, so that the phase can be optimized without interruption. This has the effect of controlling and facilitates phase design in high-speed circuits.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an automatic phase control circuit according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a delay insertion circuit in FIG.

FIG. 3 is a signal waveform diagram for explaining the operation of FIG.

FIG. 4 is a signal waveform diagram for explaining the operation of FIG.

5 is a signal waveform diagram for explaining the operation of FIG.

FIG. 6 is a block diagram showing an example of a conventional data receiving circuit.

[Explanation of symbols]

 1 Input data 2 Input frame pulse 3 Input clock 4,5 Delay insertion circuit 8 Delay circuit 9,10 Flip-flop 11 Frame counter circuit 13 Phase determination circuit 14 Up-down counter

Claims (1)

[Claims] 1. A data receiving circuit having input data, an input clock, and an input frame pulse indicating the beginning of the data, and a delay inserting circuit capable of delaying the input frame pulse stepwise, and an output of the delay inserting circuit. A first flip-flop that inverts the input clock and latches the delayed frame pulse in a reverse phase, and a second flip-flop that delays the delayed frame pulse by a delay circuit that receives the input clock and latches in the positive phase. A frame counter circuit that counts one frame by using a delayed frame pulse and the input clock, a phase by a phase determination pulse output by the frame counter circuit, and a negative phase pulse and a positive phase pulse output by the first and second flip-flops. The phase judgment circuit that makes the judgment and the output of this phase judgment circuit An automatic phase control circuit, comprising: an up-down counter for adjusting the delay amount of the delay insertion circuit.