JP2001339377A - Phase adjustment circuit and phase adjustment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust timing of a clock signal so as to satisfy the timing condition of a clock signal versus a data signal in a diversion circuit in the case of inputting the clock signal and the data signal asynchronously generated to the diversion circuit for a macro or the like in a ready-made LSI. SOLUTION: A state change monitor circuit 2a outputs a reset signal when detecting an up/down edge of a CLKI and a state change monitor circuit 2b outputs a register latch instruction signal when detecting an up/down edge of DATAI. A counter 3 always counts the system clocks and is reset by a reset signal. A delay value storage register 4 stores the count of the counter 3 by a register latch instruction signal. A select value calculation circuit 5 selects any of delay signals with patterns generated by a delay circuit 6 satisfying a timing condition on the basis of the stored count and a selector 7 outputs a clock output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an off-the-shelf LSI
When an asynchronously generated clock signal and data signal are input to an electronic circuit that uses a macro or the like in the same, a clock signal is automatically generated so as to satisfy a timing condition of a clock signal to a data signal of the input macro. The present invention relates to a phase adjustment circuit and a phase adjustment method for an asynchronous signal for adjusting the timing of the asynchronous signal.

[0002]

2. Description of the Related Art In recent years, when designing an electronic circuit, it is rare to design a completely new circuit because of the rapid development speed. In most cases, an existing circuit (such as a macro in an off-the-shelf LSI) is used. The mainstream is to proceed with the design by partially diverting). In that case, the output delay time of the ready-made L
When a clock signal output from an SI or the like is used in a subsequent-stage diversion circuit, it is not unclear whether timing conditions for input to the latter-stage diversion circuit can be satisfied or not.

[0003]

In the above-mentioned diverted circuits (such as macros in off-the-shelf LSIs), the timing conditions of input signals are already defined, and the diverted circuits are provided with independently generated clocks. In the case of inputting a signal and a data signal, the timing condition of the clock signal to the data signal is often manually adjusted by using a costly delay circuit and a jumper terminal. At this time, manual work is required for each one, and a large cost is required in a test process at the time of mass production. In addition, since the adjustment is performed manually, a work error may occur.

SUMMARY OF THE INVENTION It is an object of the present invention to eliminate the need for the above-mentioned manual adjustment process and to eliminate human error, and to reduce the cost and improve the quality of the test process. And a phase adjusting method.

[0005]

A phase adjusting circuit according to the present invention monitors a state change of a clock input signal by a system clock and outputs a reset signal when a predetermined state of the clock input signal is detected. A state change monitoring circuit, a second state change monitoring circuit that monitors a state change of the data input signal by a system clock, and outputs a register latch instruction signal when a predetermined state of the data input signal is detected; A counter that always counts and is reset by a reset signal output by the first state change monitoring circuit; and a delay that latches the count value of the counter by a register latch instruction signal output by the second state change monitoring circuit. A value holding register, and a delay circuit for generating a plurality of patterns of delay signals of the clock input signal. The count value latched in the delay value holding register is pulled in, and a pattern is selected by judging which pattern of the plurality of patterns of the delay signal of the clock input signal generated by the delay circuit satisfies the timing condition. A select value calculation circuit that outputs a signal, and a selector that selects one of a plurality of patterns of delay signals of the clock input signal generated by the delay circuit based on the select signal and outputs a clock output signal. , Is provided.

The present invention is effective in increasing the development speed, reducing the cost of the test process, and improving the quality.

[0007]

Next, an embodiment of the present invention will be described with reference to the drawings.

A phase adjusting circuit according to the present invention includes a phase adjusting circuit in an electronic circuit having a configuration in which a clock signal and a data signal generated independently of a timing condition are input to a macro having a predetermined timing condition. FIG. 1 is a circuit diagram showing an embodiment of a phase adjustment circuit according to the present invention.

The phase adjustment circuit shown in FIG. 1 is a state change monitoring circuit 2 for monitoring a state change of a clock signal (CLKI).
a, a state change monitoring circuit 2b for monitoring a state change of a data signal (DATAI), a counter 3, a delay value holding register 4, a select value calculation circuit 5, a delay circuit 6, and a selector 7.

A system clock 1 for operating the present circuit
Are output to the state change monitoring circuits 2a and 2b, the counter 3, the select value calculation circuit 5, and the selector 7. CLKI
Is input to the state change monitoring circuit 2a, and the delay circuit 6
Through the selector 7. DATAI is input to the state change monitoring circuit 2b and output from the circuit as it is as DATAO.

The reset signal from the state change monitoring circuit 2a is output to the counter 3, and the count value from the counter 3 and the register latch instruction signal from the state change monitoring circuit 2b are output to the delay value holding register 4. . The register latch signal from the delay value holding register 4 is output to the select value calculation circuit 5, and the select signal from the select value calculation circuit 5 is output to the selector 7, and CLKO is output from the selector 7.

Next, the operation of the phase adjustment circuit shown in FIG. 1 will be described.

A clock signal (CLKI) and a data signal (DATAI) generated asynchronously are first input to the state change monitoring circuits 2a and 2b. The state change monitoring circuit 2a uses the system clock 1
Monitoring the up edge or the down edge of CLKI, and outputs a reset signal to the counter 3 when the up edge or the down edge is detected. The state change monitoring circuit 2b uses the system clock 1 to
Monitoring the up edge or down edge of the TAI,
When an up edge or a down edge is detected, a register latch instruction signal is output to the delay value holding register 4.

The counter 3 always counts according to the system clock 1, and the state change monitoring circuit 2a
Are reset by the reset signal output by The count value of the counter 3 is output to the delay value holding register 4 and latched in the delay value holding register 4 by a register latch instruction signal output from the state change monitoring circuit 2b.
The latched count value represents a time difference between the up edge or down edge of CLKI and the up edge or down edge of DATAI, and the time difference is represented by the product of the count value and the cycle of the system clock 1. You.

On the other hand, the CLKI is also input to the delay circuit 6, and the delay circuit 6 generates a plurality of patterns of CLKI delay signals. The selector 7 receives a plurality of delayed signals of CLKI and a select signal from the select value calculation circuit 5.

The select value calculation circuit 5 pulls in the count value held in the delay value holding register 4 and
It determines which of the plurality of delayed signals of the CLKI generated in step (1) satisfies the timing conditions of the subsequent macro, and outputs a select signal to the selector 7.

The selector 7 generates a CLK signal based on the select signal.
One of a plurality of patterns of delayed signals of I is selected and output. In this way, a clock signal (CLKO) and a data signal (DATAO) satisfying the timing conditions of the subsequent macro are generated.

As an example, the cycle of CLKI is 30 ns,
The cycle of the system clock (SYSCLK) is 1 ns, C
A case will be described in which the timing conditions of LKO and DATAO are in phase, and a delay signal of every 3 ns is prepared from 0 ns to 27 ns in the delay circuit. FIG. 2 shows a timing chart for explaining the operation, FIG. 3 shows a delay amount in the delay circuit, and FIG.
The timing conditions of ATAO are shown.

In FIG. 2, the counter is reset to 0 when a CLKI up edge is detected in SYSCLK. Similarly, when the up edge of DATAI is detected,
In FIG. 2, the count value 4 is latched. At this time, if a clock with a delay of, for example, 6 ns is selected by the delay circuit,
The timing condition of CLKO to DATAO can be satisfied with an accuracy of ± 3 ns or less. Note that the accuracy of the phase adjustment depends on the accuracy of the delay circuit to be realized.

Although the above embodiment has been described on the assumption that a clock signal output from an off-the-shelf LSI or the like whose output delay time is unclear is used in the subsequent stage, the present invention is not limited to this. The present invention is not limited to this, and can be applied to a case where a transmission delay of a clock pattern is assumed.

Further, it is assumed that the phase adjustment circuit of the present invention can be realized by a hardware description language (HDL) to verify the operation.

[0022]

As described above, conventionally, when an electronic circuit is designed by partially diverting an existing circuit, a clock signal and a data signal generated independently from each other are input to the diverted circuit. Although the timing condition between the clock signal and the data signal is manually adjusted by using the delay circuit and the jumper terminal, according to the present invention, the manually adjusted process becomes unnecessary, and Work mistakes can be eliminated. As a result, cost reduction and quality improvement in the test process are expected.

Further, according to the present invention, even when DATAI has jitter, the selector operates sequentially so as to meet the timing condition required in the subsequent stage, so that CLKI follows the jitter of DATAI. be able to. As a result, it is expected that a malfunction caused by the timing condition in the macro at the subsequent stage is prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a phase adjustment circuit of the present invention.

FIG. 2 is a timing chart illustrating the operation of the phase adjustment circuit of the present invention.

FIG. 3 is a diagram illustrating an example of a delay amount in a delay circuit.

FIG. 4 is a diagram showing an example of timing conditions of CLKO and DATAO.

[Explanation of symbols]

 Reference Signs List 1 system clock 2a, 2b state change monitoring circuit 3 counter 4 delay value holding register 5 select value calculation circuit 6 delay circuit 7 selector

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Katsutaka Sasaki 1-4-28 Mita, Minato-ku, Tokyo NEC Communication Systems Co., Ltd. F-term (reference) 5J001 AA11 BB07 DD08 5J106 AA03 CC59 DD17 DD24 DD38 DD43 EE05 GG19 HH02 5K047 AA01 AA12 GG06 GG24 GG42 JJ01

Claims (6)

[Claims] A first state change monitoring circuit for monitoring a state change of a clock input signal by a system clock and outputting a reset signal when a predetermined state of the clock input signal is detected; and a data input signal by a system clock. A second state change monitoring circuit that monitors a state change of the data input signal and outputs a register latch instruction signal when a predetermined state of the data input signal is detected; and a first state change monitoring circuit that constantly counts a system clock. And a delay value holding register that latches the count value of the counter with a register latch instruction signal output by the second state change monitoring circuit; and a plurality of patterns of the clock input signal. A delay circuit for generating a delay signal, the delay circuit being latched by the delay value holding register A select value calculation circuit that pulls in a count value, determines which pattern of the plurality of patterns of the delay signal of the clock input signal generated by the delay circuit satisfies the timing condition, and outputs a select signal. A selector for selecting one of a plurality of patterns of delay signals of the clock input signal generated by the delay circuit based on the select signal and outputting a clock output signal. Adjustment circuit. 2. The clock input signal and the data input signal are generated asynchronously, and the clock output signal is output after adjusting the timing so as to satisfy a timing condition of a clock signal to a data signal of a subsequent diversion circuit. The phase adjustment circuit according to claim 1, wherein the phase adjustment is performed. 3. The phase adjustment circuit according to claim 1, wherein the predetermined state is an up edge or a down edge of an input signal. 4. A method of monitoring a state change of a clock input signal by a system clock and outputting a reset signal when a predetermined state of the clock input signal is detected, and monitoring a state change of a data input signal by a system clock. Outputting a register latch instruction signal when a predetermined state of the data input signal is detected; constantly counting a system clock by a counter; resetting the counter by the reset signal; Latching by the register latch instruction signal; generating a plurality of patterns of delay signals of the clock input signal; pulling in the latched count value; and generating a plurality of patterns of the delay signal of the clock input signal. Which pattern is Thailand Outputting a select signal by determining whether a switching condition is satisfied; and selecting one of a plurality of delay signals of a plurality of patterns of the generated clock input signal based on the select signal to generate a clock output signal. And outputting the phase. 5. The clock input signal and the data input signal are generated asynchronously, and the clock output signal is output after adjusting the timing so as to satisfy a timing condition of a clock signal to a data signal of a subsequent diversion circuit. The phase adjustment method according to claim 4, wherein the phase adjustment is performed. 6. The phase adjusting method according to claim 4, wherein the predetermined state is an up edge or a down edge of an input signal.