KR100684399B1 - Digital clock signal generation apparatus and method regardless of input signal duty rate - Google Patents

Abstract

Disclosed are an apparatus and method for generating a digital clock signal independent of an input signal duty ratio. The digital clock signal generator includes a clock signal delay unit for delaying a clock signal to generate clock signals having a plurality of different phases; A digitizer for detecting phases of the delayed clock signals as a digital value at a rising edge of a flip-flop; A selection signal generator configured to generate a selection signal by detecting a clock edge at which the output signal values of the digitizer transition to different digital values; And a selector configured to select and output a predetermined signal among delay signals having different phases generated by the clock signal delay unit using the selection signal.

According to the present invention, it is possible to reduce the power consumption of a microprocessor operating at a low voltage and to be applied to many low power SOC products. It is also superior to the prior art in terms of locking time, area, and power consumption, and can produce an accurately delayed output even when a signal whose duty ratio is not 50% is input.

Description

Digital clock signal generation apparatus and method regardless of input signal duty rate

1 is a block diagram showing the configuration of a digital clock signal generator regardless of the input signal duty ratio according to the present invention.

Figure 2 shows a preferred embodiment of the digital clock signal generation apparatus irrespective of the input signal duty ratio according to the present invention.

3A and 3B show the structure and timing diagram of the delay element.

4A and 4B show the structure and timing diagram of the digitizer.

5 illustrates a structure of a selection signal generator.

6 shows the structure of the selection unit.

7 is a flowchart illustrating a method for generating a digital clock signal regardless of the duty ratio of the input signal according to the present invention.

FIG. 8 illustrates waveforms of a delay cell of the clock signal delay unit 200.

9 shows the simulation results of the digitizer.

10 illustrates a simulation result of the selection signal generator.

11 shows simulation results of the multiplexer of the selection unit.

<Description of the symbols for the main parts of the drawings>

100 ... clock signal generator 200 ... clock signal delay unit

220 ... first delay element string 240 ... second delay element string

300 ... digitizers 302, 304, 306, 308, 310 ... multiple inverters

312, 314, 316, 318, 319 ... Multiple Clock Delays

320, 322, 324, 326, 328 ... multiple flip-flops

400 ... selection signal generator 402, 404, 406, 408 ... multiple inverters

412, 414, 416, 418 ... logical gate

500 ... optional

The present invention relates to a clock generator, and more particularly, to an apparatus and method for generating a digital clock signal independent of the input signal duty ratio.

Chips such as microprocessors and clock data restorers require clock-on-demand capability to quickly switch between power-down and active modes to reduce power consumption at the system level. . You need a suitable 1GHz digital clock generator. In many cases, if the duty ratio of the input clock signal is not 50%, the phase error of the digital clock generator may increase. In addition, a delay cell is required to lock in two cycles, operate at low voltages, and the design must be optimized to occupy a small area in order to generate a clock signal locally.

Many system-on-chip or microprocessors have several modes of operation, such as active mode and sleep mode, to reduce power consumption. At the entire chip level, how quickly the clock signal is resupplied, for example when switching from one mode to another mode or when some blocks are dormant by clock gating and then into active mode, can affect the performance of the entire system. Can influence

In general, in the case of a phase locked loop (PLL), it may take up to several hundred cycles to kill and reactivate the operation, which is pointed out as a problem when the operation mode is changed. Digital clock generators are often used in microprocessors or clock / data recovery circuits to speed up operating mode transitions, but conventional digital clock generators require a 50% duty cycle for the input signal.

Due to the development of process technology, the current density increases because the number of transistors integrated and the power supply voltage are lowered. This increases the influence of switching noise by the inductor and increases the difficulty of supplying a stable power supply. According to data released by Intel, the current density of high-performance microprocessors is expected to reach nuclear reactor levels in 2005 and to reach the power density levels of rocket nozzles in 2010. It is the first element to be considered in design. To this end, the power-down mode is divided into sleep mode and sleepy mode to separately control blocks not used at the system level. In order to get back to active mode, it is important to generate the required clock quickly. Clocks made from digital circuits are limited to producing an accurate phase if the duty ratio of the input signal is not 50%.

Many semiconductor chips operate beyond the GHz range. In general PLL / DLL, it takes a long time to lock, so it takes a long time to return from the power down mode to the active mode. In order to overcome this problem, a digital clock generator may have a fast locking time, but it is difficult to produce an accurate phase according to the duty ratio of the input signal. There is an absolute need for digital circuit design techniques that overcome this.

The use of digital circuitry within high-speed microprocessors or clock / data restorers is increasing the need to generate clocks of local desired phase while occupying a small area. In particular, the use of digital clock generators to reduce the time it takes to return from active mode to active mode plays a major role in reducing the overall system power consumption, making digital clock generator design technology increasingly important. When generating a clock of a multi-phase phase, basically four phases of 0, π / 2, π, and 3π / 2 are required.

Conventional PLL / DLL clock generators are limited in their operation at low voltages and require tens to hundreds of cycles to lock. For digital clock generators, Intel announced that it operates at low voltages, but still locks for 128 cycles. In addition, the phase error of the clock generated by many digital clock generators according to the duty ratio of the input signal may vary.

SUMMARY OF THE INVENTION The first technical problem to be solved by the present invention is to provide a digital clock signal generation device that locks in one cycle, operates at a low voltage, and generates a clock signal with an accurate phase regardless of an input signal duty ratio by solving the above problems. .

The second technical problem to be achieved by the present invention is to provide a digital clock signal generation method irrespective of the duty ratio.

The present invention to achieve the first technical problem,

A clock signal delay unit for delaying the clock signal to generate clock signals having a plurality of different phases; A digitizer for detecting phases of the delayed clock signals as a digital value at a rising edge of a flip-flop; A selection signal generator configured to generate a selection signal by detecting a clock edge at which the output signal values of the digitizer transition to different digital values; And a selector which selects and outputs a predetermined signal among delay signals having different phases generated by the clock signal delay unit by using the selection signal.

According to an embodiment of the present invention, the clock signal generator may further include a clock signal generator for generating a clock signal having a predetermined frequency and an inverted clock signal in which the clock signal is inverted in phase.

According to another embodiment of the present invention, the clock signal delay unit receives the clock signal as an input, a first delay element string having delay elements connected in series, and a second delay element string having the inversion clock signal as an input and delay elements connected in series. It may be configured to output a delayed clock signal from the output terminal of each delay element.

Each of the delay elements may be a buffer including two inverters.

According to another embodiment of the present invention, the digitizer may include a plurality of inverters corresponding to each of the delay elements, and inverting an output terminal signal of each of the delay elements; A plurality of clock delay units for delaying the clock signal; And a plurality of flip-flops corresponding to each of the plurality of inverters and the plurality of clock delay units, the plurality of flip-flops having the inverter output signal as an input data signal and a signal obtained by inverting the output signal of the clock delay unit as a trigger signal. Can be.

According to a preferred embodiment of the present invention, the selection signal generator exclusively ORs two adjacent flip-flop output signals to detect a position that changes from 0 (or 1) to 1 (or 0) and selects the selection signal. It may be to generate.

In addition, the selection signal generation unit exclusively ORs two adjacent flip-flop output signals to detect 'H' at a position that changes from 0 (or 1) to 1 (or 0). It is preferable that L 'is detected.

The selection signal generator may include an inverter for inverting one of the output signals of two adjacent flip-flops; And an AND gate for inputting an output signal of the inverter and another flip-flop output signal that is not inverted among the two flip-flops.

The present invention to achieve the second technical problem,

Generating a clock signal into clock signals having a plurality of different delayed phases by using a delay element connected in series; Detecting a phase of the clock signals whose phase is delayed as a digital value having a logic value of 0 or 1 at a rising edge of a flip-flop; Generating a selection signal by detecting a case where the detected two adjacent digital values are different from each other; And selecting and outputting a predetermined clock signal among clock signals having different phases of the delay element output terminal using the selection signal. to provide.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the digital clock generator and method independent of the duty ratio of the input signal according to the present invention.

1 is a block diagram showing the configuration of a digital clock generator regardless of the input signal duty ratio according to the present invention. The clock signal delay unit 200, the digitizer 300, the selection signal generator 400 and the selection unit are shown in FIG. 500 is made. The digital clock generator according to the present invention preferably further includes a clock signal generator 100. 2 illustrates a preferred embodiment of the digital clock generator regardless of the input signal duty ratio according to the present invention. Referring to Figures 1 and 2 will be described the configuration and operation of the present invention.

The clock signal generator 100 generates a clock signal Clk having a predetermined frequency and an inverted clock signal Clk_b in which the clock signal is inverted in phase. The frequency is usually a high frequency of several GHz. The clock signal generator 100 generates Clk and Clk_b from In_Clk. The signal produced here is produced in successive multi-phase clocks ( θ1, θ2 ... θn ) in a series of inverter delay cells.

The clock signal delay unit 200 receives the clock signal Clk as an input, and a second delay element in which delay elements are connected in series, and a second delay in which delay elements are connected in series. Comprising an element sequence 240, and outputs a delayed clock signal from the output terminal of each delay element. The clock signal delay unit 200 delays the clock signal to generate clock signals having a plurality of different phases, and preferably includes delay cells. 3A and 3B show the structure and timing diagram of the delay element.

The delay element is a buffer consisting of two static inverters, and the delay line is configured as a continuous series connection of delay elements. Therefore, each delay element has the same delay time, and generates a clock having a constant phase difference. Since each delay element is composed of a static inverter, it consumes less power and eliminates high-impedence conditions, thus eliminating the abnormal operation environment. The number of delay elements is in principle not limited. In the embodiment of the present invention, the PVT is set to 20 in order to satisfy the PVT change and to detect more precisely.

The digitizer 300 detects phases of the delayed clock signals as digital values at the rising edge of the flip-flop. The digitizer 300 includes a plurality of inverters 302, 304, 306, 308, 310, a plurality of clock delays 312, 314, 316, 318, 319, and a plurality of flip-flops 320, 322, 324, 326. 328). The plurality of inverters 302, 304, 306, 308, 310 correspond to each of the delay elements, and invert an output terminal signal of each of the delay elements. The plurality of clock delay units 312, 314, 316, 318, and 319 correspond to the delay elements, respectively, and delay the clock signal. The plurality of flip flops 320, 322, 324, 326, and 328 may include the plurality of inverters 302, 304, 306, 308, 310, and the plurality of clock delays 312, 314, 316, 318, and 319. Corresponding to each), the inverter output signal is an input data signal and the signal inverting the output signal of the clock delay unit is a trigger signal.

4A and 4B show the structure and timing diagram of the digitizer 300. The operation of the digitizer is as follows. The output of the delay cell will have an arbitrary voltage value between Vdd and ground as shown in FIG. 4B when capturing in the 2π phase. The digitizer will make the output of this analog delay element a digital value of 1 or 0 on the rising edge of the D-flip-flop. Therefore, even though the output value of the delay cell has an intermediate value other than 1 or 0, the delay cell has a digital value of 0 or 1 due to the regenerative characteristics of the inverter through the inverter. In addition, each inverter connected to the output of the delay cell is added to prevent the load capacitance from changing when the D-flip-flop switches, so that each delay time of the delay cell is independent of the data, even if the data transitions to 1 or 0. The delay time tau of the delay element can be kept constant. The output value thus entered is input to the selection signal generator again. The signal from the delay element goes through the inverter and into the DFF, which acts as a phase detector. The incoming signal senses the signal on the rising edge, producing a select signal to produce the correct phase even if the duty ratio is not 50%.

The selection signal generator 400 generates a selection signal by detecting a clock edge at which the output signal values of the digitizer 300 transition to different digital values. The selection signal generator 400 generates the selection signal by detecting a position that changes from 0 (or 1) to 1 (or 0) by exclusive OR of two adjacent flip-flop output signals. The selection signal generator 400 exclusively ORs two adjacent flip-flop output signals to detect 'H' at a position that changes from 0 (or 1) to 1 (or 0), and otherwise. 'L' is detected. The selection signal generator 400 is an inverter 402, 404, 406, 408 for inverting one of the output signals of two adjacent flip-flops, and the inverted output signal of the inverter and the two flip-flops are not inverted. Logical gates 412, 414, 416, and 418 which input the other flip-flop output signal are provided.

5 illustrates the structure of the selection signal generator 400. The selection signal generator 400 exclusively-orients the signal inverted by the digitizer 300 to find and notify the position at which the clock edge transitions. The implementation of the exclusive logic sum using the inverter and the AND gate is detected only when the output value of the digitizer 300 is 0 to 1, that is, when the delay cell transitions from 1 to 0. In general, the transition detection finds a place where the clock transitions from 1 to 0, but since the input of the digitizer 300 is inverted to make the delay time of the delay element constant, the selection signal generator 400 is 0 to 1. Find the transition.

The selector 500 selects and outputs a predetermined signal among delay signals having different phases generated by the clock signal delay unit 200 using the select signal. The selector 500 is preferably implemented as a multiplexer. 6 illustrates the structure of the selector 500. The multiplexer 510 senses the selection signal sent from the selection signal generator 400 and outputs a π / 2 delayed signal to the output. In this case, the multiplexer 510 should select a signal earlier than the time in consideration of compensating for the time from the delay cell to the output. In the present invention, the compensation time is set to 3τ, and in order to select a delayed signal of π / 2, an output signal before 3τ should be sent.

7 is a flowchart illustrating a clock signal generation method irrespective of the duty ratio of the input signal according to the present invention. First, a clock signal is generated as a plurality of clock signals having a plurality of different delayed phases by using a delay element connected in series through the clock signal delay unit 200 (step 700). Then, the phase is performed through the digitizer 300. The delayed phases of the clock signals are detected as digital values having a logic value of 0 or 1 at the rising edge of the flip-flop (step 720). The two adjacent digital values detected by the selection signal generator 400 are different from each other. A value is detected and a selection signal is generated (step 740). The selection unit 500 selects and outputs a predetermined clock signal among clock signals having different phases of the delay element output terminal using the selection signal. (760 steps)

Meanwhile, the simulation results of the digital clock generator irrespective of the input signal duty ratio are as follows. First, the simulation conditions are as follows. We designed a digital clock generator independent of the input signal duty ratio and experimented with various PVT (Process, Voltage and Temperature) changes for the simulation. Table 1 shows the conditions of PVT change and the input frequency.

Characteristic Item fair CMOS 0.18㎛ Process conditions FF, SS, NN Supply voltage 2.16V, 1.8V, 1.44V Temperature 25 ℃, 65 ℃, 100 ℃ locking time 2 cycle Operating frequency 1 GHz

The following waveforms show the simulation results of a digital clock generator that is independent of the input signal duty ratio for 1.8V, normal process, and 1GHz at 65 ° C.

1. Simulation result of delay cell

FIG. 8 illustrates waveforms of a delay cell of the clock signal delay unit 200. As shown in FIG. 8, the input signal is delayed through each delay element and each delay signal has a predetermined interval. For this purpose, it is important to match the load capacitance of each delay element. In addition, it is necessary to design the connecting wire as short as possible even during the layout.

2. Simulation Results of Digitizer

9 shows simulation results of the digitizer 300. Since the delay cell sensed at the 13th phase of one cycle phase, the output of the 13th digitizer is 0 and the output of the 14th digitizer is 1. When designing such a digitizer, one thing to watch out for is the timing of the D-flip-flop that captures the signal. A more accurate signal can be obtained by capturing the output of the delay element closest to the edge.

3. Simulation result of selection signal generator

10 illustrates a simulation result of the selection signal generator 400. The selection signal generator 400 may receive an output of the digitizer 300 as an input and detect a delay cell that transitions from 1 to 0, that is, a delay cell corresponding to one period. Here, it can be seen that the selection signal generator corresponding to the 14th is 'hi'.

4. Simulation result of multiplexer

11 illustrates simulation results of the multiplexer of the selector 500. The 14th signal output from the selection signal generator 400 detects the position of the delay cell and finds a point that compensates for 3τ at a point of 3/4 period. The signal at the delay cell at that point is output. The output signal can see the π / 2 delayed signal of the input signal.

Voltage fair Temperature (℃) Latency (ps) error(%) 1.44 V SS 25 272 -2.2 1.44 V SS 65 268 -1.8 1.44 V SS 100 285 -3.5 1.44 V NN 25 239 1.1 1.44 V NN 65 269 -1.9 1.44 V NN 100 245 0.5 1.44 V FF 25 224 2.6 1.44 V FF 65 227 2.3 1.44 V FF 100 262 -1.2 1.8 V SS 25 258 -0.8 1.8 V SS 65 272 -2.2 1.8 V SS 100 265 -1.5 1.8 V NN 25 251 -0.1 1.8 V NN 65 238 1.2 1.8 V NN 100 263 -1.3 1.8 V FF 25 225 2.5 1.8 V FF 65 265 -1.5 1.8 V FF 100 243 0.7 2.16V SS 25 253 -0.3 2.16V SS 65 255 -0.5 2.16V SS 100 263 -1.3 2.16V NN 25 275 -2.5 2.16V NN 65 260 -One 2.16V NN 100 270 -2 2.16V FF 25 243 0.7 2.16V FF 65 238 1.2 2.16V FF 100 230 2

Table 2 shows the experimental results of the entire circuit according to the voltage, process and temperature changes. The voltage change was 1.44V, 1.8V, 2.16V, and the simulation was performed with the change of + 20% and -20% to 1.8V, the process standard voltage, and the process changed to Fast, Slow, Normal, and the temperature was 25 ℃ The simulation was carried out while changing to 65 ° C and 100 ° C. In this task, since the π / 2 delayed signal of the input signal is output to the output, a 1GHz signal is given as an input, so a 250ps delayed signal must be output. As you can see from the results in the table, you can see a signal almost equal to 250ps. It can be seen that the error rate is almost ± 3%.

Although the present invention has been described with reference to the embodiments shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the clock signal generation apparatus irrespective of the duty ratio of the input signal according to the present invention, it is possible to reduce the power consumption of the microprocessor operating at a high voltage at a low voltage.

In addition, since the present invention plays a big role in reducing power consumption at the system level by immediately supplying a clock when a power-down mode is switched to an active mode in a high-speed digital system, the present invention may be applied to many low-power SOC products and thus may be highly marketable.

In addition, in the case of the conventional digital clock generator, the time required for locking is 8 cycles, but according to the present invention, the locking is performed in only two cycles. In addition, in the conventional case, the area and power consumption are about 7 times and 1.5 times larger than the digital clock generator according to the present invention even though the 0.11um process is used. Therefore, the present invention is qualitatively superior to the prior art in terms of locking time, area, and power consumption. In addition, even if the input signal's duty ratio is not 50%, it can produce a precisely delayed output and operate within 3% tolerance for changes in voltage, process, and temperature, resulting in high error rates in other conventional clock generators. Supplemented.

The digital clock generator according to the present invention can be very useful for reducing the power consumption of a microprocessor operating at high speed at low voltage. First, it provides a digital delay cell to replace analog circuitry, which has limitations in operating at low voltages, and can produce an accurate phase regardless of the duty ratio of the input signal.

In addition, the clock generator according to the present invention can be directly applied to low power SOC. From an economic point of view, it is very economical because it can be widely applied to low power SOC, high speed microprocessor, and clock / data restorer.

This makes it possible to use it as a clock generator that can be used to create multiphase clocks in high-performance microprocessors, or as a fast-locking clock generator for switching from power-down mode to active mode, and to skew at the interface portion of high-performance memory. It can also be used as a clock generator such as SERDES (Ethernet, MDDI for mobile phones, SONET). The present invention can be very economical since it can be widely applied to a low power SOC, a high speed microprocessor, a clock / data recoverer, etc. from an economic point of view.

Claims (10)

A first delay element sequence having a clock signal as an input and having delayed elements connected in series, and a second delay element sequence having the inverted clock signal as an input and delayed elements connected in series, and delaying the clock signal to A clock signal delay unit for generating clock signals having a plurality of different phases at an output terminal; A plurality of inverters corresponding to each of the delay elements and inverting an output terminal signal of each of the delay elements; A plurality of clock delay units for delaying the clock signal; The phases of the delayed clock signals are flipped, corresponding to each of the plurality of inverters and the plurality of clock delays, and using a signal obtained by inverting the output signal of the clock delayer as an input data signal as a trigger signal. A plurality of flip-flops for detecting digital values at rising edges of the flop; A selection signal generation unit configured to generate a selection signal by detecting a clock edge at which the output signal values of the plurality of flip-flops transition to different digital values; And And a selection unit for selecting and outputting a predetermined signal among delay signals having different phases generated by the clock signal delay unit using the selection signal. . The method of claim 1, And a clock signal generator for generating a clock signal having a predetermined frequency and an inverted clock signal in which the clock signal is inverted in phase. delete The method of claim 1, wherein each of the delay elements A digital clock signal generator, irrespective of the duty ratio of the input signal, characterized in that the buffer consists of two inverters. delete The method of claim 1, wherein the selection signal generator Exclusive OR of two adjacent flip-flop output signals to detect a position that changes from 0 (or 1) to 1 (or 0) to generate a selection signal regardless of the duty ratio of the input signal One digital clock signal generator. The method of claim 6, wherein the selection signal generating unit Exclusive OR of two adjacent flip-flop output signals results in 'H' being detected at a position changing from 0 (or 1) to 1 (or 0), and elsewhere, 'L' is detected. A digital clock signal generator that is independent of the duty ratio of the input signal. The method of claim 1, wherein the selection signal generator An inverter for inverting one of the output signals of two adjacent flip-flops; And And an AND gate for inputting an output signal of the inverter and another flip-flop output signal which is not inverted among the two flip-flops, wherein the duty cycle of the input signal is independent of the duty ratio of the input signal. delete delete

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