JPS59176866A - Automatic wiring method of printed board - Google Patents

Automatic wiring method of printed board

Info

Publication number
JPS59176866A
JPS59176866A JP58051206A JP5120683A JPS59176866A JP S59176866 A JPS59176866 A JP S59176866A JP 58051206 A JP58051206 A JP 58051206A JP 5120683 A JP5120683 A JP 5120683A JP S59176866 A JPS59176866 A JP S59176866A
Authority
JP
Japan
Prior art keywords
line
wiring
horizontal
vertical
segments
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58051206A
Other languages
Japanese (ja)
Inventor
Kensaku Fujimori
藤森 研作
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Hokushin Electric Corp filed Critical Yokogawa Hokushin Electric Corp
Priority to JP58051206A priority Critical patent/JPS59176866A/en
Publication of JPS59176866A publication Critical patent/JPS59176866A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing

Abstract

PURPOSE:To decrease greatly the retrieving time for a multi-folded point pattern in a segment retrieving system for automatic wiring of a printed board, by storing the wiring enable information in the form of the segment end point data. CONSTITUTION:When two points A and B on a wiring mesh are connected to each other, a wiring enable segment is first detected among vertical and horizontal segments which pass through pins A and B. It is regarded that the connection is possible if the vertical (horizontal) line of A crosses the horizontal (vertical) line of B. Then the wiring data is stored in a mesh region. When those lines have no crossing, the attention is paid to the wiring enable segments l1 and l2 passing through points A and B in the same direction as shown in the figure. At the same time, the overlap area of both segments is also considered to check whether a vertical line exists within this E region. Thus nine regions are obtained as connection enable regions. The wiring enable segments thus obtained are stored in horizontal and vertical data buffers respectively, and at the same time a pattern is stored in the mesh region.

Description

【発明の詳細な説明】 本発明はプリント板の自動配線方法に関し、更に詳しく
は線分探索法を用いて多折点パターンの探索時間を大幅
に低減したプリント板の自動配線方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an automatic wiring method for a printed circuit board, and more particularly to an automatic wiring method for a printed circuit board that uses a line segment search method to significantly reduce the search time for a multi-fold pattern.

プリント板の自動配線をコンピュータプログラムで行う
とき、線分探索法が広く使われている。
The line segment search method is widely used when automatically wiring printed circuit boards using a computer program.

線分操業法とは、成る結線すべき2点が与えられたとき
これらの点を通過する水平方向及び垂直方向の探索線を
延ばしそれらの線が2点を結合するかたちで交差した場
合、結線が成功したものとみなしそれらの線を配線パタ
ーンとするものである。
The line segment operation method means that when two points to be connected are given, horizontal and vertical search lines are drawn that pass through these points, and if these lines intersect in a way that connects the two points, the line is connected. These lines are considered to be successful and are used as a wiring pattern.

この方法によれば、特に配線層が2層の場合、一層で主
に水平方向のパターンを他の層で主に垂直方向のパター
ンをひくようにすることKより、かなりの密度の配線が
可能となる。しかしながら、従来方法によれば、パター
ンが第1図に示すように単純な場合には高速で結線する
ことができるが、第2図に示すような結線を行うには時
間がかかつてしまうことが知られている。第1図、第2
図において、■とくWは結線すべき2点を示し、縦方向
実線は表パターンを、横方向破線は裏パターンを、X印
は表パターンと裏パターンをつなぐスルーホールを、斜
線領域は配線禁止領域を(この項以下同じ)それぞれ示
している。
According to this method, especially when there are two wiring layers, it is possible to achieve much higher wiring density than by drawing mainly horizontal patterns in one layer and mainly vertical patterns in other layers. becomes. However, according to the conventional method, when the pattern is simple as shown in Figure 1, it is possible to connect at high speed, but it takes time to connect as shown in Figure 2. Are known. Figures 1 and 2
In the figure, ■ and W indicate two points to be connected, the vertical solid line is the front pattern, the horizontal broken line is the back pattern, the X mark is the through hole that connects the front pattern and the back pattern, and the diagonally shaded area is where wiring is prohibited. The areas are shown (the same applies hereafter).

即ち、折れ曲がり点を1自由度と考え、A点からBAK
届く経路を縦横の線で求めるとき、各折れ曲がり点での
可能径路求めの試行回数を積算していくと膨大な数とな
ってくる。長時間の探索を避けるため折れ曲がシ点の数
を小数に(例えば4点まで)制限する方法も考えられて
いるが、そのために径路が可能であるKも拘らず途中で
あきらめなければならないという不都合も生じていた。
In other words, considering the bending point as one degree of freedom, from point A to BAK
When finding a route that can be reached using vertical and horizontal lines, if you add up the number of attempts to find a possible route at each turning point, the number becomes enormous. In order to avoid a long search, a method has been considered to limit the number of bend points to a decimal number (for example, up to 4 points), but because of this, the route must be given up midway even though the route K is possible. This also caused some inconvenience.

本発明はこのような点に鑑みてなされたものであって、
線分探索法において、自動配線用メツシュデータの探索
を最小限に押さえるため、可能配線情報を線分の端点デ
ータとして記憶するよってして多桁点パターンの探索時
間を大幅に低減したプリント板の自動配線方法を実現し
たものである。
The present invention has been made in view of these points, and
In the line segment search method, in order to minimize the search for mesh data for automatic wiring, possible wiring information is stored as line segment end point data, thereby greatly reducing the search time for multi-digit point patterns. This is a wiring method realized.

以下、図面を参照して本発明の詳細な説明する。Hereinafter, the present invention will be described in detail with reference to the drawings.

第3図は、本発明を実施するためのシステムの構成を示
す図である。図において、1はその内部に配線プログラ
ムが格納されたCPU、2は主メモリで配線メツシュデ
ータ領域21.水平方向線分データが1ペ一ジ分格納さ
れる水平線分データバッファ22及び垂直方向線分デー
タが1ペ一ジ分格納される垂直線分データバッファ23
よυ構成さtlている。2ペ一ジ分以上の水平線分デー
タ及び垂直線分データは、外部の補助記憶装置3に格納
される。第4図は、配線メツシュデータ領域21に格納
されるデータの一例を示す図である。このように構成さ
れた装置において、CPU1で実施される自動配線プロ
グラムがメモリ2内の配線メツシュデータと水平、垂直
線分データを用いて自動配線を行う。
FIG. 3 is a diagram showing the configuration of a system for implementing the present invention. In the figure, 1 is a CPU in which a wiring program is stored, 2 is a main memory with a wiring mesh data area 21. A horizontal line segment data buffer 22 stores one page of horizontal line segment data, and a vertical line data buffer 23 stores one page of vertical line segment data.
It's made up of a lot of things. Horizontal line segment data and vertical line segment data for two or more pages are stored in the external auxiliary storage device 3. FIG. 4 is a diagram showing an example of data stored in the wiring mesh data area 21. In the apparatus configured as described above, an automatic wiring program executed by the CPU 1 performs automatic wiring using the wiring mesh data and the horizontal and vertical line segment data in the memory 2.

配線メツシュデータは、プリン、ト基板の2層をある配
線グリッド値(例えば1・27皿)間隔で網目状に分割
したときの最小単位の領域の状態を表わすもので、配線
メツシュ領域21は、このようなメツシュデータの格納
される領域を示す。メツシュデータの状態としては、■
端子、■配線、■スルーホール、″■配線禁止、■スル
ーホール禁止、■空白(配線可能)等がある。実際には
、第5図の表に示すようにメモリのワード内ビットにス
テータスを意味づけるようにしている。データバッファ
22.23内に格納される配線可能線分データとは、配
線メツシュデータの中で、水平又は垂直方向に配線可能
なステータスをもつ連続したメツシュをつなげたときに
求められる線の集まりをいう。線は、両端の訂座標で定
義される。
The wiring mesh data represents the state of the minimum unit area when the two layers of the printed circuit board are divided into meshes at intervals of a certain wiring grid value (for example, 1.27 plates), and the wiring mesh area 21 is This shows the area where mesh data like this is stored. The state of the mesh data is ■
There are terminals, ■Wiring, ■Through holes, ``■Wiring prohibited, ■Through holes prohibited, ■Blank (wireable), etc.In reality, the status is written to the bits in the memory word as shown in the table in Figure 5. The routable line segment data stored in the data buffer 22 and 23 refers to the data when consecutive meshes with a routable status in the horizontal or vertical direction are connected in the wiring mesh data. A collection of lines to be found.A line is defined by the corrected coordinates of both ends.

データバッファ22.23は、線が多く存在した場合、
メモリ内に入シきれないことを想定して、磁気ディスク
などの補助記憶装置3に全てのデータを貯え、その一部
のみ(1ペ一ジ分)を記憶しておくものである。1ペー
ジは、第6図の表に示すように128語長でib線分レ
ベル別に設けられる。
If there are many lines in the data buffers 22 and 23,
Assuming that the data cannot be stored in the memory, all the data is stored in the auxiliary storage device 3 such as a magnetic disk, and only a part of the data (one page) is stored. As shown in the table of FIG. 6, one page has a length of 128 words and is provided for each ib line segment level.

線分レベルは、尋粋##始点端子■から終点端子■をみ
たとき、■に近づく方向の水平、垂直配線路に正の通し
番号を、遠ざかる方向の水平、垂直配線路に負の通し番
号を付ける。同一レベル上の線分が例えこま切れ罠なっ
ていても、同一ページに格納される。ある時点であるレ
ベルの配線可能線分を求めるべく、メツシュを調べた結
果として、そのレベルの線分がベージに格納される。同
一レベルの線分が、再度メツシュ領域21がら調べられ
ることはない。
For the line segment level, when looking from the starting point terminal ■ to the end point terminal ■, assign positive serial numbers to the horizontal and vertical wiring paths that approach ■, and negative serial numbers to the horizontal and vertical wiring paths that move away from ■. . Even if line segments on the same level are segmented traps, they are stored on the same page. At a certain point in time, as a result of examining a mesh to find a routeable line segment at a certain level, the line segment at that level is stored in the page. Line segments at the same level are not examined again in the mesh area 21.

第6図は、水平、垂直データバッファ21.23及び補
助記憶装置3の内部構成を示す図である。主メモリ内に
水平方向線分データバッファ22と垂直方向線分データ
バッファ23が存在し、補助記憶装置は方向別線分デー
タが格納される領域と、線レベル及び線分データアドレ
スが格納されるインデックス領域とで構成される。線分
データアドレスが−1のときは「線存在せず」、0のと
きは「まだ求められていない」の意味をもつ。線分座標
は水平のときX座標のみ、垂直のときY座標のみとなる
。層区分はA層(部品面)とB層(ハンダ付面)とが区
別され、層により水平、垂直方向かを知ることができる
FIG. 6 is a diagram showing the internal configuration of the horizontal and vertical data buffers 21 and 23 and the auxiliary storage device 3. A horizontal line segment data buffer 22 and a vertical line segment data buffer 23 exist in the main memory, and the auxiliary storage device stores an area where line segment data for each direction is stored, and line levels and line segment data addresses. It consists of an index area. When the line segment data address is -1, it means "the line does not exist", and when it is 0, it means "the line has not been found yet". The line segment coordinates are only the X coordinate when it is horizontal, and only the Y coordinate when it is vertical. The layer division is divided into layer A (component side) and layer B (soldering side), and it is possible to know whether the layer is horizontal or vertical depending on the layer.

今、2つの配線メツシュ上に2点A、B(以下ビンとい
う)を定めこれら2点間を結線するものとする。先ず、
第7図に示すようにピンA、Bを通る垂直方向線分(実
線)と水平方向線分(破線)のうちの配線可能線分を探
し出す。最初は、水平、垂直方向線分データバッファ2
2.23はクリアされていてデータが無いのでメツシュ
データ領域21を調べて求める。このよう処して求めた
水平方向及び垂直方向の線分データは、それぞれ線分デ
ータバッファ22.23に格納する。このようにして求
めた配線をプライマリ配線とよぶ。次に、Aの垂直線(
水平線)とBの水平線(垂直線)が交差すれば結線可能
とみなし、それらの線を第8図に示すように配線する。
Now, assume that two points A and B (hereinafter referred to as bins) are defined on two wiring meshes and a wire is connected between these two points. First of all,
As shown in FIG. 7, out of the vertical line segment (solid line) and the horizontal line segment (broken line) passing through pins A and B, a line segment that can be wired is found. Initially, horizontal and vertical line segment data buffer 2
Since 2.23 is cleared and there is no data, the mesh data area 21 is examined to find it. The horizontal and vertical line segment data obtained in this manner are stored in line segment data buffers 22 and 23, respectively. The wiring obtained in this way is called the primary wiring. Next, the vertical line of A (
If the horizontal line (horizontal line) and the horizontal line (vertical line) of B intersect, it is considered that connection is possible, and these lines are wired as shown in FIG.

配線された配線データはメツシュ領域21VC格納され
る。交差しなかった場合、CPU 1は2個以上のスル
ーホールを必要とするパターンであると判断する。
The laid wiring data is stored in the mesh area 21VC. If they do not intersect, the CPU 1 determines that the pattern requires two or more through holes.

第9図は、2点A、Bを通る水平方向及び垂直方向の何
れの線も交差しない例を示す図である。この例の場合、
2点A、 Bを通過する同一方向の配線可能線分(ここ
では水平線)t、とt2vr、着目する。
FIG. 9 is a diagram showing an example in which neither horizontal nor vertical lines passing through two points A and B intersect. For this example,
Pay attention to the routable line segments (horizontal lines in this case) t and t2vr in the same direction that pass through the two points A and B.

tlと12については、図に示すようKB領領域重なり
部である。次に1この重なり領域内で垂直線が存在する
かどうかをチェックする。垂直配線領域■、■・・・0
・・・で、連結可能領域を探すと、図に示す領域では■
領域で連結可能であることがわかる。
As for tl and 12, as shown in the figure, they are KB area overlapped parts. Next, one checks whether a vertical line exists within this overlap region. Vertical wiring area ■, ■...0
..., and when searching for a connectable area, the area shown in the figure is ■
It can be seen that it is possible to connect in the area.

この垂線は、2個のスルーホールによってそれぞれ水平
線t1.匂と接続される。このようにして得た配線可A
は、それぞれ水平、垂直線分データ:バッファ22.2
3 K格納されると共に1メツシュ領域21−にはパタ
ーンが格納される。以後の探索で、もし同じところの線
分データが必要となった場合、再度メツシュ領域のパタ
ーン状態を1メツシヱずりを取出すことができるので探
索時間が大幅に削減される。
This perpendicular line is connected to the horizontal line t1. by two through holes, respectively. Connected to smell. Wiring possible A obtained in this way
are horizontal and vertical line segment data: buffer 22.2
3K are stored, and a pattern is stored in the 1 mesh area 21-. In subsequent searches, if line segment data at the same location is required, the pattern state of the mesh area can be extracted again by one mesh, thereby greatly reducing the search time.

例えば、第10図に示すようなパターンしか求められな
いような探索においても、水平方向■〜■、垂直方向■
〜[相]の水平、垂直配線領域の線分を1度求め各線分
データバッファ22.23 K格納しておくことにより
、それ以後は線同志の重なシ状態と重なっている範囲内
の連結線分の存在のチェックを繰シ返すのみで複雑なパ
ターンの配線が1メツシユずつチェックしていかなくて
も求めることが可能となシ高速の探索が行われるととK
なる。
For example, even in a search where only the pattern shown in Fig. 10 can be found, horizontal direction ■~■ and vertical direction ■
By calculating the line segments in the horizontal and vertical wiring area of ~ [phase] once and storing each line segment in the data buffer 22.23K, from then on, connections within the overlapping state of the lines can be performed. It is possible to perform a high-speed search by simply repeatedly checking the existence of line segments to find complex patterns of wiring without having to check each mesh one by one.
Become.

以上詳細に説明したように1本発明によれば自動配線用
メツシュデータの探索を最/1%限に押さえるため、可
能配線情報を線分の端点データとじて記憶するようにし
て多折点パターンの探索時間を大幅に低減したプリント
板の自動配線方法を実現することができる。
As explained in detail above, according to the present invention, in order to suppress the search for mesh data for automatic wiring to a minimum of 1%, possible wiring information is stored together with line segment end point data, so that multi-fold pattern It is possible to realize an automatic wiring method for printed circuit boards that significantly reduces search time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図、第2図はパターンの結線方法を示す図、第6図
は本発明を実施するだめのシステムの構成を示す図、第
4図はメツシュ領域に記憶されているパターン例を示す
図、第5図はメツシュデータの構成を示す表、第6図は
データバッフ1と補助記憶装置の構成を示す図、第7図
は配線可能線分を示す図、第8図〜第10図は配線方法
を示す図である。 1・・・CPU、2・・・主メモリ、3・・・補助記憶
装置、21・・・イッシ瓢領域、22・・・水平方向線
分データバッフ1.23・・・垂直方向線分データバッ
ファ。 第6図 く−主メモリ→ <−一一−−−一一一一−−雁助記視
円□第7図
1 and 2 are diagrams showing a pattern connection method, FIG. 6 is a diagram showing the configuration of a system for implementing the present invention, and FIG. 4 is a diagram showing an example of patterns stored in the mesh area. , Figure 5 is a table showing the configuration of mesh data, Figure 6 is a diagram showing the configuration of data buffer 1 and auxiliary storage device, Figure 7 is a diagram showing line segments that can be wired, and Figures 8 to 10 are wiring diagrams. FIG. 2 is a diagram illustrating the method. 1...CPU, 2...Main memory, 3...Auxiliary storage device, 21...Ishigourd area, 22...Horizontal line segment data buffer 1.23...Vertical line segment data buffer. Fig. 6 - Main memory → <-11--11-1-- Gansuke reference circle □ Fig. 7

Claims (1)

【特許請求の範囲】 以下の工程を有するプリント板の自動配線方法(1) 
 プリント板の配線データを格納するためのメモリを、
プリント板を配線グリッドで網目状に分割したメツシュ
領域と、水平方向及び垂直方向の配線可能線分を格納す
る線分データ領域に割りふる。 (2)配線すべき2点間に着目しこれら2点間を通過す
る水平及び垂直方向の配線可能線分を求める。 (3)  (2)で求めた配線可能線分のうち、一方の
点の水平線(垂直線)と他方の点の垂直線(水平線)が
交差する場合には結線可能とみなしそれらの線を配線し
、配線データはメツシュ領域に格納する。 (41(2)で求めた配線可能線分のうち、一方の点の
水平線(垂直線)と他方の点の垂直線(水平線)が交差
しなかった場合、2個以上のスルーホールを必要とする
パターンであると認識し、結線すべき2点を通過する同
一方向の配線可能線分同志の重なシをチェックしそれら
の線分間の連結線分探しを行なう。そこで求められた全
ての配線可能線分を方向及びレベル別に線分データ領域
の中に格納しインデックスに線分の有無を 。 登録する。 (5)以後の線分の重なりチェックと連結線分の存在を
チェックする場合には、既に求められている線分が存在
するかどうかは線分インデックスを参照する。
[Claims] Automatic wiring method for a printed board (1) having the following steps:
Memory for storing printed board wiring data,
The printed board is divided into a mesh area by a wiring grid, and a line segment data area is allocated to store line segments that can be wired in the horizontal and vertical directions. (2) Focusing on the two points to be wired, find the horizontal and vertical line segments that pass between these two points. (3) Among the routeable line segments obtained in (2), if the horizontal line (vertical line) at one point intersects the vertical line (horizontal line) at the other point, it is assumed that the line can be connected and those lines are routed. However, the wiring data is stored in the mesh area. (If the horizontal line (vertical line) at one point and the vertical line (horizontal line) at the other point do not intersect among the routeable line segments determined in 41 (2), two or more through holes are required. It recognizes that the pattern is a pattern that connects two points, checks for overlapping routable line segments in the same direction that pass through the two points to be connected, and searches for connecting line segments between those line segments. Store possible line segments in the line segment data area by direction and level, and register the presence or absence of line segments in the index. (5) When checking the overlap of line segments and the existence of connected line segments in the future , the line segment index is referenced to determine whether a line segment that has already been found exists.
JP58051206A 1983-03-25 1983-03-25 Automatic wiring method of printed board Pending JPS59176866A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58051206A JPS59176866A (en) 1983-03-25 1983-03-25 Automatic wiring method of printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58051206A JPS59176866A (en) 1983-03-25 1983-03-25 Automatic wiring method of printed board

Publications (1)

Publication Number Publication Date
JPS59176866A true JPS59176866A (en) 1984-10-06

Family

ID=12880425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58051206A Pending JPS59176866A (en) 1983-03-25 1983-03-25 Automatic wiring method of printed board

Country Status (1)

Country Link
JP (1) JPS59176866A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04353978A (en) * 1991-05-30 1992-12-08 Sharp Corp Automatic correction method for circuit drawing

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139868A (en) * 1981-02-25 1982-08-30 Fujitsu Ltd Circuit diagram wiring system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57139868A (en) * 1981-02-25 1982-08-30 Fujitsu Ltd Circuit diagram wiring system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04353978A (en) * 1991-05-30 1992-12-08 Sharp Corp Automatic correction method for circuit drawing

Similar Documents

Publication Publication Date Title
JPS63225869A (en) Wiring path search system
JPH0786881B2 (en) Wiring route determination method
JPS63233448A (en) Memory area allotting method and apparatus
EP0612023B1 (en) Net diagram routing method
JPS63146165A (en) Derivation of route for mutual connection between elements for connection medium
Yu et al. Fast and Incremental Routability Check of a Topological Routing Using a Cut-Based Encoding
JPS59176866A (en) Automatic wiring method of printed board
US6496968B1 (en) Hierarchical wiring method for a semiconductor integrated circuit
JPH01189936A (en) Automatic wiring method for integrated circuit
EP0302547B1 (en) Device for executing a search in a topological representation of a geographical interconnection network.
JP2523702B2 (en) Automatic wiring method for semiconductor integrated circuits
JP3229235B2 (en) Wiring shaping method and apparatus, prohibited area radius determining method and apparatus
US6545288B1 (en) Gridless router using maze and line probe techniques
JPS59189471A (en) Wiring route searching system
JP2001350813A (en) Automatic wiring method and device therefor
JP2751199B2 (en) Wiring route search method and device
JP3235636B2 (en) Train schedule creation support system
JP2722694B2 (en) Automatic wiring system
JP3014157B2 (en) Automatic wiring method
JPS62120042A (en) Automatic wiring system
JPS59188772A (en) Route retrieval and processing system
JPS61134878A (en) Wiring control processing system
JPS6123388A (en) Wiring route searching device
JPH0652532B2 (en) Circuit board wiring route search method by CAD
JPS62209890A (en) Automatic wiring