JPS59175170A - Hetero junction solar battery and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to reduce the manufacturing cost by forming a P-N junction by depositing an amorphous semiconductor on a crystalline semiconductor in a low temperature process. CONSTITUTION:An electrode 1 is formed by evaporating aluminum on the back surface of a P type polycrystalline Si wafer 2, an N type thin film semiconductor 3 and a clear conductive film 4 made of the compound of Ind oxide with Sn oxide are formed on the wafer 2 by glow discharge decomposition, and then a comb electrode 5 is formed on said film 4. Said wafer 2 and said semiconductor 3 are put in hetero junction and thus constitute the unit cell of the solar battery. Since the P-N junction can be formed in the low temperature process such as a glow discharge decomposition method by changing the N type semiconductor 3 into a thin film microcrystalline Si, the reduction of the manufacturing cost can be contrived.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to single crystal or polycrystalline semiconductors (hereinafter referred to as silicon).
The present invention relates to a veterojunction solar cell in which a PN junction is formed by depositing an amorphous or microcrystalline semiconductor (hereinafter referred to as an amorphous semiconductor) on a crystalline semiconductor, and a method for manufacturing the same.

Prior Art Conventionally, in solar cells using crystalline semiconductors, P
N junctions are generally formed by thermal diffusion or ion implantation. The former thermal diffusion method is a method in which a crystalline semiconductor device is placed in an atmosphere containing impurities to be added, and the impurities are diffused into the semiconductor by maintaining the device at a high temperature of about 1000°C. The latter ion implantation method is a method of ionizing the impurity to be added, accelerating the ions with a high electric field, and implanting them into a crystalline semiconductor. This ion implantation method is
Because the crystal structure is greatly disturbed when ions are implanted,
After ion implantation, annealing (
annealing). As mentioned above, all of these PN junction formation methods include high-temperature processes,
Advanced equipment and advanced manufacturing management are required, which increases the manufacturing cost of solar cells, and during high-temperature processing, unnecessary impurities get mixed into the semiconductor from the surrounding area, reducing the efficiency of solar cells. This was a contributing factor.

3- Purpose of the invention The present invention forms a PN junction by depositing an amorphous semiconductor on a crystalline semiconductor at a low temperature process, for example, at 200 to 300°C in the case of glow discharge decomposition method (GD method). , we aim to reduce the manufacturing cost of solar cells in terms of manufacturing technology, manufacturing equipment, etc., and create solar cells that can achieve higher efficiency by creating a tandem structure that takes advantage of the characteristics of roughly amorphous materials. The purpose of this invention is to provide a manufacturing method for the same.

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to illustrated embodiments.

FIG. 1(A) is a block diagram of a first embodiment of the present invention, showing a solar cell in which a wafer is used as the crystalline semiconductor. In the figure, 2 is a wafer (thin plate) of P-type crystalline semiconductor, for example, P-type child-crystalline silicon, 1 is an electrode made by vapor-depositing aluminum on the back side of the P-type child-crystalline silicon wafer, and 3 is P-type child-crystalline silicon. An N-type thin film semiconductor, for example, a thin film of N-type microcrystalline silicon, is deposited on a wafer 2 by the glow discharge decomposition method (GD method). Compounds with tin (
ITO> transparent conductive film, 5 was formed on the transparent conductive film (
It is a ribbon-shaped electrode.

The above N-type microcrystalline silicon has optical properties similar to those of an amorphous semiconductor, and electrical properties similar to those of a crystalline semiconductor.

The formation temperature of this N-type microcrystalline silicon is 200 to 300°C.
The conventional wet temperature for forming a PN junction in a crystalline semiconductor is 000
℃, and the processing time to form a PN junction is only a few minutes, which is shorter than the time required to form a PN junction in conventional crystalline semiconductors, reducing the manufacturing cost of solar cells. can be lowered.

In this first embodiment, a wafer of P-type subcrystalline silicon and N-type microcrystalline silicon are heterojunction-IJed to constitute a unit cell of one solar cell, and a wafer of P-type subcrystalline silicon is Since the N-type semiconductor deposited on the solar cell is a thin film of microcrystalline silicon, a PN junction can be formed using a low-temperature process such as glow discharge decomposition, thereby reducing the manufacturing cost of solar cells. be able to. The above-mentioned glow discharge decomposition method is a method of growing a '7iIJ film at a low temperature by bringing the constituent atoms of the thin film to be grown into a plasma state and decomposing them into chemically active ions and radicals.

FIG. 1(B) is an energy band diagram of the solar cell shown in FIG. Energy gap E (IC
This is larger than the approximately 1.1 [eV] of
The PN junction is a heterojunction HJ, and the window effect, that is, the optical loss on the short wavelength side of sunlight can be reduced. In the same figure, EC is the lower limit level of the conduction band, ET
is the Fermi level, and EV is the unit of the upper limit of the valence band.

FIG. 2 is a diagram showing the measured values of the IV characteristics of the solar cell shown in FIG.
The output voltage vout [V] of the solar cell in A) is shown, and the vertical axis shows the output current 1 out [m A/cJ] of the solar cell. The conversion efficiency of the solar cell shown in Figure 1 (A), determined from the IV characteristics in the same figure, is approximately 11%. Accordingly, it is possible to obtain efficiency comparable to that of a solar cell in which a PN junction is formed. Therefore, according to the heterojunction solar cell and the manufacturing method thereof of the present invention, it is possible to maintain substantially the same efficiency as a solar cell manufactured using a conventional high-temperature process, while reducing the manufacturing cost of the solar cell. .

In the first embodiment shown in FIG. 1(A), the crystalline semiconductor is P type and the amorphous semiconductor is N type, but conversely, the crystalline semiconductor is N type and the amorphous semiconductor is P type.
Furthermore, the crystalline semiconductor with reference numeral 2 may be single crystal or polycrystalline Si, GaAs, Qe, etc., and the amorphous semiconductor with reference numeral 3 may be hydrogenated or fluorinated. microcrystalline or amorphous silicon carbide, silicon nitride, silicon gel7
- May be rumanium, etc.

In addition to the GD method mentioned above, methods for forming amorphous semiconductors include: (1) heating a substance in a vacuum, evaporating it, and depositing the evaporated substance on the surface of the substance to form a film; Vacuum evaporation method, ■ Sputtering method, in which the deposited material is released by the collision of gas ions with glow discharge to form a film on the surface of another material, ■ Vacuum evaporation method, in which the evaporated material is ionized to form a film on the surface of another material. Ion blating method, which forms a film by depositing it on the surface. ■ A mixed reaction gas containing the elements for the film to be formed is fed onto a substrate that has been heated in advance in a reaction chamber, and the substrate is heated while shining light. A low-temperature process such as a photo-CVD method that forms a film using the above thermochemical reaction can be used.

FIG. 3 is a block diagram of a second embodiment of the present invention, in which a thin film is used as the crystalline semiconductor. In the figure, 6 is a thin plate-like substrate made of an inorganic solid such as metal, glass, or ceramic 8 = ivy, or a film-like substrate made of an organic solid such as polyimide. 1' is an ohmic electrode formed on the substrate 6, and 2' is an ohmic electrode formed on the ohmic electrode by vapor phase epitaxy (CVD), thermal decomposition method using organometallic material (MOCVD), or molecular beam epitaxy (MBE).
), a crystalline semiconductor thin film made to a thickness of 1ftlFi using a sputtering method, an ion blating method, or the like. 3 is a thin film of N-type amorphous or N-type microcrystalline silicon deposited on this thin film 2' by the same low-temperature process as in FIG. 1(A), and 4' and 5 are the same as in FIG. 1(A). These are the same transparent conductive film and comb-shaped electrodes as in the example.

In the above embodiment, if a conductive material is used as the substrate 6 and it also serves as an electrode, there is no particular need to form the ohmic electrode 1' separately. In addition, in this second embodiment, by making the crystalline semiconductor thinner, manufacturing costs are further reduced than in the first embodiment, and by using technologies such as CVD and MOCVD, It can be converted into an area.

FIG. 4(A) is a block diagram of a third embodiment of the present invention, in which a crystalline semiconductor 2 and an amorphous semiconductor 3 similar to FIG. 1(A) are formed into a PN junction in which a heterojunction HJ is formed. In the unit cell C1 of Ecoal, an energy gap consisting of
Further, the unit cell C2, which is composed of a PN junction in which the crystalline semiconductor 8 and the amorphous semiconductor 9 are formed into a heterojunction HJ and has an energy gap of EgC2 (EgC2>E(+01)), is subjected to the same power distribution control as the crystalline semiconductor 8. This is a heterojunction solar cell with a tandem structure in which layers are stacked with an amorphous semiconductor 7 in between.

In the figure, numerals 1 to 5 are the same as those in FIG. 1(A), and 7 is a jf
8 is a crystalline P-type thin film semiconductor further deposited on the semiconductor 7, and 9 is an amorphous N-type thin film semiconductor further deposited on the semiconductor 8. Thus, the crystalline semiconductor 8 and the amorphous semiconductor 9 form a unit cell C2 in which a heterojunction HJ is formed.

In order to form a tandem structure, it is necessary to make an ohmic junction at the interface between the unit cells C1 and C2, so by providing the amorphous semiconductor 7 between the unit cells C1 and C2 as in the present invention, , the amorphous semiconductors 3 and 7 form a good ohmic junction OJ.

FIG. 4(B) shows an energy band diagram of the solar cell of FIG. 4(A) when irradiated with light. Unit cell C1 by light irradiation
When the electrons e generated in and the holes generated in the unit layer C2 recombine via the localized level ES in the forbidden band near the junction, a recombination current flows and a good ohmic junction is formed. It has become. In other words, in the third embodiment of the present invention, by using an amorphous semiconductor in the junction part, the property of the amorphous semiconductor, which is generally considered to have a drawback of having many localized levels in the forbidden band, can be taken advantage of. The feature is that an ohmic junction is easily obtained by a PN junction of an amorphous semiconductor.

In this third embodiment, light on the shorter wavelength 11- side of sunlight is absorbed by the upper unit cell C2 with a larger energy gap, and furthermore, light on the longer wavelength side that has passed through it is absorbed by the lower energy gap. Since the energy can be absorbed by the unit cell C1 having a smaller gap, it is possible to reduce the manufacturing cost of the solar cells of the first and second embodiments and to obtain a highly efficient solar cell.

FIG. 5 is a configuration diagram of a fourth embodiment of the present invention.
Then, by the GD method, two units of amorphous semiconductor are added to the unit cell C, which is made up of a PN junction in which a crystalline semiconductor and an amorphous semiconductor are heterojunction HJ shown in FIG. 1(A) and has an energy gap of EgC. This is a heterojunction solar cell with a tandem structure in which PIN junction unit cells A1 and A2 are stacked.

// In the same figure, numerals 1.2.3 to 6 are the same as in FIG. 3, and between the amorphous semiconductor 3 and the transparent conductive film 4 in FIG. A unit cell A1 consisting of amorphous semiconductors 11 to 13 has an energy gap of E Gal (E (Ial12- >Egc)), and a unit cell A1 consisting of amorphous semiconductors 11 to 13 has an energy gap of EgC2 (Egc2).
>Egal) is inserted. Semiconductors 3 and 11 forming the junction between unit cell C and unit cell A1, and semiconductors 13 and 14 forming the junction between unit cell A1 and unit cell A2 are the same as in the third embodiment. For these reasons, it is a good ohmic junction OJ.

In this fourth embodiment, light on the shorter wavelength side of sunlight is absorbed by unit cells A2 and A1 of the upper PIN junction, and light on the longer wavelength side is absorbed by unit cells A2 and A1 of the lower heterojunction.
Since it can be absorbed by the N-junction unit cell C, in addition to reducing the manufacturing cost l~ of the solar cell of the first or second embodiment, a highly efficient solar cell can be obtained.

FIG. 6 is a block diagram of a fifth embodiment of the present invention, in which a GD layer is further added on the amorphous semiconductor 9 shown in FIG.
As shown in Figure 5, 2 units of amorphous PT
This is a heterojunction solar cell with a tandem structure in which N-junction unit cells A1 and A2 are stacked. In this figure, numerals 1 to 5 and 7 to 9 are the same as in FIG. 4, and numerals 11 to 16 are the same as in FIG. 5.

In this fifth embodiment, from light on the short wavelength side of sunlight to light on the long wavelength side, the unit cell A2 of the PTN junction with an energy gap of Ega2, Eqa
Unit cell A 1 of PIN junction where l (Egc2 > Eoal ), Egc2 (Eoal > Eg
c2), the unit of the PN junction is LeC2 and EOCl
(Egc2>E (Icl)) can be absorbed by the PN junction unit cell C1, so in addition to reducing the manufacturing cost of the solar cell of the first or second embodiment, a highly efficient solar cell can be obtained. be able to.

Effects of the Invention As described above, according to the solar cell of the present invention, an amorphous or microcrystalline amorphous semiconductor is deposited on a single crystal or polycrystalline semiconductor using the glow discharge decomposition method (GD).
Since the PN junction is formed by deposition using a low-temperature process such as (method), the temperature for forming the PN junction is extremely low, and the processing time for forming the junction is shortened, which simplifies the manufacturing equipment. , it is possible to reduce the manufacturing cost of solar cells by shortening the manufacturing time, etc., and maintain the same efficiency as solar cells manufactured using conventional high-temperature processes. By making use of the tandem structure, it is possible to achieve even higher efficiency, which has great industrial benefits.

[Brief explanation of drawings]

Figures 1 (, A) and (B) are the block diagram and energy band diagram of the first embodiment of the solar cell of the present invention, respectively, and Figure 2 is the IV characteristic of the solar cell shown in Figure 1. (The horizontal axis is the output voltage VOut [V] of the solar cell, and the vertical axis is the output current 1out [mA/cn?] of the solar cell). FIG. FIGS. 4(A) and 4(B) are respectively a block diagram and an energy band 15 diagram of a third embodiment of the present invention. FIGS. 5 and 6 are respectively a block diagram of a third embodiment of the present invention FIG. 4 is a configuration diagram of fourth and fifth embodiments of the battery. 1.1'...electrode 2.2', 8...crystalline semiconductor 3.7.11 to 16...amorphous semiconductor 4...
...Transparent conductive film 5...Comb-shaped electrodes c, cl, C2...PN junction unit cells A, A1. A
2...PIN junction unit cells Ega, Egal, E
gc2... Energy gap of amorphous semiconductor Egc, E(IcI, E(IC2... Energy gap of crystalline semiconductor HJ... Betero junction OJ between crystalline semiconductor and amorphous semiconductor... - Agent for ohmic junction between unit cells Patent attorney Hiroshi Nakai 16- Oral engraving (no change in content) Figure 2 Iou also [mA/Cm2] 0.0 02 0.4 0.6 0.
8 1.0 L2Vout (V) Eye, T OJ Eye, ■ OJ OJ OJ Procedural Amendment (Spontaneous) April 15, 1982 1. Indication of the case 1982 Patent Application No. 49318 2. Name of the invention Hetero Junction solar cell and its manufacturing method 3. Relationship with the amended person case Patent application: 3-17-4 Minamihanayashiki, Yonishi City, Hyogo Prefecture Keihiro Hamayo (and 2 others) 4. Agent address: 532 2-1-1 Tayo, Yodoyo-ku, Osaka City
No. 1 No. 5, Date of amendment order Voluntary issue 6, Subject of amendment ``Drawings'' 7, Contents of amendment As shown in the attached sheet, engraving of ``Drawings'' (1 Kyu 3 Eri) (no change in content)

Claims (1)

[Scope of Claims] 1. A heterojunction solar cell comprising a unit cell in which a single crystalline or polycrystalline semiconductor and an amorphous or microcrystalline amorphous semiconductor are PN-junctioned. 2. The heterojunction solar cell according to claim 1, wherein the crystalline semiconductor is a wafer. 3. The heterojunction solar cell according to claim 1, wherein the crystalline semiconductor is a thin film semiconductor. 4 A plurality of unit cells in which a single crystalline or polycrystalline crystalline semiconductor and an amorphous or microcrystalline amorphous semiconductor are PN-junctioned are connected in series via an amorphous semiconductor whose valence is controlled in the same way as the crystalline semiconductor. Stacked heterojunction solar cells. 5 Among the crystalline semiconductors, -1- opposite to the incident light side,
The heterojunction solar cell according to claim 4, wherein the outermost semiconductor of , ^r is . 6. The heterojunction solar cell according to claim 4, wherein the crystalline semiconductor is a thin film semiconductor. 7 One unit cell made of an amorphous or microcrystalline semiconductor with a PIN junction on the amorphous semiconductor side of an intermediate cell made of a PN junction of a single crystalline or polycrystalline crystalline semiconductor and an amorphous or microcrystalline amorphous semiconductor.
A heterojunction solar cell in which more than one unit is stacked in series. 8. The heterojunction solar cell according to claim 7, wherein the crystalline semiconductor is a wafer. 9. The heterojunction solar cell according to claim 7, wherein the crystalline semiconductor is a thin film semiconductor. 10 A plurality of unit cells in which a single crystalline or polycrystalline crystalline semiconductor and an amorphous or microcrystalline amorphous semiconductor are PN-junctioned are connected via an amorphous semiconductor 2- whose valence is controlled in the same manner as the crystalline semiconductor. One unit cell is stacked in series and further has a PIN junction made of amorphous or microcrystalline semiconductor.
A heterojunction solar cell in which more than one unit is stacked in series. 11. The heterojunction solar cell according to claim 10, wherein among the crystalline semiconductors, the outermost semiconductor opposite to the Daikenko side is a wafer. 12. Heterojunction solar type 8! according to claim 10, wherein the crystalline semiconductor is a thin film semiconductor. ! . 13. A method for manufacturing a heterojunction solar cell in which a PN junction is formed by depositing an amorphous or microcrystalline amorphous semiconductor on a single crystal or polycrystalline semiconductor in a low-temperature process.