JPS59175067A - Reproducer - Google Patents

Abstract

PURPOSE:To perform quickly and easily a random reproduction by cutting off the addresses which are generated at random when the coincidence is obtained with the contents of a memory circuit for reproduced addresses. CONSTITUTION:The addresses delivered at random from an address signal generating circuit 17 of a random address designating circuit 15 are compared with the previous addresses which are written to a memory circuit 20 for reproduced addresses after detecting a disk 1 via a gate circuit 18 through a comparator 22. Then an AND gate 28 is closed by the coincidence output of the circuit 22, and a gate opening pulse does not arrive at the circuit 18. Therefore the random address given from the circuit 17 is cut off, and no retrieval is given to the disk 1. In addition, the address is also cut off even in case the random address is maximum. In such a constitution, a random reproduction is performed quickly and easily for the Japanese playing cards of one hundred famous poems, etc.

Description

[Detailed description of the invention]

TECHNICAL FIELD The present invention relates to a playback device such as a video or audio disc player, and more particularly to a playback device suitable for games, learning, etc. 2. Description of the Related Art Devices for searching and reproducing an address or information @i specified by a user are already known. However, no device has been proposed that performs address designation 7 and reproduces data substantially independently of the user's will. OBJECT OF THE INVENTION Therefore, an object of the present invention is to provide a playback device that can quickly and easily perform random playback. Structure of the Invention To achieve the above object, the present invention provides a random method for randomly generating ah address signals corresponding to at least all addresses in a recording medium in which one bale of information blocks are recorded at predetermined addresses. an address signal generation circuit; a reproduced address storage circuit for storing an address signal already reproduced based on the address signal obtained from the random address signal generation circuit; and an address signal stored in the reproduced address storage circuit. Regenerated address signal and +=
and a random address designation circuit consisting of a reproduction specified address transmission prevention circuit that prevents the reproduction specified address signal from being transmitted at once, and a reproduction specified address signal randomly generated from the random addressing circuit. A reproducing apparatus characterized in that the reproducing apparatus is configured to responsively search the recording medium Ky' for an address corresponding to the reproduction designation address signal and reproduce the plurality of information blocks randomly and selectively. It is related. Effects of the Invention According to the above invention, a reproduced address storage circuit is provided to prevent a reproduced address from being designated again.1 This makes it possible to perform random reproduction quickly and easily. Embodiment 1 Next, a reproducing apparatus according to an embodiment of the present invention will be described with reference to the drawings and 21st page. In FIG. 1 showing an optical disc reproducing device, (1j is an optical disc as a recording medium, and address signals and information blocks are sequentially recorded in spiral or concentric circles at 00). (2) is an optical character reader, i.e., an anti-woven head or a reproducing pickup, which projects an original beam (3) onto a disk (II) on which information is digitally recorded using optical bits, and detects its reflection. disc flll by light
It optically reads and fights the information signals and address signals that are being sent. (4) is a disk rotating motor. This is a device that generates a scanning movement in the rotational direction between the disk [IJ and the beam (31).
In the case of a disk on which K1 frames of the circumference are recorded, it is rotated at a constant speed, and in the case of scanning all tracks at a constant speed, the rotation speed is different depending on the radial position. (5
+ is a radial feed device, which feeds the reader +21 in the radial direction of the beam (31)
) The reading device (2) guided in the radial direction is sent in the radial direction by the rotation of the screw barrel (7) screwed therein, but it may also be sent by a belt or a pinion and a rank or the like. In addition, the a-removal device (2) may be fixed and send the disk (moon) in its radial direction. This is a circuit that sends out the playback output obtained from the reading device (2) of the same type as (9+ is a playback output gate circuit, and the playback output line +81 in the search mode
This is a circuit that can output the reproduced output obtained from VL only during the period of the target address, that is, the designated address, without outputting it to the cabinet. [101 is an address detection circuit, which detects an address for retrieval based on the reproduced output from the reading device (2). Uυ is a search address comparison circuit, and the address detection circuit w
3(1(u) This is a circuit that outputs the match between the detected address A1 detected by u and the address A2 (target address) specified by the specified address signal supply line U, and the difference between the detected address A1 and the specified address A2. .This comparison circuit Uυ
The output showing A r = Az obtained from is line u3
1 controls the reproduction output gate circuit (9) to turn on. That is, when the specified address A2 is retrieved, the control 1 is performed so that the reproduced output is sent out through the gate circuit (9). It controls the feed device (51) so that A2 = Al.To explain this feed control circuit 04 in detail, in the search mode, based on the value of At Al obtained from the comparison circuit (111), It has a function to decide whether to search by high-speed feed or LE/low-speed feed, and the difference A2 Al between the specified address A and the detected address (current address) Al is a constant value (83).
If larger, lAw All is a constant value A3
The beam (3) is sent at high speed only to the sender, and then the beam (3) is sent back to the normal feeder. In addition, the specified address A2 and the detected address

[If you are currently close to Addressov, then AIA, -A, l<
In the case of A3, the search will be completed in a short time even if it is normally fed, so it will not be fed at high speed but will be fed iE. The above has described an example of a search method, but the present invention can also be applied to the full search method of this search method J2IIA.In short, the specified address A. The present invention can be applied to any type of device as long as it is capable of searching address A2.Q51 is a random addressing circuit newly provided based on the invention. Deluri, random playback switch (161
This is a circuit that randomly sends out a reproduction designation address signal A2 every time it is operated. Nll, this random addressing circuit (151) is a circuit that cannot send out an address signal determined based on the user's will, and sends out an address signal that is substantially unpredictable. 07 ) is an address (there is a complete if signal generation circuit, based on the clock signal, for example, a digital input H indicating address 0 to ]27).
This is a circuit that generates the address signal C substantially randomly and repeatedly. In this embodiment. A random address signal generation circuit is constituted by the combination of this address signal generation circuit, the random reproduction switch α6), and the gate time 8 bet. (It prevents the output of the same address 1 ■ during 7 rays of one address signal from the output of the address signal generation circuit α, and also prevents the output of the address I which exceeds the maximum address of the disk tl+. In this state, the address signal is randomly held by the random reproduction switch 17 and temporarily held and supplied to the search address comparison 1alj@[11]. be. The meat is the reproduced address memory (b) path, and the disk 4 (I
After being reset with the reset signal generated by the reset switch &lIz>i on i based on the ejecting or loading of the +, power-on, reset operation, etc., all address signals, that is, regeneration currents that are output from the gate circuit σ~ This is a circuit that stores addresses. The mountain is a comparison path for determining a recycled address. Random address signal generation circuit (17+ output and p41
= The entire contents of the true address memory circuit F1?54 (compared with all memory addresses, and when the random address and the reproduction stream address do not match, the output line for opening the gate circuit α9 is generated and they match. When this occurs, a signal for controlling the transmission of the next clock's random address signal is sent to line 2.This comparison circuit (
22 has a built-in circuit that holds the final comparison result for a certain period of time. 251 is a maximum address check circuit for detecting the maximum address of ℃ disk (11) based on the output of the address detection circuit 0υ1. ・c15! is for storing and outputting the output of the maximum address check circuit 125. (C) is the address signal generation circuit (17).
This is a determination circuit for determining whether or not the current address output from address ff1l, that is, the specified address, is the maximum address detection circuit stored in the maximum address storage circuit side. The 1- signal indicating A2B, that is, the signal indicating the lower maximum address signal, is input to the AND circuit (28+) by the line □□□.-In the unlikely event that the signal A< B is the pulse generation circuit (to) by line ■υ)
) will be sent to. The pulse generation circuit (to) corresponds to the coincidence output of the reproduced address publication comparison circuit Q21 and the maximum address excess determination circuit +
In response to the excess signal (A<B) of 261, a single or selected number of random playback commands are executed with one time interval gcn.
is a circuit that generates a pulse equivalent to when the random regeneration switch (161'& ON is operated. Between the A and D circuits is a random regeneration switch α6) and a pulse generation time jif! i open and any mismatch output of comparison circuit w3 for regenerating barrel address determination, A≧B'I(
The outputs A and B of another (B) path Ztil are input, and when all these outputs are input at the same time, a high level output is sent out, and the gate (B) path U81 is controlled to pass the signal. . Also, the holding circuit α9 is reset to hold the new address signal. The output of the comparison circuit 28 for determining the reproduced address is connected to A to control the gate circuit 1- by valving the 9 circuit (28). A completed address sending blocking circuit is formed by the Hisoft 1 package and the gate circuit U. In addition, the player in figure 1 has a royal palace search address designation circuit C.
A1L is also provided. Therefore, it is possible to reproduce an address desired by the user. FIG. 2 shows the address signal generating circuit α7) of FIG. 1 in detail. In FIG. 2, the B input is a 7-bit shift register, which outputs digital signal portions or address signals substantially randomly from seven output terminals Qo to Q. The shift register B21 is configured so that when the power is turned on, a digital output in which 10'' and ``0'' are mixed at the appropriate level can be obtained, and the shift register B21 is configured so that it can obtain a digital output in which 10'' and ``0'' are mixed at appropriate intervals. Q
5 so that the memory contents shift toward 6. Puta. First stage output terminal Q. and the seventh stage output terminal Q6 are coupled to the input of an exclusive OR gate G41, and the output of this gate is coupled to the input terminal of the shift register 3z. Therefore,
A random ring counter circuit is constructed by a combination of a shift register c3z and an exclusive OR gate □. The following table shows a part of the output of the shift register c3z generated every clock. The address signal generation circuit α is connected to the random playback switch (
0~] in response to the clock signal regardless of the operation of 161]
27 address signals are randomly generated. Then, the period of the clock signal is set by the random playback switch α
Because it is smaller than the time interval of 61 operations by a light minute. The outputs sequentially obtained from the address signal generating circuit α are not directly used for address designation. Therefore, addressing 7 can be performed with sufficient irregularity. As is clear from the above, in this embodiment, the address signal generation circuit N (171 itself is a random address signal generation circuit, and the combination of the address signal generation circuit α and the random reproduction switch port 6) and the gate circuit α~ A random address signal generation circuit is also constructed for .degree. C., and in the end, the address is designated by double random f. Next, the handling method and operation of the apparatus shown in FIG. 1 will be described. For example, a disk +I+ is prepared in which information blocks of Hyakunin Isshu []00 waka 'Y]DO are recorded corresponding to each address. When starting Hyakunin Isshu, turn on the power switch and the play switch (not shown).As a result, the address signal is generated randomly every clock from the address signal generation circuit αD.However, the gate circuit a& is off, the signal indicating the designated address A2 is not generated. - 10,000, the motor t41 rotates the disk [11, the reading device +21 starts reading the recorded signal, and the signal is recorded on the first part of the disk tl+. The maximum address detection circuit i25+ detects the signal indicating the maximum address obtained based on the reproduction of the maximum address on the disk, or the maximum address obtained based on the reproduction of the maximum address of the disk +I+, and this maximum address is stored in the maximum address storage circuit. (39).Also, by turning on the power, operating the play switch, or resetting the reset switch, the reset switch υ is turned on, and the playback address name memory circuit (20j) is reset before the start of Hyakunin Isshu. Ready to start. There':, f
To obtain the audio output of the first waka based on ISUK [11], turn on the random play switch for a short time. As a result, the reproducing command signal is supplied to the gate circuit α through the AND circuit (c), the gate circuit is opened, and the address signal is sent to the holding circuit α. However, if the discrimination circuit Qb detects that the address signal generated from the address signal generation circuit αn is larger than the maximum address (A) at this point, the line G71 becomes low level, so that the switch 0bI is turned off. Based on the operation (the reproduction command signal is not given to the gate circuit jJ (181) and the address signal is not output from the gate circuit Oa. However, in this case, based on the A<B output of the v4J separate circuit (26) The pulse generation circuit 4J is activated, and a plow (pulse) is generated from this as a reproduction command signal, and the operation is equivalent to operating the switch (161) again.If it is AB at this point, the gate circuit α is activated. The address signal passes through. Furthermore, at the start of play, the content of Q in the input address storage circuit is zero, so the AND circuit @ is not restricted by the output of comparison circuit 0. As described above, the gate circuit When a reproduction instruction address signal is generated from time to time, it is temporarily held in the holding circuit (19) and stored in the reproduced address storage circuit 4. When the reproduction instruction address A2 is output from the holding circuit (I91), it is stored in the known address signal A2. By the horizontal movement, the reproduction instruction address A2 is searched, and the information block, that is, the Japanese poem, which has been completely recorded at the reproduction specified address is read out. The current scanning address A+ generated from the detection circuit 00) and the playback designated address A2 obtained from the holding circuit (1!1) are compared by the comparison circuit Uυ, and it is detected whether Ax = A2. And A2A
The output of x can be detected. Normally, the target reproduction designation address A2 does not match the current address A+, so it is impossible to read the decubitus toe and toe address immediately. Then, based on the input of A2 Ax, the sending control circuit 041 determines if the difference between the two addresses is large (Tel Ax A
If x l > As is detected, the beam (3) will be set by the difference between the playback specified address A2 and the current address AI.
VC in the disk radial direction? The feeding device (51) is driven and controlled so that it feeds at a speed of 2. When the high-speed feeding corresponding to A2 AIK is completed, the normal scanning state is returned, and the address detection time 8aO) obtains the current address A. If only A2 = Ax due to the error caused by high-speed feed. Feed control is performed so that A2 = Ax in normal feed, and when 60A2 = A+, the reproduction output gate circuit +
91 discloses the transmission of the playback output, and the waka at the playback specified address (target address) is read out. Of course, at this time, the beam (3) is controlled to be sent normally. Only the first readout of the waka is completed, When the cards are scattered, turn on the random playback switch 6) to read out the first waka. and. During this operation period, if the address signal generated from the address signal generation circuit σ7) is below the maximum address signal and is not a regenerated address, the gate circuit W5u8I opens and the address signal is input to the holding circuit 1. Then, a search is performed using the new reproduction designation address signal A2. −
10, the comparison circuit for determining the reproduced address (22) compares the same number of the reproduced atlus storage circuit 4 and the currently generated address signal, and if the two match, the AN
The D circuit (281) is in the off state only during the period of the address signal, and the gate circuit α~ is also kept off, and other signals of the playback designated address are not output.However, the coincidence output of the comparison circuit causes the pulse generation circuits to rotate. and switch Q6
After a short period of time after operating 1, press the switch (Ifi +
A pulse that has the same function as the operation of is applied to the gate circuit, and an address signal is output from the gate circuit. If an address signal that satisfies the maximum address drop condition and the non-reproduction condition is not obtained even in period t-j of the J-th pulse of the pulse generating circuit C301,
The second pulse generator is generated using the pulse generator circuit diagram 1. As is clear from the above, it is untrue! Example i has the following effects: When the random playback switch σ6j is operated, an addressing signal is randomly generated from the random addressing circuit (151), so it is possible to randomly play Hyakunin Isshu etc. (b) Since the reproduced address storage circuit cA is provided to prevent the reproduced address from being designated again, the same address will not be read several times.Therefore,
You can proceed with the desired play quickly with Vcp9T. (c) Since the maximum address storage circuit G51 is provided to prevent address specification exceeding -X from the maximum address, the play progresses quickly. - Pulse generation circuit diagram) is provided, so even if it is impossible to obtain the desired address distribution at the time of operating the random reproduction switch (161), it is possible to operate the switch [61 again or at no cost. Yes. Modification (A) The random address designation circuit (15+) may be configured with a microprocessor. ■ The address signal generation circuit is configured with a memory that stores all the addresses, and this one memo is used. ) may be used to randomly read the address signal. In this case, it is also possible to read the address signal at random from the address signal G and read the address signal from the address signal. If there is a gate circuit, the detection circuit 051 may be activated. ■ The forces S used in the gate circuit to prevent the maximum address from being exceeded and to prevent the designation of a regenerated address may be provided independently. [ F] In order to manage address detection even during high-speed search, the address of the disk (1) is detected based on, for example, the detection of the radial position of the reader (2), and this address detection Based on "'cpyT fixed address periodic test dress. (A method of changing the rotational speed of the disk 111 so as to keep the scanning speed of the trunk by the G beam (3) constant;
This method can be used in combination with the method of rotating the disc il+ at a constant speed. It is also possible to add a circuit that generates multiple pulses only in time.In this case, the first pulse does not satisfy the condition that the address is not reproducible and the condition that the address is less than the maximum address is satisfied. Therefore, it becomes possible to automatically specify the next address.CI+ switch may be directly connected to the output line of the Y address signal generation circuit u7I.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a playback device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the address signal generation time 8 of FIG. 1, and FIG. 3 is a waveform diagram showing a modified example of the playback command. . (1)... Disc, (21... Reading device, (5
j...Cow radial direction feed device, (9j...Reproduction output gate circuit 1 port Or...Address detection circuit, aυ...Comparison circuit, (141...Feed control circuit. G51-゛Random address Designated circuit, a6)...Random playback switch, G7)...Address signal generation circuit, fixed circuit, Shi0)...Regenerated address storage circuit, Z21...Regenerated address determination comparison circuit,
G51... Maximum address storage circuit.

Claims (1)

[Scope of Claims] A random address signal generation circuit that randomly generates a plurality of address signals corresponding to at least security addresses in a recording medium in which multiple information blocks are recorded at predetermined addresses, respectively. . a reproduction stream address storage circuit for storing an address signal already reproduced based on an address signal obtained from the random address signal generation circuit; and 5 addresses identical to the reproduction tube address signal stored in the reproduction address storage circuit MK. and a reproduction flow address transmission prevention circuit for preventing the signal from being transmitted. A random address designating circuit is provided, and in response to one playback designation address signal randomly generated from the random address finger/foot circuit, one address is set in the recording medium corresponding to the name playback designation address signal. search,
A reproducing device configured to randomly and selectively reproduce the plurality of information blocks. +21 The random address signal generation circuit generates all addresses of the recording medium based on the clock signal.
An address signal generation circuit (I) that generates the above address signal
7). Randomly selected from the multiple information blocks]
・Random playback switch U to be operated when playing one
With υ. The output of the address signal generating circuit α is sent out only during the period corresponding to the operation of the random reproduction 2 inch (161).
A reproducing apparatus according to claim 1, which comprises a gate circuit UU81. (31) The playback device according to claim 2, wherein the address signal generation circuit (17) is a ring counter that randomly generates an output.