JPS59171279A - Synchronous controller of video disc player - Google Patents

Abstract

PURPOSE:To simplify the constitution of a video disc player by synchronizing respectively a reproduced vertical synchronizing signal and a reproduced horizontal synchronizing signal to an external vertical synchronizing signal and an external horizontal synchronizing signal. CONSTITUTION:A phase locked loop PLL11 generates an auxiliary horizontal synchronizing signal FHS having a prescribed relation to a frequency of the external synchronizing signal. Then, a PLL control section 22 controls the PLL11 in response to the phase difference between the external vertical synchronizing signal FVO and the reproduced vertical synchronizing signal FV so as to change the relation between the frequencies of the signals FHS and FHO. Further, the phase between the signal FHS and the reproduced horizontal synchronizing signal FV is compared by a phase comparison section 17 and a drive control section 19 controls the rotation of a video disc based on an output of the result of the phase comparison. Then, the signals FH and FV are synchronized respectively by the external horizontal synchronizing signal FHO and the external vertical synchronizing signal.

Description

[Detailed description of the invention] Industrial application field. The present invention is a recording medium in which a video signal is recorded. 1. Background Art and Problems Related to a Synchronization Control Device That Plays the Role of Playing Video Signals at a Predetermined Timing in a Video Disc Player That Plays All Video Signals from a Videotask Having a Video Disc Player The signal rotates a videotask in which a spiral recording rack is formed, for example, with an arrangement of pits I, and an optical reading means, for example, follows the recording rack. In a videotask player that obtains a read signal and reproduces a video IB signal from the obtained read signal, the timing of the reproduced video signal, that is, the vertical synchronization signal and horizontal synchronization signal in the reproduced video signal. Around the signal? Iterative number and place lq, . k. Control 9111 the motor that is driven to rotate from the Viteo f1 Isk j and rotation axis V to the predetermined synchronous control.
The motor that rotates the video disc is usually referred to as a DC servo motor and is called a spin motor.
(Hereinafter, the moke that rotates the video disc is referred to as a spiered motor.) Is this a video disc borrowed couple? When the reproduced video signal obtained from the videotask player is supplied to a monitor receiver which is externally synchronized from the perspective of the videodisc player, and the reproduced image is obtained, the reproduced video signal from the videotask player is supplied. Vertical and horizontal synchronization signals in No. 18,? In other words,? It is necessary to synchronize the raw vertical and horizontal synchronization signals with external vertical and horizontal synchronization signals, such as vertical and horizontal synchronization signals, which control all operations of the monitor receiver.
, In such a case, in a conventional videodisc player, first, an external vertical mouthpiece is input. and the reproduced vertical synchronization signal is detected, and based on the detected phase difference. Spintle. - When the motor is controlled, there is an external direct synchronization signal and i'l'i:/. :I Taru W “DojJI
Phase between signals: Example of phase difference, . ．． The phase difference is set to zero or a predetermined relatively small phase difference. Vertical phase servo controller 1 roll. will be held. Next, with the phase difference between the external vertical synchronization signal and the lifelong vertical synchronization signal maintained at zero or a predetermined relatively small phase difference,
Is there a phase comparison between the partial horizontal synchronization signal and the reproduced horizontal synchronization 1 word? For comparison output? The system spindle motor is then controlled and switched to the horizontal phase servo control which makes the external horizontal synchronization signal and the reproduced horizontal synchronization word have the same phase. In this way, The vertical phase servo control state and the horizontal phase servo control state are taken sequentially, and in the horizontal phase servo control state, ? The reproduction vertical and horizontal synchronization signals are synchronized with external vertical and horizontal synchronization signals. However, in the external synchronization control in such conventional video disc players, the servo control state for the spindle motor is Do I have to switch between the external vertical synchronization signal and the playback vertical synchronization signal? Is the stationary phase difference between zero or a predetermined value? relatively small? phase difference. must be strictly maintained, so i'l {do synchronization control within the videotask player? The synchronous control device performs these switching operations, ah? It is necessary to provide auxiliary circuits for maintaining the steady phase difference, and it is inconvenient that it is not possible to use a circuit C having the structure 1. Object of the Invention 1!l1 In view of the above, the present invention provides a method for obtaining a read signal from a video recorder and reproducing all the obtained read signals. With a simple +1ξ fee, the playback vertical and horizontal synchronization signals in the playback video signal can be ensured to be synchronized with the external vertical and horizontal synchronization signals of a video disc player. Synchronization 9
The whole purpose is to offer 111 goso e 1゛ to l'ju.”
1. What is the same for the videotask player according to the present invention? Term 11 device is rotating. Viteotei who is excited? The synchronization component that generates the reproduction vertical synchronization signal and reproduction horizontal synchronization signal i= obtained from the read signal from the disk? A phase locked signal is supplied with an external horizontal synchronizing signal as a basic signal and generates an auxiliary horizontal synchronizing word having a frequency determined by a predetermined relationship with the frequency of the external horizontal synchronizing signal. The phase-locked loop section is controlled according to the phase difference between the loop section, the external vertical synchronization signal, and the reproduced vertical synchronization signal, and the frequency of the auxiliary horizontal synchronization word 1 and the frequency of the external horizontal synchronization signal are adjusted. A phase locked loop control section that completely changes the relationship between the signals, a phase comparison section that compares the entire phase with the auxiliary horizontal synchronization signal and the circular horizontal synchronization signal, and a phase ratio correction section that controls the video disc. A drive control unit that controls rotation, and a reproduction direct synchronization signal and a reproduction water synchronization signal are synchronized with an external vertical synchronization signal and an external horizontal synchronization signal, respectively. It is made to be. By doing so, the switching from the vertical phase-ribo control 1 roll state to the horizontal phase-rotation control state regarding the rotation control of the video disc, which is performed in the conventional synchronization control device, can be performed. or. ,external. Vertical synchronization signal and playback. Between vertical synchronization signal: Steady. Strict maintenance of phase difference becomes unnecessary: Therefore,. The configuration has been simplified. Become something.

Embodiments Hereinafter, embodiments of the present invention will be described with reference to all the drawings.
, Figure 1 shows a video according to the present invention. Days. Ku player's same period flj! This is an example of a video disc that has been recorded with a modulated video signal.
This example is applied to a video disc player that plays video and audio signals.・Sh. , recorded on a video disc that can be rotated, rotated, and moved. ．． The signal is read in the original academic format. A pick amplifier that was used as a means etc. It is read and picked up. 1 word S is obtained from reading.
The leaking read signal S is amplified to a predetermined level by an amplifier circuit, and then shaped into a predetermined waveform by a waveform shaping circuit 3 before being supplied to a filter circuit 1. The filter circuit receives an audio signal S'a modulated from the waveform shaping output of the read signal S and a video signal SV modulated by n frequency.
t min. 1 [shi] and derive each one separately. These modulated audio one word Sa and modulated video one word Sl
v is respectively supplied to the audio demodulation circuit SEI and the video demodulation circuit B, and is demodulated.A reproduced audio signal S.A is obtained from the audio demodulation circuit S, and a reproduced video signal Sv is obtained from the video demodulation circuit B. are obtained and led out to terminals 7 and , respectively.

The reproduced video signal Sv is also supplied to a synchronization separation circuit. n. ．． 'From the sync separation circuit W, the reproduced video signal S
A vertical synchronization signal and a horizontal synchronization signal in V, that is, a raw vertical synchronization signal Fv and a reproduced horizontal synchronization signal FI{ are obtained.

On the other hand, what about from terminal /0? An external horizontal synchronizing signal F110 is supplied, and this external horizontal synchronizing signal Fno is guided to a phased locked loop circuit (hereinafter referred to as a PLL circuit). PL. L circuit //(1″1:, output of voltage controlled oscillator/2, voltage controlled excavator/2, π (n is a positive number)
A frequency divider /3 divides the frequency, a fourth comparator /no, . phase. ratio. Mosquito organ/ge nu no. Is the total output voltage controlled by one oscillation load/? It is formed by a low-pass filter /5 which is supplied to the oscilloscope, and a frequency divider /B which divides the output of the voltage controlled oscillator /2 by m (a constant positive number). Then, at the output end of the Wanderer/Otsu, which is the output of 1 Confucian, the supplementary water is generated.Here,
External horizontal synchronization is No. 'FHO! Assuming that the wave P is all fho, supplement ■
ψIf the number of cycles per period of the horizontal synchronizing signal 'ff'n's is tfhs, then flsLrJ. fl15"'"j':l1IQ4
The relationship is constant 1, . Sleeve JQ horizontal synchronization signal FHs obtained from PLL circuit //
From pm component 11 circuit 7. can get. Endogenous horizontal synchronization 1
Word F■1 and. 1>Then, the comparison 1j3 force from the phase comparator circuit /7: is supplied to the circuit /7, and then the comparison 1j3 force from the phase comparator circuit /7 is driven through the addition circuit /g:. ．． Supply is tight to the movement control 11c I road/9. Driving power:
circuit/. 9 is the spindle mork according to the comparison output X, 20 times I1?朊 11、Thereby, the rotation of the video disc. Control and compare output X power! , auxiliary water 4
The reproduction horizontal synchronization with the US synchronized car numbers F and HS is such that it is obtained when the US synchronized car numbers F and FH are in the same phase. That is, the rotation of the spindle motor 20 is controlled by the drive control circuit/9 in accordance with the comparison output X from the phase comparison circuit/7, and ? I” raw horizontal synchronization signal FH or auxiliary horizontal four-phase {word F
The servo control is performed in synchronization with Hs.

An external vertical synchronizing signal Fvo is supplied from the switched terminal 2/, and this external vertical synchronizing signal Fvo (/i) is supplied to the PLL control unit 22 together with the reproduced vertical synchronizing signal Fy from the synchronization separation circuit. .The PLL suppressor 22 detects the phase difference between the external @ direct synchronization 1 word Fvo and the reproduced synchronization signal Fv, and uses the detected output Y to control the frequency divider /3' of the PLL circuit //. il-control and change the frequency division ratio in the frequency divider /3.In that case, 1 is the ratio between the reproduced vertical 4-cycle 1 word Fv or the external vertical synchronization signal Fvo.K. The period of the external horizontal synchronizing signal FHO, that is, half of the horizontal period (hereinafter referred to as horizontal period total H), that is, 0..tHf.
When the phase is delayed by more than the phase amount corresponding to C, the division ratio of frequency divider/'3 is nf at the division ratio of frequency divider/B, 1+1. ] η from m, and reproduced vertical synchronization No. 1n FV
is 50. compared to the external vertical synchronization signal FVo. When the phase is advanced by one scale μ corresponding to the tide H, n is smaller than m, and the phase difference between the reproduced vertical synchronizing signal Fv and the external vertical synchronizing signal FVo is 0. When the phase force J corresponding to the tide H is small, 11 is made equal to 1]).

Then, the reproduced vertical synchronization signal Fv is the external vertical synchronization signal Fv
Compared to o, there is a delay of more than 4 scales equivalent to 0.5f-IC at 4'[1, and if n is taken to be a dog from m, then T)
The frequency fh. of the auxiliary synchronization signal FH's obtained from the LL circuit //. s'i is the frequency fhoJ of the external horizontal synchronization signal FHO: and becomes higher, and the reproduced horizontal synchronization signal is accompanied by the rotation control of the spindle moder 20 in accordance with the comparison output X from the phase comparator circuit/7. Since the servo control is performed so that F'H is the same as the auxiliary horizontal synchronization signal Fl{s'VC, the playback horizontal synchronization number F is
The frequency of H is the frequency of external horizontal synchronization 1st gear 1st FHO t'JJ
;． The VC21 river is marked so that it is higher than the number fho.In any case, the reproduced vertical synchronizing signal F'''V will have a phase advance, and the reproduced vertical synchronizing signal FV will be The phase difference between the vertical synchronization signal F'vo and the vertical synchronization signal F'vo is reduced.When the phase difference between the two becomes smaller than the phase meter corresponding to 0.2'rc, the PLL control unit .2,2'rc is detected, n is equal to m, and as a result, the auxiliary horizontal synchronization signal FHS and the external horizontal synchronization 1
It has the same frequency and phase as the portrait FIlIO. The reproduction horizontal synchronization signal FH is always the auxiliary horizontal synchronization signal fi signal FH.
Since the external horizontal synchronization signal FHO is controlled to be synchronized with the external horizontal synchronization signal FHO, the reproduction vertical synchronization signal F'H is eventually synchronized with the external horizontal synchronization signal FHO. Signal Fv will also be synchronized with external vertical synchronization signal Fvo.

1, the reproduced vertical synchronization signal Fy is the external vertical synchronization signal Fvo
Compared to , o:ssvC is in an advanced phase by a phase amount of h, and if h is smaller than m, then the frequency fhs of the auxiliary horizontal synchronization signal F'HS is equal to the external horizontal synchronization signal F'HS. Signal FHO
frequency fho. Then, since the reproduction horizontal synchronization signal FH is synchronized with the auxiliary horizontal synchronization signal FMS, the servo control is performed, r+i/
:+- The frequency of the horizontal synchronization signal FH is controlled to be lower than the frequency fho of the external horizontal synchronization signal F}to. Along with this, the reproduction vertical synchronization signal Fv
As a result, the phase difference between the reproduced vertical I6 synchronizing signal Fv and the external vertical synchronizing signal Fvo decreases. And the phase difference between both provinces is 0. When the phase amount becomes smaller than the phase amount corresponding to &H, this is detected by the PLL control unit 22, and 1) becomes equal to n], and as a result, the auxiliary horizontal synchronization first floor FHs and the external horizontal synchronization signal FHO have the same frequency and the same phase. And, Hio horizontal synchronization 1 town number F. n
is synchronized with Sodesuke Mizumo synchronization signal Fns J: Sea urchin control l
'iI'II, so the raw horizontal synchronization signal FI■ is likely to be synchronized with the external horizontal synchronization signal F'HO, and along with this, the reproduced vertical synchronization signal FV is also synchronized. The external talent F will be synchronized directly with the FVQ aboard ttJI. , Of course, the reproduced vertical synchronization signal Fv and the external vertical synchronization signal FVO
The phase difference between the two is initially 0.5H [/? :． If it is smaller than the corresponding phase amount, n is made equal to m, and the auxiliary horizontal synchronization signal FHS and external horizontal synchronization signal PI{O・ are made to have the same frequency and phase, and as a result, the reclaimed water The synchronization signal FH, the reproduced vertical synchronization signal F'v, the external horizontal synchronization signal FHO and the external vertical synchronization signal FvoK are respectively synchronized.

In the example shown in FIG. The signal is supplied to the drive control circuit /'? through the adder circuit 1g, thereby controlling the speed of the spindle motor 20.

The present invention shown in FIG. According to the synchronization control device for a video disc player according to the invention, the playback vertical synchronization signal f? 'v and reproduced horizontal synchronization signal FH are external vertical synchronization signal FVO and external horizontal synchronization signal 'FI{o
Next, let n in the frequency division ratio m of the frequency divider /3 of the PLL circuit // be determined as m. ]: 9 large, m is small, if so, do the same as n m by 1, fljli11', 1, the above P
I,L control section. To explain the details of 2.2 by giving an example, FIG. ρ shows I) LL control section. 2. ．． An example of 2 is shown below.

An example of this figure ρ {.・In this case, the external vertical ILf synchronization signal FVO is fed to the terminal 30VC4, and the column vertical synchronization signal Fvo is 2 as shown in FIG. 3A.
It is a frame synchronization signal that arrives every vertical period (hereinafter referred to as vertical period V), and has a width equivalent to 1 signal FvO and 3H for each synchronization. t/ke synchronization signal F. It shows the period corresponding to 7H in the middle of L.Vo. 2 is jJIli. It indicates the period from the end of tlt/ to the time point J when /V passes from the leading edge of the synchronization signal Fvo. , L3fm. i: fυ1 t.
From the beginning of 2 to the next yo M t/beginning of 1 ri-ma-te no tan [V
Show Kawakin. , ,l, ;i. The synchronizing signal P'vo from i-30 is transmitted to three monostable multi-bicycles (referred to as MM) 3/, 32 and 33j, each having a different time constant.
(From M.M3/, as shown in Figure 3B, starting from the leading edge of the same SU14s Fvo, the fossa level h is set during the period corresponding to /H, and it is lowered during other periods. Level 1=,
A signal P/ which takes H is obtained, and M'M. From 32, Figure 3C
Starting from the leading edge of synchronous fB FyOo as shown in 1
A signal P2 is obtained which takes a high level 1] during a period corresponding to 2H and a low level 1 during the other periods.
As shown in FIG. 3D, an information signal P3 is obtained which takes a high level h during a period corresponding to /V starting from the leading edge of the synchronization signal FVO and takes a low level 2 during other periods. . Then, the inverted output from the signal P/f inverter 3 and the signal P
2 is supplied to the anode same:635, and the AND circuit.
? 5, as shown in the 31st UIE, a signal Pq is obtained which takes a high level 11 in all periods L and a low level t in 9 other periods.
Inverted IL4J by B, the force and signal P3 are AND circuit 3
7, and from the AND circuit 37, a 1 bar signal P3 is obtained which takes a high level 11 in the period t2 and a low level lv,- in the other periods 9, as shown in FIG. 3F(c). .

Additionally, the inverted output of the signal P3 by the inverter 3g and the signal P/ are supplied to the OR circuit 39, and from the OR circuit 39, as shown in FIG. A signal -\'PA that takes 'f+1 and has a low level in other periods can be obtained. These signals Pt. P3 and P
Rupa, D-Frisob Frotub (hereinafter referred to as D-FF) G0. 'l/ and l/t2 are supplied to the data terminals J), respectively.

On the other hand, for End/Ryogu 3. F] Raw vertical synchronization signal Ui''V is supplied, during this time jυ1 number Fv is also frame 4 period 1
? -i, and it is said to have the full width equivalent to 3H in the fixed state, and MM/l. Goo IC supplied 1
To J-IM g/l, for example, j:lj level 1] wo and shif for a period corresponding to 5H from the front edge of the regenerator bow Fv.
ll! ．． Low level between {υ] /. t takes Hakugo P7f occurs, and three I). -FF G0,4t/and O-daλ are supplied to the clock terminal C of the people, and the falling 9esoji from the quotient level l1 of the signal 1]7 to the low level is 1), fi]i
rg0,g/andhi/I-Kronok and σ for recognition.

1 liter, one run of I] LL circuit // frequency divider / 3 frequency division [
'1'E111 and fxjifill
illll signal y/, nn illll control signal \Y2 that satisfies tjn+1 < (k is a positive number)
, and n gold m. '-k and no control A1] signal V3t,
Control signal sources /1, /1 and terminals are respectively provided to generate control signals, and the output terminals of each are connected to a common output terminal via terminals 9 and 50.
These switches qg, tiq and 50 are respectively D-'
- The on/off state is controlled by F'F'IO, ll/, and the output terminal Q of the goo, q/l, Q2 and q3, and the corresponding outputs q/, q and q are at high level. h
Only when it is taken, it is considered to be on-go-one-no-ko state.

For example, the Nyu vertical synchronization 1 word Fv is shown in FIG.
As shown in Figure 1, there are periods t and x, and as a result, the third
As shown in Figure 2, the time T of the falling edge of 14-inch P7 is within the period t (in other words, 11) when the raw vertical synchronization signal Fv is compared with the external vertical synchronization signal Fvo. hand,
In a state where the signal is in a delayed phase of 1q phase and 1y and 2 times corresponding to 0.3HI/ko, Shinzuki P3 takes a high level of 11 at time T, and signals 1) and 2 take a low level of t. D-
．． FF'! 0. K/and q. 2. Each of the fields q. 7,q
2 and q,? Only q out of them becomes high level l],
q/ and qJ are at low level l, 2 Therefore, only switches 'I, g, , /l9 and 4t9 of 50 are on, 1' is off, and evening g. and Shio 0 are turned off, and from the fltlj number 13 source. The allocation signal y2 of the output anchor {child left/from
j■11 detection output) 11 is sent as 1l, so that II becomes rn+1<, and n becomes larger than 111.

1. In a state where the time point T of the falling edge of P7 is within the period t3, that is, the direct synchronization signal Fv is 0.0% compared to the external vertical synchronization signal Fvo. ．． ．． In a phase 18 corresponding to tI-i, in a state where there is an upward phase, the time point T is
) Since B takes high level h money and 9, {word name Pl & and P3 are low level l, . J) - Output q3 of FF Ω? 1] Reach level h and... D-F1j''IO and HiLl/
The output of q/ and q. 2 is low. Become a bell, follow"
C, switch NO is turned on, switch /Ig
Then, the filter is turned off, and the ifillfllli signal y3 from the flil+ control signal source 7 is sent out as the detection output Y from the output terminal. This nine ((from, n is +
nk, and n is m less than 9, which means K.

In addition, the time T of the falling edge of the signal P7 is period 1i43.
tz, that is, the phase difference between the IIl raw vertical synchronization signal FV and the external vertical synchronization signal Fvo is θ. Shio. ．．
In a state where the phase amount corresponding to Hvc is smaller than the phase amount corresponding to / becomes a high level h, and the outputs of D-FF g/ and q) become low level L. Therefore, the switch llg is turned on, and the switching 7 and SO are turned off. The control signal yi from the control signal source 15 is sent out as the detection 1, IJ force Y from the output terminal 5/.

This makes 1] equal to January. Another specific example of 2.2 is shown below. In this example, the terminal O/ is supplied with an external synchronization signal Fvo, similar to that in the example of FIG. Ω, as shown in FIG. In the tide chart, one synchronization signal Fv. At the time T/, /V, a period corresponding to 0.3H has elapsed since before ^ o. JUl of culm
A time point T2 at which the interval has elapsed and a time point T3 at which the /■ has elapsed are shown.
11 point T < t and the same culm 1 ν before the stage of pounding 1 1 {S No. Fv
'． 0 from the leading edge of 0. '! f;. At the terminal 11, where the previous times T and t are shown for a period corresponding to 1-1, there is the same il worker shift synchronization signal F■ as in the example in Fig. These synchronization signals Fvo and Fv are supplied to the set terminal S of FF Otsu3 and the reset terminal J-terminal; ? -Fi; 'Otsu 3 believes in the same period F'vo
At the leading edge of O, it is set 1.σ:j'J, and at the leading edge of the synchronous double number Fv that arrives after that, it is reset l.
QV? l, Synchronous IR No. "VQ's I) High rate per period in the period at the front end of the same store No. FvO which subsequently arrived from the 11th edge"]
Gold and (9, emit signal Uθ that takes low level l in other periods, 7in I... Reset - FF from Otsu 3, Uo, counter Oda's enable mother-daughter EN (reset). , while the counter Uθ takes a high level 11, the clock pulse CL supplied to the terminal C counts as quickly as 1, and for each count of the counter Uθ. The count output No. is supplied to one input terminal of each of the S digital comparators Otsushio, Otsuotsu, Otsu7, Otsug and Otsu9. At the other input terminal {, the counter [
・is from the leading edge of the synchronization signal F÷0 to the time T/lT. 2'+
Tj'; count value N/'rNa'+N3 that should be obtained when the test is carried out for a period up to each of T'l and Tr,
Nq and N3. A comparison is made with each of these digital ratios Otsushio to Otsu9, respectively 1"" force signal U/, "J-2, UJ+U
K and (Js are respectively "No is N/"2 and No is N.
2 or more, No is N3 or more, No is Ng or more, and N'
When o is greater than or equal to Ns, it becomes /7///, and otherwise it becomes "0".

Then, the signal ``/〃 supplied from the terminal 70 and the output signal U/ are connected to the circuit 7/(1711) which is supplied from the terminal 70. ,(#'.
'0' Hello, <{I Sat/77/' signal U6 is obtained, and j1:1 force fgi [J/ and U no are Exku no 1.' Names 7 and 2, the output signals U1 and Uj are excluded/pull-or circuit '7.
3 to 'i. The output signal U3' and the exclusive OR circuit 7' are connected to the exclusive OR circuit 5, and the output signal U3' and the exclusive OR circuit 7' are connected to the exclusive OR circuit 5 and the output signal U5 and 17. of “0” supplied by Party B. '' are supplied to the exclusive-OR circuit 77, respectively, and the exclusive-OR circuits 72, 7, and :? '、． '
? 'l', 7'3 and 7' each output na product, ``0''
” or /7’77/ signal TJ7’r”’U’
g"'+'Uq, U/θ and U// are obtained, respectively.
Furthermore, are the signals U'A and TJ// an OR circuit? 'gVc
Supplied? Part 1” i force, 7f hanging VCLr? It becomes LJ or "/": The number U・l2 becomes 141raha,ru.
, size, frequency division i of the above-mentioned P'L'L circuit/.../ R/3
11 Ken] and Nasu IQill on the hill)
4 words y'/, 11 total rn'+a. (a is a positive number) and the control signal y'λ, n is m+b' (b is a...l:!l
ll dog positive number) and nazffjllffllI word y'3
,! 1 total m-b and slow control: signal': 1. ．． '”y.'i
/． , and direct seal 17j between nl-a and 4・′su1{
Shi? , I'5. ”fi=.(+soku//,・depart/1, 1
Control signal sources 7f, g'c>', g. 'g'7 and gg are all connected to a common output terminal g9. These switches
ll- to gg are the signals Ul. 2 and U7~U/O
The on/off state is controlled by the corresponding ′ signal {
J/2 and U? ~LJzo is turned on only when it becomes "/", and for example, the 5 playback vertical synchronization signal F'v is
As shown in FIG. S, the leading edge time T' is located at lB1 between the entrance points T2 and T3. Vertical synchronization: 0.0 compared to signal Fvo. In a certain state, the lag phase (lζ) with a phase amount much larger than the phase corresponding to the phase H corresponds to the set/reset-Fl'i'' 3, as shown in the left figure C. During the period t' from the leading edge of the synchronizing signal Fv.o to the time T', a signal UO is obtained which takes a high level of 1, and during this period t' the counter tl
l's count[・is performed 1, and count 1・out. Power N. 0 is Count 1 (straight N and N.2 inferior thick., N
3 to N5, and at its end, output one word U/ and TJ. 2 is ``/'', ・1 其力f word〒U3～LT
5 becomes 17'0'' 6 As a result, the signals U'i and U
``7~TJto's? Among them, i'U is ``Pado?'' Natte et al. ．． ．． is #0, /4 and 1. ,? Follow: Out of Tesisochi gda ~ gg, only Otsu is in the on state, and the others are in the off state, fl! y'/ is from the output end -"Ag eaves, I) L, Ii control section Hayashi. 2.2 is sent out as the detection output Y, , . J'): 'From IC, l] is 1-1)
(m. Yo: Rita) and 3f. 1. 1,. :・． , 1,
7fl. 4 (Synchronized condolence ↑ No. T"v's leading edge point T' is located between IPI point IT't. t. 2 t (7):
Place-． r;6't5'j? j+, i.e. ilii41:
,乎'(n period Ibango Fv is external middle one. IH: i period {
,N,,,l. ``Compared to lFVo, it is equivalent to 0shio I-I, g111 is more dog, but it is much more dog (/j
: There is no delay in the appearance of the skin. ．． In a certain phase/vc state, counter [/output].ノNθ
In dogs, it is 1 smaller than Nβ~N6. , Na no Yumei Shin MIU
zl=and(fU7~IJ/θ ゐAmong them, only U7 becomes a "pa" and the others(ha/IQ'll roar,, Therefore, the switch g
．． Among y to gg, only g is turned on and the others are turned off, and the control signal y' is sent out from the output terminal g9 as the detection output Y.As a result, l] becomes 1. ]]
→-a (m is a dog, and m is smaller than b).

Similarly, time T' of the leading edge of the reproduced vertical synchronization signal Fv is between time T3 and Tq, or between time T. , and T5, that is, the state located between
is 0.0 compared to the external vertical synchronization signal Fvo. ．． An advanced phase of the phase ml which is much larger than the phase amount corresponding to 5-H,
If (P, the phase corresponding to o.sI-IVc: it is larger than 100,000 yen, but it is much smaller than 1) and is in an advanced phase of the amount {・1] (key, respectively, s' isochi g4t ~gg, only g7 is on, and the four main states are off, and the switch is off, and only gg is in the on state, and the other ( I is in the off state, and the control signal y'q is also {-, < ball, V's is the output terminal g
9 as a detection output (1"J is sent.1]] is smaller than m7b4m), or +n-a (m
It is smaller and thicker than m-1).

Further, at 0°C, the time T' of the leading edge of the reproduced vertical synchronization signal Fv is between the leading edge of the external/hand side synchronization signal Fy6 and the time TI, or before the time Tj and the next external synchronization signal FVO. In other words, the phase difference between the internal vertical synchronizing signal Fv and the external vertical synchronizing signal FVo is 0. The phase corresponding to s1{−ji. In the state where J:V) is small, the count output No is smaller than any of the counts niN'/~N, which is 9 dogs, so the output signals U/~U5 are both "0" or 2L
also “pa.,) c# result, signal U/.2 and U?”
Only 3U/2 of tJ/o becomes “/” /lli
d,'u//o77-. Therefore, switch g~
Of the gg, only g+ is in the on state and the others are in the off state!
River and sale, fltll! tllIi No. Y'i Ka. IE force 1'iM child g9ka C) Sent as detection output Y,,
Thus, 1] is equal to m: t1,.

Effects of the Invention As is clear from the above explanation, the present invention has advantages. According to such a synchronization control device for a video disk player, it is possible to immediately detect the phase of an accurate synchronization signal in the servo control of the spindle mork, which was necessary in the conventional synchronization till control device. The phase difference of the horizontal synchronization signal from the servo control state is quickly changed to the servo control state, and the steady phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal is strictly maintained at a predetermined level. It is possible to reliably synchronize the reproduced vertical and horizontal synchronizing signals with the external vertical and horizontal synchronizing signals, respectively, without compromising the overall performance. Furthermore, since there is no need to switch the servo control 1 roll state or maintain a steady phase difference between the external vertical synchronization signal and the reproduced vertical synchronization signal as described above, the circuit configuration can be completely simplified. Oh, PLL
circuits and P. The LL control section, etc. can be easily integrated into an integrated circuit, and by integrating these into an integrated circuit, there is an advantage that the circuit structure can be further simplified.

Figure 4 is a connection diagram showing an example of a synchronization ηill control device for a video disc player according to the present invention IJ'; Figures 10 and 3 are examples of the PLL control unit shown in Figure λ. The waveform diagram provided for explanation, Fig.
A block diagram showing another example of the LL flill control section, and FIG.

In the figure, / is a pickup, a filter circuit, O is a video demodulation path, 9 is a synchronization separation circuit, /0 is a terminal to which an external horizontal synchronization signal is supplied, '// is a PLL circuit, / is a phase comparison circuit, /9 is the drive IM1] control circuit, 20 is the spindle motor, 2/ is l1 to which an external vertical synchronizing signal is supplied.
1″1 child, .2λ is PLLiltll control 1, -449-

Claims (1)

[Claims] ．． ．． Rotation drive. a synchronization separator that generates a reproduced vertical synchronization signal and a live horizontal synchronization signal obtained from nine signals read from a video disc; Thousand synchronized faith! ．． is the basis. The frequency of the external horizontal synchronization signal, which can be supplied as a quasi-signal. The auxiliary horizontal synchronizing signal having the same wave number determined by the specified ratio is generated. The loop part, the external vertical same 1υj signal and the above reproduction. Detect the phase difference between the vertical signal and the phase locked/loose part k, t:i according to the detected phase difference.
ll bait 1 and the above. Frequency of auxiliary horizontal synchronization signal. and"
2) Change the relationship between the frequency and the frequency of the external horizontal synchronization signal. a phase locked loop control section, the auxiliary horizontal synchronization signal, and the reproduction horizontal synchronization signal. Towosuji. It's comparable to mosquitoes. The rotation of the video disc is based on the phase comparison section and the t'J force of the phase comparison section. 1. A synchronization control device for a video disc player, comprising: a synchronization control unit for controlling the playback vertical synchronization signal and the playback horizontal synchronization signal with the external vertical synchronization signal and the external horizontal synchronization signal, respectively.