JPS59171204A - Bias circuit - Google Patents
Bias circuitInfo
- Publication number
- JPS59171204A JPS59171204A JP58045136A JP4513683A JPS59171204A JP S59171204 A JPS59171204 A JP S59171204A JP 58045136 A JP58045136 A JP 58045136A JP 4513683 A JP4513683 A JP 4513683A JP S59171204 A JPS59171204 A JP S59171204A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- transistor
- amplifier
- resistor
- high frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
- H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は高周波用トランジスタのバイアス回路に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bias circuit for high frequency transistors.
第１図は通電使用されるバイアス回路を示す図である。FIG. 1 is a diagram showing a bias circuit used for energization.
バイアスの安定度を保つために、抵抗Ｒ４をエミッタに
接ｆｉ＝し、使用周波数で等制約にエミッタが接地する
ｊｌ永コンデンサＣ１を付ける。しかしながら、使用周
波数が高くなるにつれ、コンデンサＣ１による接地が困
難になり高価な高周波用のコンデンサを何本か並列にト
ランジスタのエミッタに出来る限り近づけて接続して使
用したりする。In order to maintain the stability of the bias, a resistor R4 is connected to the emitter, and a long capacitor C1 whose emitter is grounded is attached with equal constraints at the frequency used. However, as the operating frequency increases, it becomes difficult to ground the capacitor C1, and several expensive high-frequency capacitors are connected in parallel as close as possible to the emitter of the transistor.
さらに、これらの方法を用いても、使用周波数外ではコ
ンデンサＣ１が接地の役目をせず、トランジスタＴ几１
が発振した９する。Furthermore, even if these methods are used, the capacitor C1 does not serve as a ground outside the operating frequency, and the transistor T1
oscillated 9.
このために、エミッタを接地し、直流安定を保つ回路が
いくつか考えられている。第２図がその一例である。抵
抗Ｒ５にかかる電圧を基準にして常に抵抗Ｒ７にかかる
電圧が一定になる様に演算増幅器ＩＣＩの出力が制御さ
れるために、直流での安定が保たれる。For this purpose, several circuits have been devised to ground the emitter and maintain DC stability. Figure 2 is an example. Since the output of the operational amplifier ICI is controlled so that the voltage applied to the resistor R7 is always constant based on the voltage applied to the resistor R5, stability in direct current is maintained.
しかしながら、第２図の回路においては、電源の電圧変
動に対し、抵抗Ｒ５にかがる電圧が変動する事によシ、
電源電圧変動によりトランジスタＴ几２の電流が変化し
てしまう。通常トランジスタの高周波領域でのパラメー
タ、例えばＳパラメータや雑音指数はトランジスタのコ
レクタ電流に多くは支配されるために、第２図の回路で
は電諒審圧変動により、高周波も性も変化してし、マう
。However, in the circuit shown in Fig. 2, the voltage applied to resistor R5 fluctuates in response to voltage fluctuations in the power supply.
The current of the transistor T2 changes due to fluctuations in the power supply voltage. Normally, the parameters in the high frequency region of a transistor, such as the S parameter and noise figure, are largely controlled by the collector current of the transistor, so in the circuit shown in Figure 2, the high frequency and characteristics change due to voltage fluctuations. , Maou.
本発明は上記欠点を解決する為になされたものであり、
従って本発明の目的は、電源電圧変動に対しても常にト
ランジスタのコレクタ電流の変化のないエミッタを接地
さｎたトランジスタの新規なバイアス回路を提供するこ
とにある。The present invention has been made to solve the above-mentioned drawbacks,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel bias circuit for a transistor whose emitter is grounded so that the collector current of the transistor does not change even when the power supply voltage changes.
上記目的を達成する為に、本発明に係るバイアス回路は
、エミッタを接地したトランジスタにおいて、＋１ｆＪ
ＡＺ トランジスタのコレクタを第１の抵抗を介して
′屯ｄメに接続し、さらに前記トランジスタのコレクタ
を演鎧−増幅器の正入力に接続し、前記演３′ン増幅器
の負入力を宗霜１圧ダイオードを介してｔｉＪ、＄ｔに
接続し、きらに前記び算増幅器の負入力を第２の抵抗を
介して接地し、＋４’ｔｌ記肌（転）４増幅器の出力を
前記トランジスタのベースに接続してＫｔ’ｊ成される
。In order to achieve the above object, the bias circuit according to the present invention provides +1fJ in a transistor whose emitter is grounded.
The collector of the AZ transistor is connected to the first resistor through the first resistor, the collector of the transistor is further connected to the positive input of the amplifier, and the negative input of the amplifier is connected to the first resistor. tiJ and $t through a pressure diode, the negative input of the differential amplifier is grounded through a second resistor, and the output of the differential amplifier is connected to the base of the transistor. Kt'j is formed by connecting to.
第３図は本発明の一天施例を示す回路枯成図である。第
３図において、本発明の一実施例は、第２図にＡ＜シた
バイアス回路の抵抗比５を定電圧ダイオードＸ１に変７
えて構成される。即ち、参照符号ＴＲ３はトランジスタ
、ＩＣＺは演算増幅器、Ｘｌは定電圧ダイオード、几８
、Ｒ９は抵抗をそれぞれ示す。FIG. 3 is a circuit diagram showing an instant embodiment of the present invention. In FIG. 3, one embodiment of the present invention changes the resistance ratio 5 of the bias circuit, which is A
It is constructed by That is, reference symbol TR3 is a transistor, ICZ is an operational amplifier, Xl is a constant voltage diode, and 几8
, R9 represent resistances, respectively.
第３図に示すように構成して電源からの電圧を常に一定
にする事によって、抵抗比９にかかる電圧は一定になり
、トランジスタＴＲ３に流れる電流は電源電圧変動に対
しても変らない。By configuring as shown in FIG. 3 and keeping the voltage from the power supply constant, the voltage applied to the resistance ratio 9 becomes constant, and the current flowing through the transistor TR3 does not change even when the power supply voltage fluctuates.
本発明は以上のように構成され、本発明によれは、トラ
ンジスタの高周波特性も電源電圧変動に対し変らず、安
定した特性を有する増幅回路を作ることが出来る。The present invention is constructed as described above, and according to the present invention, the high frequency characteristics of the transistors do not change with respect to fluctuations in the power supply voltage, and it is possible to create an amplifier circuit having stable characteristics.
第１図は通常のバイアス回路の構成図、第２図は高周波
回路で用いらｎるエミッタ接地型バイアス回路の構成図
、第３図は本発明に係る筒周波回路のエミッタ接地型バ
イアス回路の一実施例を示す構成図である。
■も１〜Ｒ９，＠、抵抗器、Ｃ１−申−バイパスコンデ
ンツ“、ＴＲ１〜ＴＲ３ψΦ拳トランジスタ、■、ｃＪ
、ＩＣ２，、・演算増幅器、Ｘ１１１・・戻電圧ダイオ
ード
特許出願人 日本電気株式会社
代 理 人 弁理士 熊 谷 雄太部第１ 図
第２図
第３図
手続補正−（＋１発）
昭和５８年４月１１日
特許庁長官 若 杉 和 夫 殿
１ 事件の表示
昭第１ｊ５８年特許願第４５１３６＠
２ 発明の名称
バイアス回路
３ 補正をする者
事件との関係 特許出願人
住 所 東京都港１メ芝五Ｊ゛目３３ζ）１１号名 称
（４２３）日本正気株式会社
代表者 社長 関 本 忠 弘
４ 代 理 人
住 所 神奈川県用崎市多摩区宿河原１６３２柑地ダイ
アバ１／ス登戸第２４０７号
１ｊｌＪ 、￥ｉｌｊ岩の発明の詳細な説明の４１・）
す６ 補正の内容
■１本ノ５瓜明卸］１す第３０第１６イｊと同第１７行
の間に次の文意を挿入する
１次に本発明をその好徒しい一実施例につい１７一Fig. 1 is a block diagram of a normal bias circuit, Fig. 2 is a block diagram of a common emitter bias circuit used in a high frequency circuit, and Fig. 3 is a block diagram of a common emitter bias circuit for a cylindrical frequency circuit according to the present invention. FIG. 1 is a configuration diagram showing an example. ■Mo1~R9, @, resistor, C1-bypass capacitor, TR1~TR3ψΦ fist transistor, ■, cJ
, IC2,... Operational amplifier, X111... Return voltage diode Patent applicant NEC Corporation Agent Patent attorney Yutabe Kumagai 1 Figure 2 Figure 3 Procedure amendment - (+1 shot) April 1982 Kazuo Wakasugi, Commissioner of the Japan Patent Office, June 11th 1 Display of the case Patent application No. 45136 of 1972 5J ゛ 33 , ¥ilj Rock's Detailed Description of the Invention 41.)
6. Contents of the amendment ■ 1 book no. Nitsui 171
Claims (1)
ランジスタのコレクタを第１の抵抗を介して′電源に接
続し、さらに前記トランジスタのコレクタを演算増幅器
の正入力に接続し、前記演算増幅器の負入力を定電圧ダ
イオードを介して電源に接続し、さらに１１Ｊ記演算増
幅器の負入力を第２の抵抗を介して接地し、前記演算増
幅器の出力をＢｊＪ記トランジスタのベースに接続する
ことをｑ！ｆ６にとするバイアス回路。In a transistor whose emitter is grounded, the collector of the mtl transistor is connected to a power supply via a first resistor, the collector of the transistor is further connected to the positive input of an operational amplifier, and the negative input of the operational amplifier is connected to a constant voltage. q! is connected to the power supply via a diode, the negative input of the operational amplifier 11J is grounded through a second resistor, and the output of the operational amplifier is connected to the base of the transistor BjJ! Bias circuit for f6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58045136A JPS59171204A (en) | 1983-03-17 | 1983-03-17 | Bias circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58045136A JPS59171204A (en) | 1983-03-17 | 1983-03-17 | Bias circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59171204A true JPS59171204A (en) | 1984-09-27 |
Family
ID=12710859
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58045136A Pending JPS59171204A (en) | 1983-03-17 | 1983-03-17 | Bias circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59171204A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19604239A1 (en) * | 1995-02-08 | 1996-08-22 | Alps Electric Co Ltd | High frequency power amplifier for portable communication equipment |
| JP2008288817A (en) * | 2007-05-16 | 2008-11-27 | Nippon Telegr & Teleph Corp <Ntt> | Wide-band and low-noise amplifier |
-
1983
- 1983-03-17 JP JP58045136A patent/JPS59171204A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19604239A1 (en) * | 1995-02-08 | 1996-08-22 | Alps Electric Co Ltd | High frequency power amplifier for portable communication equipment |
| DE19604239C2 (en) * | 1995-02-08 | 2002-09-19 | Alps Electric Co Ltd | High-frequency transistor power amplifier |
| JP2008288817A (en) * | 2007-05-16 | 2008-11-27 | Nippon Telegr & Teleph Corp <Ntt> | Wide-band and low-noise amplifier |
| US8004363B2 (en) | 2007-05-16 | 2011-08-23 | Nippon Telegraph And Telephone Corporation | Wideband low-noise amplifier |
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