JPS5821926A - Interface circuit - Google Patents

Abstract

PURPOSE:To pervent the effect of a time delay caused by the working of a transistor, by actuating a transistor in an active region to control the working of another transistor that produces an output signal. CONSTITUTION:The collector voltage of a transistor TRQ2 is clamped by the emitter voltage of a TRQ5. The base voltage of the TRQ5 is set constant by the collector voltage VL of a TRQ6 of a constant voltage circuit 31. Thus it is always possible to actuate the TRQ2 in an active region by setting each resistance value of the resistances R3 and R4 at a prescribed value. As a result, a current I2 flows to the collector of the TRQ2 at a time point when an input signal P has a rise temporarily, and at the same time a current I1-I2 is supplied to the base of a TRQ4. Thus the voltage VO has a rise with no time delay, and an output signal OUT has a fall. The signal OUT has a rise with no time delay also when the signal P has a fall.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention particularly relates to an interface circuit that supplies a driving signal to a circuit that requires level conversion of an input signal from an external circuit.

Generally, when driving a circuit such as a logic circuit in response to an input signal from an external circuit, it is often necessary to convert the level of the input signal. For example, for a high-level input signal from a linear circuit, normally I"L (Int@grated-
The input voltage characteristics of logic circuits such as Inj@ctlon Logle) are at a low level. Such a signal level O
An interface circuit is required between different circuits, and various interface circuits have been considered in the past.The ojl1 diagram is an interface for driving a logic circuit such as I"L in accordance with an input signal P from an external circuit. Showing the configuration of the circuit 'C is 0, that is, between the power supplies Wee
9) A bipolar transistor (hereinafter simply referred to as a transistor) Qs-Qt is connected in series via a resistor Rr, and a power supply Ve is connected to the collector of the transistor Q1.
e is supplied, and a current 11 is generated in response to the input signal P supplied to that pace. Transistor Q again! teeth,
The construction ζ ivy is grounded, and the resistor Il! is connected to the power source v@c in parallel with the resistor B1. A diode-connected Niotsuta grounded transistor Q provided in series connection with
The collector of s is connected. Such a transistor Q
In the tmQs circuit (current current 2-circuit), the resistors R,
The current flowing through the meeting! Tomi is transistor Q! collector current I
= is equivalent to . Then, a common emitter transistor Q4 is provided, whose paste is connected to the connection point between the collector of the transistor Qt and the resistor RX, and an output signal OUT is generated from the collector of the transistor Q4. This output signal 0υT is supplied as an input signal to a circular circuit such as I"L, for example.

In such an interface circuit, the input signal P
is supplied to transistor Q1, the current ! 8 is resistance R
1 flows through transistor Q! supplied to This transistor Q! The collector current I'c! Since is the same value as the current 11, let us assume that the current! The least is the current! If the electric current mr Is −It J is larger than the transistor Q,
supplied as a pace current. Therefore transistor Q
4 is in the on state, the output signal OUT falls, and the signal r
OJ occurs. At this time, for example, a capacitance C is provided between the pace of the transistor Q4 and the ground, and when that capacitance CiC is charged with the current r II -x* J, the voltage between the pace and the emitter of the transistor Vl
1, a voltage vo is generated. This voltage v0 can be set to a lower level than the input signal P (assumed to be the same level as Vce), and level conversion has been performed.However, in such an interface circuit, the input signal When the signal P is supplied and the signal P rises, the operation of the transistor Q is in the saturation region, and the voltage V is the saturated collector-entrant voltage of the F transistor Q, vcmsat, (medium Ov)
It is in a state of The time required for the operation of this transistor Q to become an active region is 1. After the elapse of , the capacitance C is charged and the voltage V· rises. Therefore, the output signal OUT will fall after the elapse of time t1. Similarly, at the time when the input signal P falls, a current flows into the operating line active region of the transistor Q, that is, the collector! ! is flowing, so the voltage V is at a high level (the level of vmm of transistor q4), and after time t1 has elapsed, the voltage V
The operation enters the saturation region (VCmsatl-QV), the capacitance C is discharged, the voltage V falls, and therefore the output signal OUT rises. In this case, time t! is time t, less than 0 thus transistor Q! Accumulation time in operation (tl and 11)
Therefore, there is a disadvantage that a time delay occurs in the output signal OUT of the interface circuit with respect to the input signal PK, and this adverse effect becomes particularly large when the input signal P has a high frequency.

This invention was developed in view of the above circumstances, and it provides level conversion for an input signal by preventing the time delay effect caused by the operation of a transistor, and also generates an output signal that is synchronized with the input signal. The purpose is to provide an interface circuit that can

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows its configuration. In the same interface circuit as shown in FIG.
Transistor Q! controls the operation of transistor Q4 that occurs! A transistor Qs k is provided to supply an emitter current to the collector of the transistor Qs. The collector of this transistor Qs is supplied with a power supply Vec, and its pace is supplied with a constant voltage VL. Furthermore, this constant voltage vLt - the generated constant voltage A circuit 31 is provided, and this constant voltage circuit 3 includes a transistor Q1 whose emitter is common and a resistor R1 connected in series.
and 84 are provided in parallel. This transistor Q-
The common connection terminal of resistors a, , a, is connected to the base of n1
A power supply V@e is supplied to one terminal of the resistor R through a resistor Ri, and one terminal of the resistor R4 is grounded.

In the interface circuit configured in this manner, the collector voltage vcm of the transistor Q is clamped by the voltage across the transistor Qa. The base voltage Vm of this transistor Qs is set to a constant voltage by 1 to the collector voltage VL of the transistor Q of the constant voltage circuit 31. That is, the base voltage Vs of the transistor Q is, where Vlm, :)? The voltage between the base and the resistor R1 of the resistor Q6 is the resistance value of the resistor R, and the resistance value R4 is the resistance value of the resistor R4. Therefore, from the above formula (1), if the resistance values of resistors i and *R4 are set to a predetermined value, then K, and therefore transistor Q! Collector voltage VCI! is clamped to a predetermined value n, ie held above the saturation voltage vcmsat1, and the transistor Q! K always operates in the active region. In addition, each resistance value R of the resistor RIsR4
,,R, may be set so as to satisfy the following relational expression (2) t-. Here, Vlm is the base-emitter voltage of the transistor Q4 that generates the output signal OUT.

In this way, transistor Q () operates in the active region, so that when input signal P temporarily rises, transistor Q! A current I flows through the collector of the transistor Q4, and a current r It - It J is supplied to the base of the transistor Q4, so that the voltage We (V"4) is supplied to the base of the transistor Q4 without the time delay tl shown in FIG. rises, and therefore the output signal OUT falls.Similarly, when the input signal P falls, the capacitance C is connected to the transistor Q.
! voltage v0 without any time delay tl.
falls, and the output signal OUT rises. Therefore, the output signal OU'l''i can be generated in synchronization with the input signal PK.

Figure 4 shows an interface circuit for operating a large number of transistor tubes using the same human input signal PK.
1 are provided in parallel, and the transistor Qst-
At each base of all Qsn of Qsn, there is a transistor q8
The collector current of n0 and the transistor Qu
The emitter current flows from each of ~Qtn through a resistor (R1 or any resistance value) to that transistor Qa-Q*
0 supplied to the collector of n further generates an output signal;
Transistors Q41 to 941k whose base currents are controlled by the respective collector currents of transistors Qts to Qn
are provided in parallel. In the case of such a circuit, a multi-emitter type transistor Q, t- is provided in place of the transistor Q, and the emitter current of this transistor Qv is supplied to each collector of the transistors Qa to Qtn, so that the transistor Qmt ~Q! It is possible to clamp each collector voltage of n. The other components, operations, and effects of this interface circuit are shown in FIG. 3 and are the same as those in the above embodiment, are designated by the same reference numerals, and will not be described further.

Note that in the above embodiment, the constant voltage circuit 31 is not limited to this, and may have another circuit configuration, but it is necessary that it can be integrated into an IC together with the interface circuit. Also, the current supplied to the diode-connected transistor Qs! ,
The generation of the signal P may be controlled by an input signal, for example, a reverse phase signal of the input signal P.

As described in detail above, according to the present invention, it is possible to provide an interface circuit that can generate an output signal synchronized with an input signal by controlling the base current of a transistor that generates an output signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional interface circuit, FIG. 2 is a diagram showing its timing chart, FIG. 3 is a block diagram of an interface circuit according to an embodiment of the present invention, and FIG.
The figure is a block diagram of an interface circuit according to another embodiment of the present invention.
Qn ~ Qtll * Q41 ~ Q411・
... Bipolar transistor, B1 to R3... Resistor. Applicant Representative Patent Attorney Takehiko Suzue 11m 2nd! ll! f 111311FF Figure 4 Showa Me6.1j+ -” 8, Indication of the case Patent Application No. 120131/1982, Name of the invention Interface circuit, Person making the amendment Relationship with the case Patent applicant (3107) Tokyo Shibaura Electric Co., Ltd. '6 Agent, voluntary amendment 7, Contents of the amendment (1) The scope of claims in the specification is corrected on a separate sheet of paper. [Drawings 1 and 4 are corrected on a separate sheet of paper]. means for supplying a first current from a power supply to the collector of a first bipolar transistor with a common emitter in response to an input signal; means for generating a predetermined second current from the power supply; supplying a base current to the first bipolar transistor [7] means for making the collector current of the transistor equal to the second current; means for supplying the base of the second bipolar transistor with a common emitter for generating an output signal; and a third bipolar transistor whose collector is supplied with power and whose collector current is supplied to the collector of the first bipolar transistor in accordance with the base current. An interface circuit comprising a transistor and a constant voltage circuit that holds the base voltage of the third bipolar transistor constant, and clamps the collector voltage of the first bipolar transistor to a predetermined voltage.

Claims (1)

[Claims] The first electric current is output from the power supply in response to the input signal.
means for supplying a current to the collector of the tenth bipolar transistor that is grounded; means for generating a predetermined second current from the power supply; means for making the collector current equal to the second current; and supplying a current obtained by subtracting the collector current of the first bipolar transistor from the current *i to the second bipolar transistor grounded for output signal generation. means, a bipolar transistor of jI3 whose collector is supplied with power and whose collector current is supplied to the collector of the first bipolar transistor in accordance with the pace current, and a pace voltage of the ogno bipolar transistor kept constant; 1. An interface circuit comprising: a constant voltage circuit, and clamping the collector voltage of the second bipolar transistor to a predetermined voltage.