JPS5917097U - semiconductor memory cell - Google Patents
semiconductor memory cellInfo
- Publication number
- JPS5917097U JPS5917097U JP11100482U JP11100482U JPS5917097U JP S5917097 U JPS5917097 U JP S5917097U JP 11100482 U JP11100482 U JP 11100482U JP 11100482 U JP11100482 U JP 11100482U JP S5917097 U JPS5917097 U JP S5917097U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- double
- npn
- base
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Static Random-Access Memory (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来のＰＮＰＮ交差結合型メモリセルとその
周辺回路図、第２図は、ＰＮＰＮ交差結合型メモリセル
の書き込み時における各部の電圧、電 。
流を示した説明図、第３図は、本考案の一実施例の半導
体メモリセルとその周辺回路図、第４図は、従来のＰＮ
ＰＮ交差結合型メモリセルと本考案の半導体メモリセル
との書き込み時における比較図、第５図は本考案の一実
施例の断面図及び回路図である。
Ｔ１−Ｔ１２・・・トランジスタ、■１〜Ｉ４・・・定
電流源。FIG. 1 is a diagram of a conventional PNPN cross-coupled memory cell and its peripheral circuitry, and FIG. 2 shows voltages and currents at various parts during writing in the PNPN cross-coupled memory cell. 3 is a diagram showing a semiconductor memory cell according to an embodiment of the present invention and its peripheral circuit, and FIG. 4 is an explanatory diagram showing a conventional PN
A comparison diagram of a PN cross-coupled memory cell and a semiconductor memory cell of the present invention during writing, and FIG. 5 is a sectional view and a circuit diagram of an embodiment of the present invention. T1-T12...transistor, ■1-I4...constant current source.
Claims (1)
型ＮＰＮ トランジスタのコレクタに接続し、第１ＰＮ
Ｐ）ランジスタを第１の抵抗を介して、第１ダブルエミ
ツタ型ＮＰＮ ）ランジスタのベースに接続し、第２Ｐ
ＮＰ ）ランジスタのベースを第２ダブルエミツタ型Ｎ
ＰＮ ）ランジスタのコレクタに接続し、第２ＮＰＮ
）ランジスタのコレクタを第２の抵抗を介して、第２ダ
ブルエミツタ型ＮＰＮトランジスタのベースに接続し、
第１ダブルエミツタ型ＮＰＮ ）ランシタのコレクタを
第２ダブルエミツタ型ＮＰＮ ）ランジスタのベースに
接続し、第１ダブルエミツタ型ＮＰＮ ）ランジスタの
ベースを第２ダブルエミツタ型ＮＰＮ ）ランジスタの
コレクタに接続することにより１つの交差型メモリセル
を構成し、従来のＰＮＰＮ交差結合型メモリセルに比較
して、ＰＮＰトランジスタのコレクタに抵抗をもうけた
ことを特徴とする半導体メモリセル。The base of the first PNP transistor is connected to the collector of the first double emitter type NPN transistor, and
P) Connect the transistor to the base of the first double-emitter type NPN transistor through the first resistor, and connect the transistor to the base of the second P
NP) The base of the transistor is the second double emitter type N
PN ) connected to the collector of the transistor, and the second NPN
) Connecting the collector of the transistor to the base of the second double emitter type NPN transistor via the second resistor,
One crossover is achieved by connecting the collector of a first double-emitter NPN) transistor to the base of a second double-emitter NPN) transistor, and by connecting the base of the first double-emitter NPN) transistor to the collector of a second double-emitter NPN) transistor. What is claimed is: 1. A semiconductor memory cell comprising a PNP transistor type memory cell and having a resistor in the collector of a PNP transistor, compared to a conventional PNPN cross-coupled memory cell.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11100482U JPS5917097U (en) | 1982-07-23 | 1982-07-23 | semiconductor memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11100482U JPS5917097U (en) | 1982-07-23 | 1982-07-23 | semiconductor memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5917097U true JPS5917097U (en) | 1984-02-01 |
Family
ID=30257931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11100482U Pending JPS5917097U (en) | 1982-07-23 | 1982-07-23 | semiconductor memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5917097U (en) |
-
1982
- 1982-07-23 JP JP11100482U patent/JPS5917097U/en active Pending
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