JPS59170958A - Electronic calculator - Google Patents

Abstract

PURPOSE:To operate continuously even if an error is generated on the way of operation of a long calculation formula by clearing only an arithmetic register when data are included in saving registers. CONSTITUTION:When the contents of a formula 1+2X[3-4X(5divided by 0)] are inputted successively from an input part 10, 4XA, 3-B, 2XA, 1+B, 0, and 5divided by are stored in the saving registers 23, 33, the saving registers 24, 34, the saving registers 25, 35, the saving registers 26, 36, a register 21, and a register 22 respectively at the input of 0. When a right parenthesis key is depressed, 5divided by 0 is operated and an error is generated. Therefore, an AC all clear key is depressed, so that signals 105, 106 are outputted from an arithmetic control part 11 and data in the registers 21, 22 are cleared. On the other hand, data in the saving registers are not cleared and can be operated continuously.

Description

[Detailed description of the invention] The non-invention relates to electronic desk calculators.

With the recent advances in VC electronic technology, complicated calculations involving parentheses, etc., can now be calculated by prioritizing multiplication and division or ty) Rt nVC even with VC key operations 1~.
An electronic desktop calculator (calculator) using the so-called child-complete formula has been developed.

For example, when calculating 8-Bx (C+(D-E÷F)) with a total of 4 such draws, (1) -E1F) is given the highest priority, but among them, E-4-Fi First calculate and subtract x-r from the sieve. Furthermore, the result is added to all C, and the result is f
B Performs all VC multiplications and subtracts all results from kA.

As mentioned above, the order of calculation is determined automatically, and in that case, if the calculation order is slow, the data? It is necessary to save the data to a register other than the arithmetic register, but if the user of the computer performs an unreasonable operation or the result of the operation overflows, an error will occur. When these errors occur in the middle of a long calculation formula, it is inconvenient that all registers must be completely cleared using the clear key and the entire operation must be performed manually from the beginning.

In view of these points, the purpose of the present invention is to provide an electronic desktop calculator that, when an error occurs in the middle of a long calculation formula, clears all the calculation registers and continues the calculation. It is about providing.

The electronic desk calculator according to the present invention is an electronic desk calculator that performs calculations by sequentially processing a parenthesis calculation function and mixed calculations such as addition, subtraction, multiplication, and division.
In case c, only the arithmetic register is fully cleared and the entire contents of the data save register are protected (~, all features are that continuous computation is possible).

An embodiment of the invention is shown in FIG.

When a key is operated in the key manual section 10, a corresponding signal is transmitted to the arithmetic control section 11Vc.

When the multiplication key diagram and the division key field of the key human power unit 100 are operated, the full calculation control unit 11 determines that it is necessary to save the intermediate results, and the signal 101 (input VC transmission of the JR gate 14 and AND gate 72 In addition, when the left parenthesis key [C of the key input section 10 is operated, the signal 102 is sent from the arithmetic control section 11 to the OR gate 14 and A N I).
is transmitted to the input of gate 62.

Further, when the addition key date and subtraction key date of the key manual unit 10 are operated, the signal 103 is transmitted from the calculation control unit 11 to the input of the gate 15. Furthermore, when the LOCKY and LOCKY are operated, the calculation control The signal 104 from the section 11 is A, ND.
It is transmitted to the inputs of gates 63, 64, 65, and 66.

Further, when the A and C keys of the key human power section 10 are operated, a signal 105 is transmitted from the arithmetic control section 11 to the human power of the OR gate 15. The signal 106 is sent from the arithmetic control unit 11 to the register 3.
This is the calculation data transmitted to 1.

(The output of JR gate 14 is (JR gate 15 and AND
connected to the inputs of gates 53, 54, 55, 56, (J
The output of R gate 15 is connected to AND gate 52VC. They are called registers 221 and 31'kX registers,
The register 210 section mainly stores numerical data, and the register 310 section mainly stores arithmetic instructions and other data. Registers 22 and 32kY registers, registers 23 and 33 as save register M1, registers 24 and 34 as save register M2. Registers 25 and 35 save register M3. Registers 26 and 36r are called save registers M4, and the data storage method is the same as that of the X register. Operation instructions and other data are stored in the register 32.
A timing signal for storing only VC (hereinafter referred to as timing signal T) is connected to the inputs of AND gates 62 and 72, and an information signal Δ (hereinafter referred to as N
An information signal 11 (hereinafter referred to as B information) is connected to the input of the AND gate 720, and an information signal 11 (hereinafter referred to as B information) is connected to the input of the AND gate 62, indicating that all the data of the previous addition/subtraction is to be saved because the multiplication/division key has been operated. %AND gates 52, 62.
The outputs of 72 and 63 are connected to the input of OR gate 42, and the output thereof is connected to the input VC of register 32. The output of the register 21 is connected to the arithmetic control section 11 and A, the input of the ND gate 52, and the display section 12.
2 is connected to the arithmetic control section 11 and the input of AND gate 53, and the output of AND gate 53 is connected to (JR gate 4
The output of the OR gate 43 is connected to the input of the register 33, the output of the register 33 is connected to the input of the register 23 and the arithmetic control section 11, and the output of the register 23 is connected to the input of the AND gates 54 and 63. connected to AN
The output of the D gate 54 is connected to the input of the JR gate 440, and the output of the D gate 54 is connected to the input of the register 340.
The output of register 34 is connected to the input of register 24, the output of register 24 is connected to the inputs of gates 55 and 64, and the output U of AND gate 1-64 is connected to
The output of gate 55 (OI, connected to the input of gate 430, ANL) is connected to the input of JR gate 45, OR
The output of gate 45 is connected to the input VC of register 35,
The output of register 35 is connected to register 25, the output of register 25 is connected to the input VC of AND gates 56 and 65, and the output of gate 65 is 1dOR gate 4.
The output of AND gate 56 is connected to the input of register 36, the output of register 36 is connected to the input VC of register 26, and the output of register 26 is connected to the input of AN
It is connected to the input of D gate 66, and the output of AND gate 66 is connected to the input of OR gate 45.

Next, in the calculation example of 1+2X (3-4X (5+O)), we will focus on the movement of data in each register.
As shown in the figure. When the country numeric key of the key operator unit 10 is operated, the OVCVC equivalent signal 106 is output from the arithmetic control unit 11 and stored in the X register 21 (step 1).

Next, when the addition key is operated, the addition instruction is stored in the
The data in the X registers 21 and 31 is transferred to the X registers 22 and 32V via the 1% gate 42 (step 2).

When the next VCCJ numeric key is operated, data corresponding to the X register VC(2) is stored as in step 1 (step 3).

Next, when the ward multiplication key is operated, the signal 101 is output from the arithmetic control unit 11, and information B is stored in the X register via the AND gate 72 and the OR gate 42 in synchronization with the timing signal TVC. Gates 14 and 15
is operating, so the data in the X register is the AAND gate 52 and OR gate 42? The data in the X register is transferred to the X register via the AND gate 53 and (
It is transferred to the M Lujistar via the JR gate 43 (step 4).

When the next V old friend parenthesis key is operated, the signal 102 is output from the arithmetic control unit 11, and in synchronization with the timing signal T4ζ, the information Δ is stored in the register 32VC through the AND gate 62 and the OR gate 42 (-). JR Gate 14
operates, the data in the X registers 22 and 32 are transferred to the 23 and 33 V of the save register M1 via the AND gate 53 and the OR gate 43, and the data in the 23 and 33 voltages of M1 are transferred to the AND gate 54 and the OR gate 44? 24 and 3 of the save register M2. [This is transferred (Step 5).

Next VC (3) If you press all the numeric keys, you will get K as in step 1.
[3] Data corresponding to vc is stored in the X register (step, pro).

Next, when the day subtraction key is fully operated, the subtraction instruction is stored in the register 31 VC as in step 2, and at the same time the data in the X registers 21 and 31 is transferred to the X registers 22 and 32 VC (step 7).

Next VC (4) When the numeric key is operated, it is the same as Mechitsubu 3.
Data corresponding to ■ is stored in the FCX register 21 (step 8).

Next, when the multiplication key in the figure is operated, the operation is the same as in step 4, the data in the X register goes to Ml, and the data in Ml goes to M2.
%M2 data is transferred to M3 (step 9).

Next, when the 1°C left parenthesis key is operated, the arithmetic control unit 11 outputs the 1 port number 102, and operates in the same manner as in step 5.
The data in the X register goes to Ml, the data in Ml goes to M2,
The data in M2 is transferred to M3, and the data in M3 is transferred to M4 (step 10).

When the next V [51 numeric key is operated, data corresponding to VC+33 VC is stored in the X register C (step 11), as in step 3.

When the next VC division key is operated, the division instruction is sent to register 3.
14c is stored, the data in the vCX registers 21 and 31 is simultaneously transferred to the X registers 22 and 32V (step 12).

When the next VC number key is operated, the VC
Data corresponding to U@v is stored in the X register (
Step 13).

Next vc (53 When the right parenthesis key is operated, the data in the X register and the data in the X register are also retrieved.
The calculation is performed using 1, but in this calculation example, 5+O
When is calculated, an error 9 occurs due to an absurd operation (step 14).

Next, when the VcAO all clear key is operated, a signal 105 is output from the calculation control section 11. Clear data is sent from the signal 106 to the X register VC. Here, the data in the register 33 is sent to the arithmetic control unit 11 as a signal 107.
vC is transmitted. That is, im number 107 means that the stack register is in use. Then signal 107V
Signals 101, 102, 10 from C dependent V calculation control unit 11
3 is not sent. Therefore, the clear data U of the X register
, since OR gate 15 is operating, ANIJ gate 5
2 and the Y register VC is transferred via the OR gate 42. M3. The state of M4 remains unchanged (step 15).

As explained above, if an error occurs during the calculation of a VC or long GL formula, conventionally all registers must be cleared, and the take also has to be corrected from the beginning, which is an inconvenience. However, it is uninvented (
5. If there is a take in the % saving l/raster, the calculation can be continued by clearing only the calculation take, and the effect is tremendous.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a clear diagram of the data movement of the valley register when implementing the invention. lO... Key human power department, 11... Arithmetic control section %] 2.
...Display section, 14, 15, 42, 43, 44, 45
...OR gate, 52. 53. 54.
55. ! '56゜62.63,64,65,66.
72...ANL) gate, 21, 22, 23, 2
4, 25, 26° 31.32. '33, 34, 35.3
6...Register. Figure 1

Claims (1)

[Claims] In desktop electronic computers that have multiple data save registers and give priority to multiplication/division over addition/subtraction in parenthesis calculation functions and mixed calculations such as addition, subtraction, multiplication, etc., the digit save register is in use for temporary error clearing operation. in the case of,
Clear only the calculation register and save the above data register? VC and LC electronic desk calculator.