JPS59169178A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59169178A JPS59169178A JP4334083A JP4334083A JPS59169178A JP S59169178 A JPS59169178 A JP S59169178A JP 4334083 A JP4334083 A JP 4334083A JP 4334083 A JP4334083 A JP 4334083A JP S59169178 A JPS59169178 A JP S59169178A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode
- plate
- contact
- hole
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/492—Bases or plates or solder therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明はダ雑な形状のゲートを1lJii入た半導体装
置の成極構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a polarization structure for a semiconductor device including roughly shaped gates.
例乙は高速サイリスク素子の表面形状を表わす平面図を
第1図1こ示し、第2図には第1図のA−A拡大断面図
を示す。第1図、第2図ζこおいて、半導体基板1は主
表面に複雑な形状のゲート電極2とカソード電極3を備
えており、このような高速サイリスク素子が正常な動作
を維持するためlこ、ゲート電極2とカソード電極3(
!:が永続して電気的tこ短絡することがないよう両磁
極はそれぞれ分離して配置されるのが普通である。4は
第1段のゲート電極である。Example B shows a plan view showing the surface shape of a high-speed silice element in FIG. 1, and FIG. 2 shows an enlarged sectional view taken along the line A-A in FIG. 1 and 2, the semiconductor substrate 1 has a complex-shaped gate electrode 2 and cathode electrode 3 on its main surface. Here, the gate electrode 2 and the cathode electrode 3 (
! The two magnetic poles are usually arranged separately to prevent permanent electrical short-circuiting. 4 is a first stage gate electrode.
さらtここのカソード電極3の上Aこは第3図に示すご
々く、平滑な面をもった導電性金属の接触電極5が当接
される。ゲート′#M、極2とカソード電極3とが電気
的に短絡を生じない配置とする手段は、第2図または第
3図からゎ力)るが、例えばシリコン基板1の主表面が
凹凸面をもつよう多こ、薬品などを用いてエッチングカ
Ω工fこより段差を形成し、シリコン基板1の凹部にア
ルミ蒸着膜からなるゲート電極2とシリコン基板1の最
外表面に同じくアルミ蒸着膜からなるカソード電極3を
設けることにより行われる。このようにしてシリコンA
M1の主表面に設けた凹凸面の高低差により、ゲート電
極2は接触電極板5との間に空間絶縁部が生じ1ゲート
電極2は接触電極板5に当接しているカソードを極と電
気的絶縁状態が保たれでいるのである。Further, above the cathode electrode 3, as shown in FIG. 3, a contact electrode 5 made of a conductive metal and having a smooth surface is brought into contact. The means for arranging the gate '#M, pole 2 and cathode electrode 3 so that no electrical short circuit occurs is shown in FIG. 2 or 3. For example, if the main surface of the silicon substrate 1 is an uneven surface A step is formed by an etching process using a chemical or the like, and a gate electrode 2 made of an aluminum vapor-deposited film is formed in the recessed part of the silicon substrate 1, and a step made of an aluminum vapor-deposited film is also formed on the outermost surface of the silicon substrate 1. This is done by providing a cathode electrode 3 of In this way silicon A
Due to the difference in height of the uneven surface provided on the main surface of M1, a space insulation part is created between the gate electrode 2 and the contact electrode plate 5, and the gate electrode 2 connects the cathode that is in contact with the contact electrode plate 5 with the electrode. This means that a state of physical insulation is maintained.
しかしながらこのような構造をとっているために必然曲
番こ生する欠点はシリコン基板1の主表面±0.O1
上に形成される凹部の深さ寸法を0.02 +nm
に制御しなけれはならないという加工上の困難さを伴う
ことである。例えば加工されたシリコン基板1の主表面
の凹部の深さが規定寸法より浅すきた場合には、第4図
tこ示すようにゲート′颯極2にフォトマスクの相関の
悪さなどに起因して突起部6が生すると、この突起部6
が接触電極板5に接触してしまうことがあり、その結果
ゲート電標2とカソード1極3との電気的な短絡を招く
。また第5図に示したよう(こ、シリコン基数1の土表
面に設けた凹部に製造過程中(こ金属微粒子などの異物
7が混入した場合、この導電性をもった異物を介して、
ゲート電極2と接触電極&5が接触してゲート、カソー
ド両親極間(こ短絡を生ずる。However, due to this structure, the disadvantage is that a curved number inevitably occurs. The depth dimension of the recess formed on O1 is 0.02 + nm
This is accompanied by difficulties in processing as it has to be controlled. For example, if the depth of the recess on the main surface of the processed silicon substrate 1 is shallower than the specified dimension, this may be due to poor correlation between the gate electrode 2 and the photomask, as shown in Figure 4. When the protrusion 6 is formed, this protrusion 6
may come into contact with the contact electrode plate 5, resulting in an electrical short circuit between the gate electrode 2 and the cathode 1 pole 3. In addition, as shown in Figure 5, if foreign matter 7 such as metal particles gets mixed into the recesses formed on the surface of the silicon base 1 soil during the manufacturing process, the electrically conductive foreign matter will
Gate electrode 2 and contact electrode &5 come into contact, causing a short circuit between the gate and cathode parents.
本発明は、上述の欠点を除去して、半導体装置に設けら
れた二つ以上の電極が互に嵯気的な短絡を生ずることな
く、安定した作動状態を永続して保持てきるような電極
構造とする方法を提供することζこある。The present invention eliminates the above-mentioned drawbacks and provides an electrode that permanently maintains a stable operating state without causing any gaseous short circuit between two or more electrodes provided in a semiconductor device. This is to provide a method for creating a structure.
本発明は例えば高速サイリスタのゲート、カソード両親
極間の短絡を防止するために、ゲート電極に対向するイ
面所の接触奄$i板(こゲート電極よりやや太き輪tI
Sをもった貫通孔または溝のような逃げ部を設けること
により達成される。For example, in order to prevent a short circuit between the gate, cathode, and parent electrodes of a high-speed thyristor, the present invention provides a contact plate (a ring slightly thicker than the gate electrode) on the side facing the gate electrode.
This is achieved by providing a recess such as a through hole or groove with an S.
本発明の冥施91J iこ基づき説明する。 The explanation will be based on 91J of the present invention.
第6図は第2図〜第5図と同様2こ高速サイリスタの電
極44造を示す仏犬断同図であり、第2図〜第5図と同
一符号は同一名称をもつで表わしである。本発明では、
第5図(こおいで、ゲート成極2と接触m面板5とが面
接接乃虫するのを防ぐため、接触電極板5のゲー) 1
1と対向する個所(こ、ゲートH4極2よりやへ大さい
同じ輪郭の形状を有する貫通孔8を設けである。このよ
うにすればシリコン基板1の主表面に四部を設けてゲー
トtit極2を配@する心安なく、また接触電極板5と
して用いられるモリに−’デンなどの電気良導体の厚さ
は01〜0.5 mmであって、従来の欠点とされたシ
リコン基板lの主表面に設けた凹凸の高低差0.02十
〇・01間に比べて、はるかに大きいから、たとえゲー
ト電極(こ前述した第4図の突起6や第4図の異物7の
混入があったとしても、ゲート′域極2の厚さ寸法0.
02+mに対しで十分ζこ対応できる。すなわち、ゲー
ト電極2と接触′F1!極板5.が直接接触する状態は
起らないだけでなく、突起や異物が接79!It軍極板
5の貫通孔8を欠き抜けることもない。接触電極板5の
取付は貫通孔8を利用して、ゲート電極2の位置と合致
するようζこ確認しながら行うことができる。FIG. 6 is a cross-cut diagram showing the electrodes 44 of two high-speed thyristors, similar to FIGS. 2 to 5, and the same symbols as in FIGS. 2 to 5 are represented by the same names. . In the present invention,
Figure 5 (In order to prevent the gate polarization 2 and the contact electrode plate 5 from coming into contact with each other, the contact electrode plate 5 is gated) 1
A through hole 8 is provided at a portion opposite to the gate H4 pole 2 and has the same contour shape as that of the gate H4 pole. 2, and the thickness of the electrically conductive material used as the contact electrode plate 5 is 01 to 0.5 mm, which is the main problem of the silicon substrate l, which was considered a drawback of the conventional method. Since the difference in height of the unevenness provided on the surface is much larger than the height difference of 0.02 x 0.01, even if the gate electrode (the protrusion 6 in Fig. 4 mentioned above or the foreign matter 7 in Fig. 4 is mixed in) Even if the thickness of gate region pole 2 is 0.
02+m is enough to deal with ζ. That is, contact with the gate electrode 2 'F1! Pole plate 5. Not only will there be no direct contact, but there will also be contact between protrusions and foreign objects.79! The through hole 8 of the IT polar plate 5 will not be cut out. The contact electrode plate 5 can be attached using the through hole 8 while checking that it matches the position of the gate electrode 2.
第7図は第6図の変形例を示すものである。第7図が第
6図と異る点は、接触電極板5の厚さを十分厚くして貫
通孔8ではなく、ゲート電極2と同一輪郭の溝9を設け
たことである。この溝9は従来の半導体基板に設ける寸
法制御の困難な凹部の形成に比べて、力3Sはるかに容
易である。溝9の深さを01〜0.5備とすれば効果は
第6図の場合と同様である。し力)し接触′電極板5自
体の厚さは1〜3咽としである。例えば平型の高速サイ
リスクでは、ケースに収容された後に、はじめて接触電
極板5が加圧接触されるものであり、加圧接触板5は常
時拘束されていないから0.1〜0.5 m程度の厚さ
では取扱い中の回転を防止するために、補強板が心安で
あるか、1〜3輔とした第7図の厚さを有する接触成極
板5を用いるとさは、重量効果があって回転に対する袖
筒の役割も十分果すことができるので、接触電極板5の
回転防止処置を必挟としない。したがって当然のことな
がら部品点数が減るという二次的効果をもたらfo婢付
きの接触′電極板5は別に設けた図示しでない位置合わ
せ用の孔を用いて組立作業を行うことができる。FIG. 7 shows a modification of FIG. 6. The difference between FIG. 7 and FIG. 6 is that the thickness of the contact electrode plate 5 is made sufficiently thick and a groove 9 having the same outline as the gate electrode 2 is provided instead of a through hole 8. This groove 9 is much easier to form than the formation of a concave portion in a conventional semiconductor substrate, which is difficult to control in size. If the depth of the groove 9 is set to 0.01 to 0.5 mm, the effect is similar to that shown in FIG. The thickness of the contact electrode plate 5 itself is 1 to 3 mm. For example, in a flat type high-speed cylisk, the contact electrode plate 5 is pressed into contact for the first time after it is housed in a case, and the pressure contact plate 5 is not always restrained, so the distance is 0.1 to 0.5 m. If the contact polarization plate 5 has a thickness of 1 to 3 mm as shown in Figure 7, it is safe to use a reinforcing plate to prevent rotation during handling. Since the contact electrode plate 5 can sufficiently function as a sleeve against rotation, it is not necessary to take measures to prevent the contact electrode plate 5 from rotating. Naturally, therefore, a secondary effect is that the number of parts is reduced, and the contact electrode plate 5 can be assembled using a separately provided positioning hole (not shown).
以上説明したことく、本発明によれば、シリコン基板の
主表面に、極めて手数のかっ)る面倒な、しかも深さの
制御が困難な、四部を形成するための力a工が不要とな
り、接触電′極板に設けた貫通孔または溝は、ゲート電
極と接触胤極板との距離を十分大きくとれる配置とする
ことができるから、無作為な異物の混入など、予期し得
ない不利な状況があったとしても、ゲート電極とカソー
ド電極の電気的短絡力3艮期間にわたって発生しないこ
とは確実であり、本発明を用いた半導体装置は安定な運
転を就けるこ々ができる。なお不発明は高速サイリスク
についで説明したがトランジスタなどにも適用できるも
のである。As explained above, according to the present invention, there is no need for the extremely laborious and troublesome mechanical work to form the four parts on the main surface of the silicon substrate, and the depth is difficult to control. The through holes or grooves provided in the contact electrode plate can be arranged to provide a sufficiently large distance between the gate electrode and the contact electrode plate, so that unexpected disadvantages such as random foreign matter can be avoided. Even if such a situation were to occur, it is certain that an electrical short-circuit force between the gate electrode and the cathode electrode will not occur for three periods, and the semiconductor device using the present invention can be operated stably. Although the non-invention was explained in connection with high-speed silicon risk, it can also be applied to transistors and the like.
第1図は高速サイリスタの′成極構造を示す平面図、第
2図は同じく拡大断面図、第3図は接触電極を両人た断
面図、第4図、第5図は′成極の短絡状態を示した断面
図、第6図、第7図は本発明の電極を備えた断面図であ
る。
1:半導体lli、&、2:グート′g極、3:カソー
ド成極、5:接触電極、6:突起部、7:異物、8:貫
通孔、9:溝。
第1図
第2図
第3図
第4図
第5図
第6図
第7図Figure 1 is a plan view showing the polarization structure of a high-speed thyristor, Figure 2 is an enlarged sectional view, Figure 3 is a sectional view of both contact electrodes, and Figures 4 and 5 are the polarization structure of the high-speed thyristor. 6 and 7 are cross-sectional views showing the short-circuited state, and FIGS. 6 and 7 are cross-sectional views including the electrode of the present invention. 1: Semiconductor lli, &, 2: Gut'g pole, 3: Cathode polarization, 5: Contact electrode, 6: Projection, 7: Foreign matter, 8: Through hole, 9: Groove. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7
Claims (1)
1の電極層と、前記接触板(こは当接しない第2の電極
層とを備えた半導体装置において、前記第2の電極層と
対向する個所に、前記第2の電極層よりやや大きい輪郭
を有する逃げ部を設けた接5ilc極板が備えられてい
ることを特徴とする半導体装置。l) A semiconductor device comprising a first electrode layer that contacts the contact electrode plate on the main surface of the semiconductor substrate, and a second electrode layer that does not contact the contact plate; 1. A semiconductor device comprising a contact plate having a relief portion having a slightly larger outline than the second electrode layer at a location facing the second electrode layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4334083A JPS59169178A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4334083A JPS59169178A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS59169178A true JPS59169178A (en) | 1984-09-25 |
Family
ID=12661111
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4334083A Pending JPS59169178A (en) | 1983-03-16 | 1983-03-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59169178A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4939367B1 (en) * | 1970-12-31 | 1974-10-25 | ||
JPS5265667A (en) * | 1975-11-27 | 1977-05-31 | Mitsubishi Electric Corp | Semiconductor device |
-
1983
- 1983-03-16 JP JP4334083A patent/JPS59169178A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4939367B1 (en) * | 1970-12-31 | 1974-10-25 | ||
JPS5265667A (en) * | 1975-11-27 | 1977-05-31 | Mitsubishi Electric Corp | Semiconductor device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62224028A (en) | Manufacture of film for semiconductor technology and application of the film | |
JPS59169178A (en) | Semiconductor device | |
JPS587862A (en) | Bipolar transistor structure and method of producing same | |
JPS6286715A (en) | Manufacture of semiconductor device | |
JPH04343479A (en) | Variable capacitance diode | |
JPS6273711A (en) | Semiconductor device | |
JPS62140433A (en) | Manufacture of semiconductor device | |
JP3111489B2 (en) | Method of forming insulating film having inclined surface | |
JPH05182977A (en) | Manufacture of semiconductor device | |
JPS63181449A (en) | Semiconductor device | |
JPH02153532A (en) | Electrode wiring structure for semiconductor device | |
JPS603154A (en) | Amplifying gate type thyristor | |
JPS6077460A (en) | Manufacture of semiconductor device | |
JPS61208240A (en) | Manufacture of semiconductor device | |
JPH02143563A (en) | Thyristor | |
JPH0669092B2 (en) | Method of manufacturing gate turn-off thyristor | |
JPH0554704B2 (en) | ||
JPS60160125A (en) | Manufacture of semiconductor device | |
JPS61174638A (en) | Formation for electrode metal wiring pattern | |
JPH02222574A (en) | Semiconductor device | |
JPS60145612A (en) | Manufacture of semiconductor device | |
JPH01120027A (en) | Manufacture of semiconductor device | |
JPS6038873A (en) | Manufacture of semiconductor device | |
JPS5969930A (en) | Manufacture of semiconductor device | |
JPS6410649A (en) | Manufacture of semiconductor device |