JPS59168789A - Television receiver - Google Patents

Abstract

PURPOSE:To simplify circuit constitution by performing a color processing and a double scanning converting processing in the same synchronism system taking a color burst as a reference synchronism. CONSTITUTION:The video signal Si of the interlace system is applied to double scanning converting processing circuits 20, 23 and 24 after prescribed signal processing. Then, the signal Si is converted into video signal of the non-interlace system where a horizontal frequency is doubled. A PLL circuit 30 generates a master clock CLKM in synchronizing with a color burst obtained from the signal Si. Further, a digital processing section such as a color demodulating circuit 22, and converting circuits 20, 23 and 24 or the like takes this clock CLKM as the reference synchronism. Further, a pulse PWS deciding a write start phase to a memory constituting the converting circuits 20 , 23 and 24 is obtained by a PLL circuit 35 controlled by the clock CLKM. 39, 43 register 37, counter 38, coincidence circuit 44, counter control logical circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention provides an interlaced video signal,
This invention relates to a television receiver that displays non-interlaced images.

BACKGROUND TECHNOLOGY AND PROBLEMS Generally, in a screen display using an interlaced method, when the number of scanning lines is 525, one field is composed of 262.5 lines, and screen flicker is suppressed by transmitting this at 60 Hz. Also, to get the vertical resolution,
The next field is scanned with a shift of +scan line interval.

However, in this case, even though macroscopically the number of images is 60 per second, microscopically one scanning line lights up every 5 seconds, and the display period is 6 seconds. Therefore, when the point of interest moves to follow the movement of the image, the coarse scanning line structure of every other field becomes noticeable, degrading the image quality.

In order to reduce the roughness of the scanning line structure, a television receiver that performs double-speed scanning with twice the horizontal frequency has been proposed. In this case, the display period of each scanning line is set to one second, the roughness of the scanning line structure is reduced, and high image quality can be obtained.

In order to perform double-speed scanning in which this horizontal frequency is doubled,
The interlaced video signal is converted into a non-interlaced video signal with twice the horizontal frequency and supplied to the picture tube, where non-interlaced display is performed.

It is desirable that such conversion processing, t and b times scanning conversion processing, be performed using the same reference synchronization system as other signal processing processes, such as luminance signal/chrominance signal separation and color tone processing. That is, since the color processing uses the color burst as the reference synchronization, it is consistent in terms of system configuration, and it is simple and inexpensive to process the double scanning conversion processing using this as the reference synchronization.

However, in conventional double scanning conversion processing, the horizontal synchronization signal is used as the reference synchronization. Therefore, in the conventional system, color processing uses a color burst as a reference synchronization, and double scanning conversion processing uses a horizontal synchronization signal as a reference synchronization, and two types of synchronization systems are required.

In a color video signal, three types of synchronization information, namely a color burst, a horizontal synchronization signal, and a vertical synchronization signal, and frequency are guaranteed with high accuracy. This is because if the force 2-burst is not correct, the hue will change and correct color reproduction will not be possible. On the other hand, the horizontal and vertical synchronization signals are not strictly subject to color bursts. Considering color processing in this way, the color burst should be synchronized with the reference.

In contrast to color processing, double scanning conversion processing is processing for converting the horizontal scanning line structure, and since it is processing for changing the method of assembling an image, it should be based on the horizontal synchronization signal.

FIG. 1 shows a principle circuit diagram for performing double scanning conversion processing.

In the figure, (1) and (2) are line memories, respectively.
(3) and (4) are respective changeover switches. The changeover switches (3) and (4) change their states every IH (one horizontal period), and when the changeover switch (3) is switched to one side of the memories (1) and (2), the changeover switch (
4) is switched to the other side. The interlaced video signal Si supplied to the input terminal (5) is stored in the memory (
Writing is performed alternately in memory 1) and memory (2) for each IH, and data is written to memory 1) and memory (2) from the other memory (2) and memory (1) to the IH written in memory (1) and memory (2). The IH portion of the video signal written to the previous IH is read out twice in succession. Therefore, in this case, the output terminal (6) is supplied with a video signal of each scanning line of the image signal 8i, or a non-interlaced video signal with twice the horizontal frequency that is repeated twice with a period of H. SNI is obtained.

Here, the writing start phase to the memories (1) and (2) must come in the horizontal retrace section of the video signal Si (shown in FIG. 2B) as indicated by the arrow in FIG. 2A.

At this time, the video signal 8NI becomes as shown in FIG.
Good non-interlaced display. On the other hand,
As shown in FIG. 3A, when the start phase of writing to memories (1) and (2) reaches the video interval of the video signal Si (shown in FIG. 3B), the video signal 8NI becomes As shown in the figure, a step difference appears on both the left and right sides of the displayed image, making it unsightly.

By the way, in the color video signal of the NTSC system, the color subcarrier frequency fsc and the horizontal frequency fb are related as shown in the following equation.

455 ・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・(1) fsc=-Tf
h and 4 as the sampling frequency for digitization.
fsc is often used, and in this case, the number of pixels in one scanning line is 910.

As mentioned above, the instantaneous frequency (IH length) of the horizontal synchronization signal is not strict even at the broadcasting station itself, and furthermore, if a home VTR (video tape recorder) is used, for example, this will be further exacerbated by jitter, etc. Ru. Due to these circumstances, when strict color burst is used as the reference synchronization, it becomes difficult to determine where to start writing into the memories (1) and (2).

That is, if the writing start phase is determined simply by horizontal synchronization of the input video signal Si, then the instantaneous frequency (LH length)
Since the number of pixels is changing, the definition of (1) that a scanning line has 910 pixels no longer holds true, causing an excess or shortage of memory and disrupting the synchronization of reproduced images. Therefore, conventionally, in double scanning conversion processing, a horizontal synchronization signal is used as a reference synchronization.

That is, as shown in FIG. 4, the IH time is always divided into 910 equal parts to create a reference master clock. In the figure, a video signal S is supplied to the terminal (8), and the synchronization signal is separated there.The separated synchronization signal is then transmitted to the horizontal synchronization separation circuit ( 9) to obtain a horizontal synchronizing signal 1 (sync), which is supplied to the phase comparator α0. Also, aυ is approximately 8 f
This shows a voltage-controlled variable frequency oscillator that obtains an oscillation signal with a frequency of sc, and the oscillation signal from this is phase-compared via a frequency divider a2) whose frequency division ratio is responsible, and a frequency divider 0th floor whose frequency division ratio is cloth. vessel(
10), and the phase is compared with the horizontal synchronization signal H5sync. The comparison error signal is then supplied as a control voltage to the oscillator aυ via the low-gust filter 04). Therefore, each of the oscillator (11) and frequency divider (12) outputs 8 fs synchronized with the horizontal synchronization signal I (sync).
c and 4 fSC frequency read clock CLKR
and write clock CLKw are obtained. The write start signal Pws is obtained from the frequency divider a□□□. Further, a5) is a 455-decimal counter, and a double-speed horizontal synchronizing signal Hsync2 is obtained from this counter αω.

In the method shown in Fig. 4, the IH is correct at every instant.
Although synchronization with 10 pixels can be achieved, color processing cannot be performed with this synchronization system.

Therefore, in addition to this synchronization system, a synchronization system that uses color burst as a reference synchronization as described above is necessary for color processing.

In this way, in the conventional system, color processing uses the color burst as the reference synchronization, and double scanning conversion processing uses the horizontal synchronization signal as the reference synchronization. Two types of synchronization systems are required, and the entire process including color processing is performed using the horizontal synchronization signal as the reference synchronization. When considering a digital processing system, it would be extremely complex.

Incidentally, it is also possible to perform color processing digitally, then convert it back to analog, and then digitize it again using a clock system based on the horizontal synchronization signal and perform double scanning conversion processing. However, in order to convert to analog during processing, I)
- An A converter, an A-D converter for re-digitizing, and a new lock circuit for double scanning conversion processing are required, which are expensive.

OBJECTS OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and it is an object of the present invention to enable color processing and double scanning conversion processing to be processed in the same synchronous system, thereby achieving a simple and inexpensive configuration.

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a method in which an interlaced color video signal is supplied to a double scanning conversion processing circuit.
In a television receiver in which the horizontal frequency is converted to a non-interlaced video signal with twice the horizontal frequency and a non-interlaced display is performed, a first clock is used to generate a master clock synchronized with the color burst obtained from the color video signal. and a 20th PLL circuit that generates a signal for controlling the write start phase of the memory constituting the processing circuit based on the master clock, and a 20th PLL circuit that generates a signal for controlling the write start phase of the memory constituting the processing circuit as a horizontal synchronization signal. A horizontal synchronizing signal separated from a non-interlaced video signal is used.

Since the present invention is constructed in this way and processes only in a synchronization system using color burst as the reference synchronization, the circuit construction is simple and can be constructed at low cost.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

In the figure, a6) is a long terminal to which an interlaced video signal Si (illustrated in FIG. 6, AK) is supplied. After this video signal Si is converted into a digital signal by an A-D converter (17), the luminance signal/chrominance signal separation circuit a81
supplied to The luminance signal Y separated by this separation circuit (18) is sent to a double scanning conversion circuit through a signal processing circuit aCj.
supplied to In the signal processing circuit (LL3, aperture correction etc. are performed. In addition, the double scanning conversion circuit (LL3)
01 is configured, for example, as shown in FIG. can get. This luminance signal Y' is then supplied to the matrix circuit (2]).

Further, the color signal C from the separation circuit (1110) is supplied to the color demodulation circuit IT2.Then, a red difference signal aY and a blue difference signal B-Y are obtained from this color demodulation circuit, and are converted into double scanning signals. The double scanning conversion circuits (2) and (2) are also configured, for example, as shown in FIG. The red difference signal (R-Y)' and the blue difference signal (B-Y)', which are continuous twice with a period of H, are obtained and are supplied to the matrix circuit (2). be done.

From the matrix circuit r2), the red, green, and blue primary color signals of each scanning line are obtained as red, green, and blue primary color signals R', G', and B' that are consecutive twice with a period of H, respectively. These signals R,', G' and B' are respectively]
]-A converter (25R), (25G) and (25B
) of the picture tube (not shown), red, green, and
Supplied to the cathode related to blue color.

Further, the luminance signal Y' is supplied to the synchronization separation circuit (26), and the multi-horizontal synchronization signals H, ync2. (shown in FIG. 6F) is obtained. This horizontal synchronizing signal H3ync2 has twice the normal frequency, and in the picture tube,
Based on this, horizontal deflection is performed.

Further, the video signal Si is supplied to a synchronization separation circuit (27), and a synchronization signal (shown in FIG. 6B) is separated. The separated synchronization signal is then supplied to a vertical synchronization separation circuit f28), thereby obtaining a vertical synchronization signal VS'/nC.

In the picture tube, vertical deflection is performed on this basis.

In the end, the picture tube receives signals R', G' and B',
Non-interlaced display with twice the horizontal frequency is performed.

Color demodulation circuit (2 x 1 scan conversion circuit (2o), (2
The digital processing portions such as 31 and 04J are processed using a master clock CLKM obtained using the color burst obtained from the video signal Si as a reference synchronization.

That is, the video signal Si is supplied to the burst gate circuit C, and the synchronization signal is supplied from the synchronization separation circuit (5) to the r-) circuit (29). And this gate circuit (29) packs the horizontal synchronization signal? The color burst (frequency is fSC) superimposed on -ch is darted, and this is supplied to a phase comparator (31) constituting a PLL circuit (to). In addition, the (3) is a voltage-controlled variable frequency oscillator that oscillates a signal with a frequency of approximately 8 fSc.

The oscillation signal from this is supplied to a frequency divider (after being frequency-divided by +j in (2), the phase comparator c3). The comparison error signal from the phase comparator (3υ) is supplied as a control voltage to the oscillator (32) via a low-gust filter (b).

Therefore, the oscillator 02 is synchronized with p color gust.
A signal having a frequency of fSC is obtained, and this is taken as the master clock CLKM.

By the way, if double scanning conversion processing is to be performed based on the master clocks CL and KM synchronized with this color burst, the double scanning conversion circuit (2 series (23)
, (It becomes difficult to determine where to start writing to the memory that constitutes 241. If the writing start phase is simply determined by horizontal synchronization of the input video signal Si, the instantaneous frequency (length of IH) will change. Therefore, the definition that one scanning line consists of 910 pixels no longer holds true, and the synchronization of reproduced images is disrupted due to excess or shortage of memory.

Therefore, in this example, the pulse that determines the write start phase, that is, the write start pulse Pws, is controlled by a digital PLL circuit (
38I, and the above-mentioned disadvantages do not occur.

In the figure, the master clock CL KM is supplied to a flip-flop (36), and this flip-flop (
A signal with a frequency of 4 fsc is obtained.

This is then supplied as the K clock signal to the N-ary counter (37) forming the digital PLL circuit (351).

This N-ary counter C3η is a 910-ary counter that normally counts from "0" to r909j as shown in FIG. It is said that This counter G
The output of F is supplied to the coincidence detection circuit (2) and also to the register 09. Register G1 has a synchronous separation circuit (5
) (horizontal synchronization signal Hsync)
(shown in FIG. 7B) is provided as a clock signal. The output of the counter (37) is written into this register (31) at the timing of supplying the synchronization signal as shown in FIG.
). In addition, a subtracter (4G has a terminal (4υ to target value, e.g. r 4ss J (shown in the seventh diagram)
is given. Subtractor (subtraction output from 4G en (7th
(shown in FIG. E) is fed to an adder 43 forming an accumulator. The addition output from the adder (42) is determined by the register (43).
supplied to In this register, 43 is a synchronization signal (7th
(shown in FIG. This cumulative value (shown in Figure 7F) is written to the register (register 13) where the subtracted output en from the subtractor is accumulated sequentially depending on the clause. signal vsy
nc is supplied as a clear signal. Therefore, immediately before the register '431K is cleared, the cumulative value of the deviation from the target value per field (field cumulative value) is written. Then, from this value, the average error from the target value of the synchronization signal can be determined.

The output of this register C43 is the counter control logic circuit (
44). A vertical synchronization signal vsync is supplied to this logic circuit (44) as a timing signal.

This logic circuit (4(a)) knows the above-mentioned field cumulative value using the vertical synchronization signal vsync, and controls the N-ary counter (37) based on this field cumulative value. That is, this logic circuit f44) With the characteristics shown in FIG. 8, "N" of the N-ary counter C37) is controlled only once.

For example, if the field cumulative value is -300 (the phase is delayed), as shown in FIG. and then again to 9
Make it a decimal counter. By doing this, the phase can be advanced. Also, the field cumulative value is +2
00 (the phase is leading), Fig. 9B
rNJ of the N-ary counter C37) as shown in
10 J, and when it counts up to 1109, it returns to 0, and after that it becomes a 910 decimal counter again. By doing so, the phase can be delayed.

The flowchart shown in FIG. 10 is based on this digital PLL.
This shows the operation of the circuit (39).

Further, in the digital PLL circuit C35), the target value r 455 J from the terminal (current) is supplied to the coincidence detection circuit 1.

From this example of the coincidence detection circuit, an N-ary counter (37
When the output of ) becomes the same as the target value r 455 J, a pulse is obtained, which is the double scanning conversion circuit (20), (c)
Start filling the memory that constitutes and (to) ・Gurus P
ws (illustrated in Figure 6C). and,
This write start pulse Pws determines the write start phase as shown by the arrow in Figure 6.

In this way, according to this example, when writing starts and gurus pws
is output every time 910 clocks are counted in one field, so the double scanning conversion circuit (201,
There is no excess or shortage of memory constituting (23) and (to), and synchronization is not disrupted. In addition, the vertical synchronization signal vsyn
Since the double scanning conversion output is phase-shifted every time c is supplied,
Due to excess or insufficient memory, the signal after the double scanning conversion process will not be the desired signal, but since this is a vertical gray ranking period, it will not affect the screen. Horizontal synchronization also causes a phase jump at this time, but by making the AFC time constant faster, it can be brought in before the vertical blanking period ends, and stable synchronization can be achieved within the three effective surfaces. can be obtained. Further, the phase of the write start pulse Pws is controlled by a synchronization signal obtained from the synchronization separation circuit (27), that is, a horizontal synchronization signal,
The phase is controlled so that it is in the vicinity of the horizontal synchronizing signal, that is, within the horizontal blanking period.

Therefore, the image displayed on the screen will not have a difference in level on both the left and right sides, making it unsightly. Furthermore, the horizontal synchronization signal Hs
Since ync2 is obtained from the signal after double scanning conversion processing,
Even if the output is phased every time the vertical synchronizing signal VSynC is supplied, horizontal deflection scanning corresponding to the signal can be reliably performed.

After all, according to this example, color processing and double scanning conversion processing are processed in the same synchronization system with color burst as the reference synchronization, so the circuit configuration is simple and can be constructed at low cost. .

Incidentally, the digital PLL circuit (3!9) can have a configuration in which the subtracter (4G) is omitted separately from the above-mentioned embodiment. That is, the cumulative value of the reno star is written to the register r4.

Since the cumulative value of the target value is known in advance, the register (43
Since the accumulation of errors can be determined from the contents of , the logic circuit (4a) can be designed with this in mind. It is also possible to have a characteristic that does not shift the phase near the center.Also, if the field cumulative value is very large, the register that makes up the accumulator (the number of bits of Since this becomes complicated, it is also possible to saturate the accumulator output.

Furthermore, the digital PLL circuit 0 can be configured using a microcomputer so as to operate according to the flowchart shown in FIG. 10, and in this case, the hardware configuration is further simplified.

Well, in the above embodiment, luminance signal/chrominance signal separation →
Although the processing is performed in the order of luminance signal Y processing, color demodulation→double scanning conversion processing→color matrix, the processing order does not have to be in this order. Furthermore, although the double scanning conversion processing is performed on the luminance signal Y and the color difference signals B-Y and RY, it may be performed on the video signal Si, or after it is converted into a primary color signal.

Effects of the Invention According to the present invention described above, since processing is performed only in a synchronization system using color burst as reference synchronization, the circuit configuration can be simplified and can be constructed at low cost.

[Brief explanation of the drawing]

Figure 1 is a principle diagram of a double-scanning conversion circuit, Figures 2 and 3 are diagrams for explaining the same, Figure 4 is a circuit diagram of the synchronous system of a conventional double-scanning conversion circuit, and Figure 5 is a diagram of a conventional double-scanning conversion circuit. FIGS. 6 to 11 are diagrams showing one embodiment of the invention, and are diagrams for explaining the example in FIG. 5, respectively. (2), (23) and (24 are double scanning conversion circuits, (2 are color demodulation circuits, (to) are PLL circuits, and (3!9 are digital PLL circuits.) Figure 7F
(Σen)-2(Σ-es)-2+0
(4!n)-2+0-fFigure 6Figure 8Figure 11Figure 9U
θ υFigure 10

Claims (1)

[Claims] In a television receiver in which an interlaced color video signal is supplied to a double-scan conversion processing circuit and converted into a non-interlaced video signal with double the horizontal frequency, a non-interlaced display is performed.
a first PLL circuit that generates a reliable star clock synchronized with the color burst obtained from the color video signal;
A second PLL circuit generates a signal for controlling the write start phase of the memory constituting the processing circuit based on the master clock, and the horizontal synchronization signal is generated by the non-interlace method obtained from the processing circuit. A television receiver characterized in that a horizontal synchronizing signal separated from a video signal is used.