JPS59167734A - Direct memory access control system - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of the whole of a system by providing read cycles in the beginning and the last of a memory cycle and using the other part of the memory cycle as a write cycle in case of data transfer to shorten the memory cycle. CONSTITUTION:In case of data transfer from a memory 10 to a memory 22, a direct memory access control circuit 11 reads out data from the memory 22 to data registers 13-16 with word addresses, which are indicated by address registers 17-19, by the control of a microprocessor 12. Data is written from the memory onto this data. Data of data registers 13-16 in this state is written on the memory 22 with word addresses which are read out again. When data is written from the memory 10 on data registers 13-16, data is written on the memory 22 with word addresses counted up by +1; and this operation is repeated.

Description

Detailed Description of the Invention (a) Technical Field of the Invention The present invention relates to a data processing device that transfers data in a direct memory access mode between areas with different data widths, and particularly relates to a data processing device that transfers data between areas with different data widths in a direct memory access mode, and in particular, converts memory cycles into write/read cycles. This invention relates to a direct memory access 4Ii control method that improves data transfer efficiency by shortening the length of the memory.

(b) Conventional technology and problems When transferring data in direct memory access mode between areas with different data widths, two-word boundaries (addresses within the storage area specified as integral multiples of the word length) It is not necessarily transferred; read, modify, write,
Is there a method using a cycle method or has it been proposed?
In a data processing device with a fixed memory cycle length, one memory cycle becomes long. That is, an extra memory cycle is required for the modification time, which has the drawback of poor efficiency.

(c) Purpose of the Invention The purpose of the present invention is to eliminate the above drawbacks when transferring data by direct memory access.

A read cycle is provided at the beginning and end of the memory cycle,
Another object of the present invention is to provide a direct memory access control method that improves the overall transfer efficiency by shortening the memory cycle as only a write cycle.

(d) Structure of the Invention The structure of the present invention is that in a data processing device that transfers data between storage means with different data widths using a direct memory access mode, data is stored in the storage means with a larger data width. In this case, a read cycle for reading data from the storage means having a large data width is added to the first and last write cycles of the memory cycle for storing the data.

(e) Embodiments of the Invention When data is transferred between areas with different data widths in die reflex h memory access mode, if the addresses are continuous, except at the start and end of the transfer, the rest will be word boundaries. It is possible to transfer by.

For example, a case will be explained in which 1 byte of data is transferred to a memory of 4 bytes and 1 word. Figure 1 shows 17 at word addresses "01" to "'05" of 4-hyde 1-word memory.
An example of transferring height data is shown below. As shown in FIG. 1, the word address "01" starts from the high L-position "2", and the word addresses ", 02", "03",
“04” is 4 consecutive hides, word address “05”
If you want to transfer data that ends at hide position "2" in °°.

Data at word addresses “02” to “04” can be transferred at word boundaries. Therefore, word addresses “01” 1 “05”
By making it possible to transfer data in word units, all data can be transferred at word boundaries. Normally, in a circuit that mainly uses direct memory access transfer, the amount of data that can be transferred at a two-word boundary is large, as shown in the example above, and the
The frequency at which data must be transferred is only at the start and end of the transfer, and the frequency at which it is required is relatively low. Accordingly, the present invention allows all tenitor transfers to be performed at word boundaries.

FIG. 2 is a block diagram of a circuit showing one embodiment of the present invention. Memory 10 is a memory with a 1-hide configuration and is a direct memory.
Under the control of the memory access control circuit 11, data is written/output in data registers 13.1'4 to 15.16. The data register 13.14. is, 16 is more writable/readable than memory 22, but memory I
The registers written by O are masked and stored in the memory 22.
It cannot be set from the side, and is reset when the memory 22 reads the data. Memory 22 is 4 Hyde l
It has a word configuration, and therefore four sets of data registers are provided. The microprocessor 12 sets the address at which the data is to be written into the memory 22 in address registers 17 and 18.
．． Seven throats at 19.

At this time, one word of the memory 22 is 4 hides.

The lower two bits of the address register 19 are assigned as the address indicating the hide position, and the seven so[
do. For example, when representing an address with 24 bits, j8 bits are set in each of the data registers 17 and 18, and 6 bits are set in the address register 19. The address registers 17 to 19 have an increment 1 function, and when the access to the memory 22 is completed, the address for the memory 22 is incremented by 1.

2 pins 1- of the hide register are recoded by the decoder 21 and sent to the data registers 13-16.

Cheetare 2 register 1 specified by the address
3 to 16 are respectively enabled and data sent from the memory 10 is sent. Each data register 13~
16 to 7) 1- Hyde unit data is stored in the memory 22.
It is stored at the address for each corresponding hide on the side. Therefore, except for the lower two bits of the address in memory 22, the addresses written to address registers 17-19 are in word units. For example, addresses such as one-to-one addresses "01" to "'05" in FIG. 1 are shown.

The hide register 20 also has an increment function, and as the first data is sent from the memory 10 to the data registers 13-16, the addresses of the data registers 13-16 are incremented by one. That is, if the data register 13 is instructed to V when the address is "00", the address is "" 0.
1”, the data register 14 is set to address “1o”.
When the address is 11'', the data register 15 is specified, and when the address is 11'', the data register 16 is specified.This also does not specify the hide address on the memory 22 side.
The hide position "o" shown in the figure is the data in the data register 13, the hide position "1" is the data in the data register 14, the hide position "2 is the take of the data register]5, the byte position "3' is ” stores the data of the data register 16, respectively.

When data is transferred from memory 10 to memory 22 in direct memory access mode.

Under the control of the microprocessor 12, the
-Memory access control circuit 11 is data register I3
~1G and address registers 17-19; 1ilJ? a
lLL7. )-E-1) 22yo"+7 +X' Send data δ to registers 13 to 16 at the word address indicated by reply registers 17 to 19.
3 to 16 (Write data from the memory 10 to the successively output data. By doing this, the data in the memory 10 is superimposed on the data in the memory 22 and written in the take registers 13 to 16. The word I address “” shown in Figure 1
If the data of ``01'' is written from 1 to 10, the data in the memory 22 will remain in hide positions ``0'' and ``1'', and the data in hide positions ``2'' and ``3'' will be rewritten. and becomes the data in the memory 10. The data in the data registers 13 to 16 in the above state is written into the memory 22 at the read word address again. By doing this, it becomes the same as writing data in hide locations "'2" and "3" in the memory 22 in hide units.At this time, the addresses of address registers 17 to 19 are incremented by 1.Next, the data When data is written from the memory 10 to the register registers 13 to 16, the data is written to the memory 22 using the word address incremented by 1, and the addresses of the address registers 17 to 9 are incremented by -1. When a state is reached in which data at word address "05" in FIG. 1 is written by repeating 1, for example, the memory 22 becomes a read cycle.

Data is read from the memory 22 into the data registers 13-16 according to the word address at that time.

At this time, data in take registers 13 to 15 corresponding to hide positions "0 to 3" are masked.

It is not affected by data writing from the memory 22 either. Therefore, data in the memory 22 is written only to the take register 16 corresponding to byte position "3". In the above state, the data in the data registers 13 to I6 is written to the read word address of the memory 22. This is the hide position.”
This is the same as writing data in Hyde units to ``0'', ``1'', and ``2''.In order to operate as explained above, the memory 22 has 1 address registers 17 to 19.
It is possible to transfer takes by performing write/read cycles using only the c6 word address.

(f) As described in the detailed description of the invention, the present invention is capable of shortening the memory cycle of the memory, which is an increase compared to adding read cycles at the start and end of transfer of infrequent direct memory access. Time is short,
In particular, the larger the area of data transferred by direct memory access, the greater the effect.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of transferring 17-height data to word addresses 01 to 05 of a 4-hide, 1-word memory, and FIG. 2 is a block diagram of a circuit showing an embodiment of the present invention. be. 10. 22 is a memory, 11 is a direct memory access control circuit, 12 is a microprocessor, 13, 14
, 15.16 are take registers. 17, 18, and 19 are address registers, 20 is a hide register, and 21 is a decoder.

Claims (1)

[Claims] Direct data transfer between storage methods with different data widths
In a data processing device that transfers data using memory access mode I, when storing data in a storage means with a large data width, the data width is Big notes 1.
A direct memory access control system characterized by adding a successive cycle for reading data from means a.