JPS59165447A - Integrated circuit - Google Patents

Integrated circuit

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Publication number
JPS59165447A
JPS59165447A JP58039017A JP3901783A JPS59165447A JP S59165447 A JPS59165447 A JP S59165447A JP 58039017 A JP58039017 A JP 58039017A JP 3901783 A JP3901783 A JP 3901783A JP S59165447 A JPS59165447 A JP S59165447A
Authority
JP
Japan
Prior art keywords
silicon carbide
thick film
carbide ceramic
integrated circuit
glass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58039017A
Other languages
Japanese (ja)
Inventor
Norihiko Okochi
大河内 敬彦
Nobuyuki Sugishita
杉下 信行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58039017A priority Critical patent/JPS59165447A/en
Publication of JPS59165447A publication Critical patent/JPS59165447A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To obtain the integrated circuit comprising the thick-film resistor without a blister on surface of the substrate of insulating silicon carbide ceramic by using the conductive substance which is non-reactive to the silicon carbide ceramic and the material consisting of non-reducable glass as the materials of the thick-film resistor. CONSTITUTION:A thick-film resistor 3 consisting of the conductive substance which is non-reactive to the silicon carbide ceramic and the non-reducable glass is formed on surface of the insulating silicon carbide ceramic substrate 1. The components of this non-reducable glass comprise Gibbs' standard-producing free energy in 900 deg.C of about 49kcal/mol or less for each metal oxide in the molecule. The above conductive substance preferably consists of one or more of LaB6, MoB, YB6, CaB6, BaB6, Ta2O5 and In2O3 and the non-reducable glass preferably consists of one or more of CaO, ThO2, BeO, La2O3, SrO, MgO, Y2O3, the rare earth oxide, Sc2O3, BaO, HfO2, ZrO2, Al2O3, Li2O3, TiO, CeO2, TiO2, SiO2, B2O3, Cr2O3 and ZnO.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、電気絶縁性炭化硅素セラミック基板を用いた
集積回路に係シ、特に大電力半導体素子を搭載するのに
適した厚膜混成集積回路に関する。
[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an integrated circuit using an electrically insulating silicon carbide ceramic substrate, and particularly a thick film hybrid integrated circuit suitable for mounting a high-power semiconductor element. Regarding.

〔発明の背景〕[Background of the invention]

集積回路は、セラミック基板上に導体、抵抗等を有する
。これらの導体、抵抗をスクリーン印刷或いは焼成技術
によって形成したのが厚膜混成集積回路である。
An integrated circuit has conductors, resistors, etc. on a ceramic substrate. Thick film hybrid integrated circuits are formed by forming these conductors and resistors by screen printing or baking techniques.

集積回路におけるセラミック基板には、酸化物系のセラ
ミック主としてアルミナ(At203 ”Iが使用され
てき゛た。
Alumina (At203''I), which is an oxide ceramic, has been used for ceramic substrates in integrated circuits.

しかし、最近、酸化物系セラミックに代わって炭化物系
セラミックたとえば炭化硅素(SiC)が使用される傾
向にある。このことは特開昭55−113683 号公
報によっても伺い知ることができる。
However, recently, carbide ceramics such as silicon carbide (SiC) are being used instead of oxide ceramics. This fact can also be found in Japanese Patent Application Laid-Open No. 113683/1983.

本発明は、電気絶縁性炭化硅素セラミック基板の表面に
直接厚膜抵抗を形成する技術を研究している過程で見出
されたものである。すなわち、アルミナ基板のときに使
っていた厚膜抵抗材料を炭化硅素セラミック基板に対し
て使うと、厚膜抵抗にふくれが生じることを究明し、そ
の対策を検討していて見出したものである。
The present invention was discovered in the process of researching a technique for directly forming a thick film resistor on the surface of an electrically insulating silicon carbide ceramic substrate. In other words, we discovered that when the thick film resistor material used for alumina substrates was used for silicon carbide ceramic substrates, blistering occurred in the thick film resistors, and we were considering countermeasures.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、電気絶縁性炭化硅素セラミック基板の
表面にふくれのない厚膜抵抗を有する集積回路を提供す
るにある。
An object of the present invention is to provide an integrated circuit having a thick film resistor without blisters on the surface of an electrically insulating silicon carbide ceramic substrate.

〔発明の概要〕 本発明は、厚膜抵抗の材料として、炭化硅素セラミック
に対して非反応性の導電性物質と非還元性ガラス(各成
分は分子中の各金属−酸素結合1個当シ約−49Kca
t/ mot以下の900Cにおけるキプスの標準生成
自由エネルギーを有する)よシなるものを用いることを
特徴とする。
[Summary of the Invention] The present invention uses a non-reactive conductive substance and a non-reducing glass (each component corresponds to one metal-oxygen bond in the molecule) to silicon carbide ceramic as a material for a thick film resistor. Approximately -49Kca
It is characterized by using a material having a standard Kipus free energy of formation at 900C of less than t/mot.

導電性物質と非還元性ガラスの組成比は、厚膜抵抗の抵
抗値の目標をどこにおくかによって決まる。高抵抗にし
たい場合には、非還元性ガラスの量を多くすればよいし
、低抵抗にしたい場合には導電性物質の量を多くすれば
よい。炭化硅素セラミック基板に対する厚膜抵抗の接着
性を考慮し、非還元性ガラスの量は少なくとも5重量%
以上とすることが望ましい。一般には、導電性物質10
〜95重量%、非還元性ガラス残部の範囲内で選ぶこと
が望ましい。
The composition ratio of the conductive substance and non-reducing glass is determined by the target resistance value of the thick film resistor. If high resistance is desired, the amount of non-reducing glass may be increased, and if low resistance is desired, the amount of conductive material may be increased. Considering the adhesion of the thick film resistor to the silicon carbide ceramic substrate, the amount of non-reducible glass is at least 5% by weight.
It is desirable to set the above. Generally, conductive material 10
It is desirable to choose within the range of 95% by weight with the remainder being non-reducible glass.

アルミナセラミック基板に対して使用されている厚膜抵
抗を炭化硅素セラミック基板に対して使用した場合に、
厚膜抵抗にふくれが発生するのは次の理由による。
When a thick film resistor used for an alumina ceramic substrate is used for a silicon carbide ceramic substrate,
The reason why bulges occur in thick film resistors is as follows.

アルミナ基板の厚膜抵抗には、導電性物質としてRII
 02、ガラス物質としてPbOなどが使用されている
ので、これらを例にとって説明する。
The thick film resistor on the alumina substrate uses RII as the conductive material.
02. Since PbO and the like are used as glass materials, explanation will be given by taking these as examples.

なお、本発明において電気絶縁性炭化硅素セラミック基
板は、全く導電性がないものを意味するわけではない。
Note that in the present invention, the electrically insulating silicon carbide ceramic substrate does not mean that it has no conductivity at all.

集積回路の基板として使える程度に電気絶縁性があるこ
とを意味している。
This means that it has enough electrical insulation to be used as a substrate for integrated circuits.

本発明の技術は、炭化硅素セラミック全般に広く適用す
ることが可能である。
The technology of the present invention can be widely applied to silicon carbide ceramics in general.

Ru 02は非常に還元性の強い金属酸化物であるため
、Ru 02を導電性物質とした厚膜抵抗体をSiC基
板上で焼成した場合には、(1)式に示す反応が生じる
Since Ru 02 is a highly reducing metal oxide, when a thick film resistor using Ru 02 as a conductive substance is fired on a SiC substrate, the reaction shown in equation (1) occurs.

8iC+3/2RL102 →5iOz+3/2Ru+
CO↑・(1)一方、PbOも非常に還元性の強い金属
酸化物であるため、(I)式同様に(2)式に示す反応
が生じる。
8iC+3/2RL102 →5iOz+3/2Ru+
CO↑・(1) On the other hand, since PbO is also a highly reducing metal oxide, the reaction shown in formula (2) occurs similarly to formula (I).

sic+3Pbo→5i02+3Pb+CO↑  ・・
・ (2)これらの反応により発生したCOガスによっ
て抵抗体膜にふくれが生じる。
sic+3Pbo→5i02+3Pb+CO↑ ・・
- (2) The CO gas generated by these reactions causes blistering in the resistor film.

一般に、SiCと金属酸化物(MOと仮定する)との反
応を(3)式のように仮定した場合、(3)式に示す反
応が起こるか否かは、この反応の生成自由エネルギー(
ΔGで表す)を考えればよい。
Generally, when the reaction between SiC and a metal oxide (assumed to be MO) is assumed to be as shown in equation (3), whether or not the reaction shown in equation (3) occurs is determined by the formation free energy of this reaction (
(expressed as ΔG).

8 i C+ 3M0−+8 i 02 + 3M+ 
CO↑ ・・・ (3)(3)式に示す反応が生じない
だめの条件は焼成温度におけるΔGが正になることであ
り、成る温度におけるΔGは(4)、(5)式のように
なる。
8 i C+ 3M0-+8 i 02 + 3M+
CO↑ ... (3) The condition for the reaction shown in equation (3) to occur is that ΔG at the firing temperature is positive, and ΔG at the temperature is as shown in equations (4) and (5). Become.

ΔG−(ΔG′5lo2+3ΔG′M+ΔG’(o)−
4ΔG;Io+3ΔG′Mo)〉O・・・・・・・・・
 (4) 上記の(5)式を満足するような標準生成自由エネルギ
ー値を有する金属酸化物で構成された厚膜抵抗体であれ
ば、焼成時に(3)式に示す反応は起らず、抵抗膜のふ
くれ、抵抗体物質の化学変化の無い良好な厚膜抵抗体を
得ることができる。但し、式(4)。
ΔG-(ΔG'5lo2+3ΔG'M+ΔG'(o)-
4ΔG; Io+3ΔG'Mo)〉O・・・・・・・・・
(4) If the thick film resistor is made of a metal oxide having a standard formation free energy value that satisfies the above equation (5), the reaction shown in equation (3) will not occur during firing, It is possible to obtain a good thick film resistor without blistering of the resistor film or chemical change of the resistor material. However, formula (4).

式(5)中のΔGO8ICは所定の温度におけるsic
の標準生成自由エネルギー値を示す。同様にΔG0O は所定の温度における金属酸化物MOの標準生成自由エ
ネルギー値を示す。その他も同様である。
ΔGO8IC in equation (5) is sic at a given temperature
shows the standard free energy of formation value. Similarly, ΔG0O represents the standard free energy of formation of metal oxide MO at a predetermined temperature. The same applies to others.

非還元性酸化物よシ成るガラスの通常の焼成温度が90
0C前後であることよ、9.1200’Kにおける(5
)式の条件を計算すると、Δo;o < −48,7K
cat/ mot即ち約−49Kcat/mot以下ト
fxる。この、ΔGoMoの値を満足する非還元性金属
酸化物を以下に示す。なお、カッコ内には1200’K
における金属−酸素結合1個描シのΔG’M□ (Kc
 al/mot)値を示した。
The normal firing temperature for glass made of non-reducible oxides is 90°C.
It should be around 0C, 9. (5 at 1200'K)
) Calculating the condition of the formula, Δo;o < −48,7K
cat/mot or less than about -49Kcat/motfx. Non-reducible metal oxides that satisfy this value of ΔGoMo are shown below. In addition, 1200'K is in parentheses.
ΔG'M□ (Kc
al/mot) values are shown.

Cab(−121)、That (−119)、Bed
(−115)、Lat、s (−115)、5ro(−
113)、Mg0(−itz)、 Y2O3(−txt
)、希土類酸化物(−n。
Cab (-121), That (-119), Bed
(-115), Lat, s (-115), 5ro(-
113), Mg0(-itz), Y2O3(-txt
), rare earth oxide (-n.

〜−108)、5C203(107)、Bad(−10
6)。
~-108), 5C203 (107), Bad (-10
6).

Hf0z (105)、Zr02(103)、Atze
3(103)、Ljz03(−103)、Tie(−9
7)、Ce02(92L T′i0□(−87L 5i
02 (−80)、B2O3(78LCrzOs (−
65>、Zn0(53)。
Hf0z (105), Zr02 (103), Atze
3 (103), Ljz03 (-103), Tie (-9
7), Ce02(92L T'i0□(-87L 5i
02 (-80), B2O3(78LCrzOs (-
65>, Zn0 (53).

一方、代表的な還元性金属酸化物としては、次に示すも
のがある。5n02(40’l、Mn0z(313)。
On the other hand, typical reducing metal oxides include the following. 5n02(40'l, Mn0z(313).

K2O(37)、 N1p(−33)、 Cd0(−2
8)、 Pb0(24)、 Bi20g (19)、 
CLIO(13’)、 Ru02(4)。これらの還元
性金属酸化物は(3)式に示す反応を生じると考えられ
、SiC基板上に直接形成する厚膜抵抗の組成物として
は好ましくない。
K2O(37), N1p(-33), Cd0(-2
8), Pb0 (24), Bi20g (19),
CLIO (13'), Ru02 (4). These reducing metal oxides are thought to cause the reaction shown in equation (3), and are not preferred as a composition for a thick film resistor directly formed on a SiC substrate.

したがって、SiC基板上に直接形成する厚膜抵抗の導
電性物質は、炭化硅素セラミックと反応しないLaB6
 、MOB、YB6.CaB6.BaBs l5rBa
などの非酸化物及び、’l’a205 、 InzOa
などの非還元性金属酸化物が適し、ガラス成分としでは
、前記非還元性金属酸化物が適する。
Therefore, the conductive material of the thick film resistor formed directly on the SiC substrate is LaB6, which does not react with silicon carbide ceramic.
, MOB, YB6. CaB6. BaBs l5rBa
Non-oxides such as 'l'a205, InzOa
Non-reducible metal oxides such as the following are suitable, and the above-mentioned non-reducible metal oxides are suitable as the glass component.

〔発明の実施例〕[Embodiments of the invention]

実施例1 電気絶縁性炭化硅素セラミック基板上に第1表に示すガ
ラスペーストを焼成にょシ形成した。屋1は非還元性ガ
ラスであシ、屋2とA3は還元性ガラスである。
Example 1 A glass paste shown in Table 1 was formed by firing on an electrically insulating silicon carbide ceramic substrate. House 1 is made of non-reducing glass, and House 2 and A3 are made of reducing glass.

非還元性ガラスを用いたペーストは、ふくれが生じなか
ったが、還元性ガラスを用いたA2と屋3は激しい発泡
現象があシ、ペーストのふくれが生じた。
The paste using non-reducing glass did not cause blistering, but A2 and Ya3 using reducing glass had a severe bubbling phenomenon and the paste blistered.

実施例2 第1表に示すガラスと導電性物質の混合物を電気絶縁性
炭化硅素セラミック基板に焼成によシ形成し、厚膜抵抗
を得た。混合物の組成比および発泡状況の有無を第2表
に示す。■は発泡現象がなくふくれが認められなかった
が、■及び■は激しい発泡現象があシふくれが認められ
た。
Example 2 A mixture of glass and conductive material shown in Table 1 was formed on an electrically insulating silicon carbide ceramic substrate by firing to obtain a thick film resistor. Table 2 shows the composition ratio of the mixture and the presence or absence of foaming. In case (2), there was no foaming phenomenon and no blistering was observed, but in cases (2) and (2), severe bubbling phenomenon and blistering were observed.

第   2   表 実施例3 第1図によシ実施例を説明する。ここで用いたL a 
B g系抵抗ペーストの組成は下記のとおシである。
Table 2 Example 3 An example will be explained with reference to FIG. L a used here
The composition of the Bg-based resistance paste is as follows.

LaBc+系抵抗ペースト成分: LaBa 20重量
%。
LaBc+ resistance paste component: LaBa 20% by weight.

ガラス50重量%、ビヒクル30重量%。50% glass, 30% vehicle.

ガラス組成: B2O325,9重量%+ s 1Q2
40.8重量’l=、 、 AtzOs I J3.8
重量s、Ca0 10.3重量% l zro、 3.
6重量%、Tie、0.6重量%。
Glass composition: B2O325, 9% by weight + s 1Q2
40.8 weight'l=, , AtzOs I J3.8
Weight s, Ca0 10.3% by weight l zro, 3.
6% by weight, Tie, 0.6% by weight.

酸化べIJ IJウムで粒界制御をして、電気絶縁性に
した高熱伝導率(2,7W/ cm−1Z’ )′ft
有するSiC基板上の上K、抵抗端子としてAu系厚膜
導体2a及びこの端子間にLaB、系厚膜抵抗体3を形
成しつづいてAg/Pd系厚膜導体2を形成した。さら
に厚膜導体2に、Pb80/5n20はんだ5を用いて
、大電力トランジスタ(コレクタ損失IW)4を接続し
、ベース及びエミッタ端子はアルミニウム線6により厚
膜導体2に接続した。
High thermal conductivity (2.7W/cm-1Z')'ft made electrically insulating by controlling the grain boundaries with Betium oxide.
On the upper surface of the SiC substrate, an Au-based thick-film conductor 2a was formed as a resistance terminal, and a LaB-based thick-film resistor 3 was formed between these terminals, and then an Ag/Pd-based thick-film conductor 2 was formed. Furthermore, a high power transistor (collector loss IW) 4 was connected to the thick film conductor 2 using a Pb80/5n20 solder 5, and the base and emitter terminals were connected to the thick film conductor 2 using an aluminum wire 6.

さらにコンデンサ等の電子部品(図示せず)を搭載して
、厚膜混成集積回路を形成した。
Furthermore, electronic components such as capacitors (not shown) were mounted to form a thick film hybrid integrated circuit.

本実施例の混成集積回路動作時における半導体素子上面
の温度上昇を測定し、アルミナ基板上に同一の半導体を
用いて同じように形成した第2図の従来技術による混成
集積回路の場合と比較した結果、本実施例での温度上昇
が従来例よ#)3c低かった。また、本実施例の混成集
積回路の面積((基板面積)は、従来例よシ約20%小
さくすることができた。従来技術の場合、アルミナの熱
伝導率が小さい(0,2〜0.3 w/cm = c)
ので、半導体素子を接続するときに予め導体2に金属放
熱板を接合し、放熱板を介して半導体素子を接続する必
要があるが、本発明によれば金属放熱板を省略できると
いう効果もある。
The temperature rise on the top surface of the semiconductor element during operation of the hybrid integrated circuit of this example was measured, and compared with that of a hybrid integrated circuit according to the prior art shown in FIG. 2, which was formed in the same way using the same semiconductor on an alumina substrate. As a result, the temperature rise in this example was #) 3c lower than in the conventional example. In addition, the area (substrate area) of the hybrid integrated circuit of this example was able to be reduced by about 20% compared to the conventional example. .3 w/cm = c)
Therefore, when connecting a semiconductor element, it is necessary to bond a metal heat sink to the conductor 2 in advance and connect the semiconductor element through the heat sink, but the present invention has the effect that the metal heat sink can be omitted. .

第2図において、符号7はアルミナ基板、8は金属放熱
板である。
In FIG. 2, numeral 7 is an alumina substrate, and 8 is a metal heat sink.

実施例4 第3図は実施例3と同じSiC基板を用いて、大電力半
導体ICを搭載した厚膜混成集積回路の実施例である。
Embodiment 4 FIG. 3 is an embodiment of a thick film hybrid integrated circuit using the same SiC substrate as in Embodiment 3 and mounting a high-power semiconductor IC.

基板l上に、Au系厚膜導体2aを形成した後、実施例
3と同様にL a B s系厚膜抵抗体3及びA g/
P d系厚膜抵体2を形成した。
After forming the Au-based thick film conductor 2a on the substrate l, the L a B s-based thick film resistor 3 and the A g/
A Pd-based thick film resistor 2 was formed.

つぎに、半導体ICl0を導体2上に重ね、AIJ−8
i共晶9を形成して接続し、ICの端子はA、u線6に
よシ導体2aに接続した。
Next, the semiconductor ICl0 is stacked on the conductor 2, and the AIJ-8
An i-eutectic 9 was formed and connected, and the terminal of the IC was connected to the conductor 2a through the A and U wires 6.

本実施例の厚膜混成集積回路でも、実施例3の場合と同
様の熱放散効果が得られた。また、実施例4も厚膜抵抗
体を直接高熱伝導5iCK形成できるので、厚膜抵抗体
の面積を小さくすることができ、基板面積の小型化に効
果がある。
The same heat dissipation effect as in Example 3 was also obtained in the thick film hybrid integrated circuit of this example. Furthermore, since the thick film resistor in Example 4 can also be directly formed with high thermal conductivity 5iCK, the area of the thick film resistor can be reduced, which is effective in reducing the substrate area.

以上、実施例について詳述した通り、本発明によれば、
厚膜抵抗のふくれ防止のほか熱伝導の極めで高いSiC
セラミック基板を用いることによυ大電力半導体素子に
放熱用金属板を取付けることなく基板に直接搭載でき、
またSiC基板上に直接厚膜導体及び厚膜抵抗体を形成
できるので、厚膜混成集積回路の小形化に大きな効果が
ある。
As described above in detail regarding the embodiments, according to the present invention,
In addition to preventing thick film resistors from blistering, SiC has extremely high thermal conductivity.
By using a ceramic substrate, υ high-power semiconductor devices can be mounted directly on the substrate without attaching a metal plate for heat dissipation.
Furthermore, since thick film conductors and thick film resistors can be formed directly on the SiC substrate, there is a great effect on downsizing of thick film hybrid integrated circuits.

〔発明の効果〕〔Effect of the invention〕

以上述べたとおり、本発明によれば電気絶縁性炭化硅素
セラミック基板に直接、厚膜導体を形成した場合に、厚
膜導体にふくれが生じるのを防止できる。
As described above, according to the present invention, when a thick film conductor is directly formed on an electrically insulating silicon carbide ceramic substrate, it is possible to prevent blisters from forming in the thick film conductor.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す厚膜混成集積回路の断
面図、第2図は大電力半導体素子を有する従来例による
厚膜混成集積回路の断面図、第3図は本発明の他の実施
例による厚膜混成集積回路の断面図である。
FIG. 1 is a sectional view of a thick film hybrid integrated circuit according to an embodiment of the present invention, FIG. 2 is a sectional view of a conventional thick film hybrid integrated circuit having a high power semiconductor element, and FIG. 3 is a sectional view of a thick film hybrid integrated circuit according to an embodiment of the present invention. FIG. 7 is a cross-sectional view of a thick film hybrid integrated circuit according to another embodiment.

Claims (1)

【特許請求の範囲】 1、電気絶縁性炭化硅素セラミック基板の表面に、前記
炭化硅素セラミックに対して非反応性の導電性物質と非
還元性ガラス(各成分は分子中の各金属−酸素結合1個
当シ約−49Kcal / mol以下の900Cにお
けるギプスの標準生成自由エネルギーを有する)よシな
る厚膜抵抗を有することを特徴とする集積回路。 2、特許請求の範囲第1項においで、前記導電性物質が
LaB5 、 MOB、 YB6 、 CaBs 、 
BaBa 。 8rBs + Ta205 + In2O3よりなる群
から選ばれた少なくとも1つよシなることを特徴とする
集積回路。 3、特許請求の範囲第1項において、前記非還元性ガラ
スがCab、 Tb02 t Bed、 La2O5、
sro。 MgO,Y2O3,希土類酸化物+ 8czOs + 
BaQ。 Hf 02 r Z r02 + AZ203+ L 
i20g ’+ T ’ 0 * CeOz TTiO
z 、 8i0z 、 B2O3、cr2o3 、 Z
nOよシなる群から選ばれた少なくとも1つからなるこ
とを特徴とする集積回路。
[Claims] 1. On the surface of an electrically insulating silicon carbide ceramic substrate, a conductive substance that is non-reactive with the silicon carbide ceramic and a non-reducing glass (each component is a metal-oxygen bond in the molecule) An integrated circuit characterized in that it has a thick film resistor having a typical free energy of formation of a cast at 900C of less than about -49 Kcal/mol per piece. 2. In claim 1, the conductive material is LaB5, MOB, YB6, CaBs,
BaBa. An integrated circuit comprising at least one selected from the group consisting of 8rBs + Ta205 + In2O3. 3. In claim 1, the non-reducing glass is Cab, Tb02t Bed, La2O5,
sro. MgO, Y2O3, rare earth oxide + 8czOs +
BaQ. Hf 02 r Z r02 + AZ203+ L
i20g '+ T' 0 * CeOz TTiO
z, 8i0z, B2O3, cr2o3, Z
An integrated circuit comprising at least one selected from the group consisting of nO and cy.
JP58039017A 1983-03-11 1983-03-11 Integrated circuit Pending JPS59165447A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58039017A JPS59165447A (en) 1983-03-11 1983-03-11 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58039017A JPS59165447A (en) 1983-03-11 1983-03-11 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS59165447A true JPS59165447A (en) 1984-09-18

Family

ID=12541333

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58039017A Pending JPS59165447A (en) 1983-03-11 1983-03-11 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS59165447A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4785342A (en) * 1986-01-29 1988-11-15 Hitachi, Ltd. Static random access memory having structure of first-, second- and third-level conductive films
US5196915A (en) * 1988-11-21 1993-03-23 Hitachi, Ltd. Semiconductor device
WO2003061097A1 (en) * 2002-01-18 2003-07-24 Eun-Kook Kim Electric energy saving device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527700A (en) * 1978-08-16 1980-02-27 Du Pont Thick film composition
JPS55113683A (en) * 1979-02-21 1980-09-02 Kyoto Ceramic Method and composition of metallizing carbide type ceramic body
JPS5666086A (en) * 1979-11-05 1981-06-04 Hitachi Ltd Electrically insulating board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5527700A (en) * 1978-08-16 1980-02-27 Du Pont Thick film composition
JPS55113683A (en) * 1979-02-21 1980-09-02 Kyoto Ceramic Method and composition of metallizing carbide type ceramic body
JPS5666086A (en) * 1979-11-05 1981-06-04 Hitachi Ltd Electrically insulating board

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4785342A (en) * 1986-01-29 1988-11-15 Hitachi, Ltd. Static random access memory having structure of first-, second- and third-level conductive films
US5196915A (en) * 1988-11-21 1993-03-23 Hitachi, Ltd. Semiconductor device
WO2003061097A1 (en) * 2002-01-18 2003-07-24 Eun-Kook Kim Electric energy saving device

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