JPH08153945A - Ceramic circuit board - Google Patents
Ceramic circuit boardInfo
- Publication number
- JPH08153945A JPH08153945A JP4972395A JP4972395A JPH08153945A JP H08153945 A JPH08153945 A JP H08153945A JP 4972395 A JP4972395 A JP 4972395A JP 4972395 A JP4972395 A JP 4972395A JP H08153945 A JPH08153945 A JP H08153945A
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- glass
- circuit board
- overcoat
- ceramic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/06—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base
- H01C17/065—Apparatus or processes specially adapted for manufacturing resistors adapted for coating resistive material on a base by thick film techniques, e.g. serigraphy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
- H01C17/02—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistors with envelope or housing
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はオーバーコートガラスで
覆われた外部抵抗体を表面に有するセラミック回路基板
に関する。更に詳しくはトリミングによって得られた正
確な抵抗値を安定に維持する外部抵抗体を有するセラミ
ック回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ceramic circuit board having an external resistor covered with overcoat glass on its surface. More specifically, the present invention relates to a ceramic circuit board having an external resistor that stably maintains an accurate resistance value obtained by trimming.
【０００２】[0002]
【従来の技術】集積回路に使用されるセラミック回路基
板において、多層回路基板の層間に設けられる内蔵抵抗
体の他に、セラミック回路基板の表面に印刷された導体
パターンと外部抵抗体などからなる回路が設けられ、セ
ラミック回路基板の高機能化、低コスト化に貢献してい
る。基板表面に抵抗体を形成する場合、一般的にはガラ
ス組成分に導電性物質を加えたものをペースト状にして
印刷し、焼結して抵抗体とする。この際、抵抗体の保護
や耐候性の向上を目的として、抵抗体をガラス系材料で
覆うように印刷し、焼成することによりオーバーコート
することも行われている。更に、レーザートリミングな
どの手法を用いて抵抗値が微調整される。2. Description of the Related Art In a ceramic circuit board used for an integrated circuit, in addition to a built-in resistor provided between layers of a multilayer circuit board, a circuit including a conductor pattern printed on the surface of the ceramic circuit board and an external resistor. Is provided, which contributes to higher functionality and lower cost of the ceramic circuit board. When a resistor is formed on the surface of a substrate, generally, a glass composition containing a conductive substance is printed in a paste form, and the paste is printed to obtain a resistor. At this time, for the purpose of protecting the resistor and improving weather resistance, the resistor is printed so as to be covered with a glass-based material, and is overcoated by firing. Further, the resistance value is finely adjusted using a technique such as laser trimming.
【０００３】一般にセラミック回路基板に用いられる抵
抗体は、抵抗体を８００〜９００℃で焼成後、低融点の
オーバーコートガラスを印刷し、５００〜６００℃で焼
成する。しかしながら電子機器の小型化、高密度化に伴
いセラミック基板も高密度のための多層化、シリコンチ
ップ搭載のために低熱膨張化の傾向にある。このような
回路基板には低温焼成基板が用いられている。低温焼成
基板は多くの場合内層にＡｇ，Ｃｕが用いられていて、
その熱膨張収縮の回数を少なくし、信頼性の高い回路基
板を得るためには焼成回数はできる限り少なくする必要
がある。又、回路基板と熱膨張を合わせる為、オーバー
コートガラスも低熱膨張のガラスを用いる必要がある
が、低融点のガラスは耐候性の点で欠点がある。そのた
め抵抗体の焼成温度程度のガラスを用いざるを得ない。
従って、多層構造、あるいは低熱膨張のセラミック回路
基板にはオーバーコートと同時焼成の抵抗体を用いるの
が望ましいことになる。しかし、抵抗体とオーバーコー
トを同時に焼成すると、オーバーコートガラスが抵抗体
から発生する気泡を閉じ込め、焼結後の抵抗体内部に気
泡が残存する傾向がある。抵抗体中気泡はレーザートリ
ミング時にトリミング先端が気泡と非常に接近した場
合、トリミング先端と気泡との間にクラックが入り、抵
抗値の安定性のない抵抗体になるという問題点があっ
た。Generally, a resistor used for a ceramic circuit board is produced by firing a resistor at 800 to 900 ° C., printing a low melting point overcoat glass, and firing at 500 to 600 ° C. However, along with the miniaturization and high density of electronic devices, there is a tendency for ceramic substrates to be multi-layered for high density and to have low thermal expansion due to mounting silicon chips. A low temperature firing substrate is used for such a circuit substrate. In many cases, low-temperature fired substrates use Ag or Cu for the inner layer,
In order to reduce the number of times of thermal expansion and contraction and obtain a highly reliable circuit board, it is necessary to reduce the number of firings as much as possible. Further, in order to match the thermal expansion with that of the circuit board, it is necessary to use a glass having a low thermal expansion as the overcoat glass, but a glass having a low melting point has a drawback in terms of weather resistance. Therefore, it is unavoidable to use glass having a firing temperature of the resistor.
Therefore, it is desirable to use a resistor that is co-fired with an overcoat for a ceramic circuit board having a multilayer structure or low thermal expansion. However, when the resistor and the overcoat are fired at the same time, the overcoat glass tends to trap the bubbles generated from the resistor and the bubbles tend to remain inside the resistor after sintering. The bubble in the resistor has a problem that when the trimming tip comes very close to the bubble during laser trimming, a crack is formed between the trimming tip and the bubble, and the resistance value is not stable.
【０００４】これを図によって説明すると、図１はセラ
ミック回路基板上に設けられた従来の外部抵抗体の平面
図であり、図２はその断面図である。セラミック基板の
表面１に金属ペーストなどを配線材料として印刷して表
面の導体パターン２が形成され、その一部が抵抗体への
電極となっている。抵抗体３はガラス成分に金属などの
導電材料を加えたものが用いられ、その上部を覆ってガ
ラス材料がオーバーコート４されている。そして、抵抗
体３とオーバーコート４とで外部抵抗体７が形成されて
いる。このオーバーコート４は個々の抵抗体３よりやや
広くなるように覆ってもよいし、複数の抵抗体３を導体
パターン２をも含めて広い面積にわたって一様に覆って
もよい。広い範囲をオーバーコートする場合には、必要
な個所にビアホールを設け、更に外部との導通を図るこ
ともできる。オーバーコート４と抵抗体３は同時焼成さ
れると、抵抗体内に発生した気泡６がオーバーコート４
が存在することによって外部へ逃げられなくなって内部
に閉じ込められた状態となっている。このような外部抵
抗体７をレーザートリミングすると図示されるようなト
リミング溝５がオーバーコート４と抵抗体３中に形成さ
れる。通常、レーザートリミングは抵抗値を測定しなが
ら行われるが、気泡６の存在はこのような精密なトリミ
ングを困難にするばかりでなく、トリミング溝の先端が
気泡６と接近した場合にはマイクロクラックが生ずるこ
とになる。また、トリミング中にはクラックが生じてい
なくても、気泡が原因となって製品として使用中にクラ
ックが発生することもある。このように抵抗体中の気泡
の存在は抵抗値を不正確にし、安定性のないものとして
いる。This will be explained with reference to the drawings. FIG. 1 is a plan view of a conventional external resistor provided on a ceramic circuit board, and FIG. 2 is a sectional view thereof. A metal paste or the like is printed as a wiring material on the surface 1 of the ceramic substrate to form a conductor pattern 2 on the surface, and a part of the conductor pattern 2 serves as an electrode to the resistor. The resistor 3 is formed by adding a conductive material such as a metal to a glass component, and the glass material is overcoated 4 to cover the upper portion thereof. Then, the resistor 3 and the overcoat 4 form an external resistor 7. The overcoat 4 may be covered so as to be slightly wider than the individual resistors 3, or the plurality of resistors 3 may be uniformly covered over a wide area including the conductor pattern 2. When overcoating a wide range, via holes may be provided at necessary places to further connect with the outside. When the overcoat 4 and the resistor 3 are co-fired, the bubbles 6 generated in the resistor will be overcoated.
Due to the existence of, it cannot be escaped to the outside and is in a state of being confined inside. When such an external resistor 7 is laser-trimmed, a trimming groove 5 as shown is formed in the overcoat 4 and the resistor 3. Normally, laser trimming is performed while measuring the resistance value, but the presence of the bubbles 6 not only makes such precise trimming difficult, but also causes microcracks when the tip of the trimming groove approaches the bubbles 6. Will occur. Even if no crack is generated during trimming, bubbles may cause cracks during use as a product. Thus, the presence of bubbles in the resistor makes the resistance value inaccurate and makes it instable.
【０００５】[0005]
【発明が解決しようとする課題】本発明の目的は、抵抗
体が気泡をほとんど含有せず、かつ、抵抗体と同時焼成
されたオーバーコートを有する外部抵抗体付きセラミッ
ク回路基板を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a ceramic circuit board with an external resistor in which the resistor contains almost no bubbles and which has an overcoat co-fired with the resistor. is there.
【０００６】[0006]
【課題を解決するための手段】本発明者らは鋭意検討の
結果、抵抗体とオーバーコートガラスが特定の関係を有
する時に上記目的が達成されることを見出し本発明に至
った。即ち、本発明は下記の（１）〜（５）の構成のセ
ラミック回路基板である。 （１）抵抗体とオーバーコートガラスとを同時焼成して
なる外部抵抗体を有するセラミック回路基板において、
該外部抵抗体は低気泡性抵抗体を有することを特徴とす
るセラミック回路基板。 （２）上記抵抗体に含まれるＡｇ系成分の含有量が０〜
１％であり、該抵抗体のガラスの屈伏点が上記オーバー
コートガラスの屈伏点以下であることを特徴とする
（１）記載のセラミック回路基板。 （３）上記抵抗体がＡｇ系成分を１％以上含有し、該抵
抗体のガラスの屈伏点の１０℃低い温度が、上記オーバ
ーコートガラスの屈伏点以下であることを特徴とする
（１）記載のセラミック回路基板。 （４）上記抵抗体のガラス成分がＣａＯ−Ａｌ2Ｏ3−Ｓ
ｉＯ2−Ｂ2Ｏ3系ガラスであることを特徴とする（１）
記載のセラミック回路基板。 （５）上記オーバーコートガラスの成分がＣａＯ−Ａｌ
2Ｏ3−ＳｉＯ2−Ｃｒ2Ｏ3−Ｂ2Ｏ3系ガラス粉末６０〜
９０重量％とアルミナ粉末１０〜４０重量％を含有し、
かつガラスの屈伏点が７２０〜７４０℃であることを特
徴とする（１）記載のセラミック回路基板。As a result of intensive studies, the present inventors have found that the above object can be achieved when the resistor and the overcoat glass have a specific relationship, and have completed the present invention. That is, the present invention is a ceramic circuit board having the following configurations (1) to (5). (1) In a ceramic circuit board having an external resistor formed by simultaneously firing a resistor and an overcoat glass,
The ceramic circuit board, wherein the external resistor has a low-foaming resistor. (2) The content of the Ag-based component contained in the resistor is 0 to
The ceramic circuit board according to (1), wherein the resistance point of the glass of the resistor is 1% or less, and the deformation point of the glass of the resistor is not more than the deformation point of the overcoat glass. (3) It is characterized in that the resistor contains 1% or more of an Ag-based component, and a temperature lower than the yield point of glass of the resistor by 10 ° C. is equal to or lower than the yield point of the overcoat glass (1). The described ceramic circuit board. (4) the glass component of the resistor is CaO-Al 2 O 3 -S
It is characterized by being a glass of iO 2 -B 2 O 3 (1)
The described ceramic circuit board. (5) The component of the above overcoat glass is CaO-Al
2 O 3 -SiO 2 -Cr 2 O 3 -B 2 O 3 based glass powder 60
90% by weight and 10 to 40% by weight of alumina powder,
And the yield point of glass is 720-740 degreeC, The ceramic circuit board as described in (1) characterized by the above-mentioned.
【０００７】本発明によって、オーバーコートガラスと
抵抗体を同時焼成しても、抵抗体に気泡が残留せず、低
気泡性抵抗体が得られる理由は、第一に、Ａｇ系成分の
含有量が０〜１％であり、オーバーコートの屈伏点より
抵抗体のガラスが低い又は同等の屈伏点を持つようにす
ることにより、抵抗体の焼結を早くし、発生した気泡を
オーバーコートガラス側に逃がすからであり、第二に、
抵抗体にＲｕＯ2系やＢｉ2Ｒｕ2Ｏ7系の電気抵抗成分に
加えてＡｇを積極的に添加することにより、Ａｇがこの
抵抗体材料と組み合わされて焼結を促進し、上記と同様
に抵抗体の焼結を早くして発生した気泡をオーバーコー
トガラス側に逃がすからである。なお、本発明において
用いる屈伏点とは、ガラス材料を加温するにつれて、ほ
ぼ直線的に熱膨張率も上昇するが、ある温度でこの上昇
が止まり低下に転じる時のガラスの軟化温度に相当する
ものである。この熱膨張率の測定方法自体は日本工業規
格に定められている。According to the present invention, even when the overcoat glass and the resistor are co-fired, bubbles do not remain in the resistor and a low-foaming resistor is obtained. Firstly, the content of the Ag-based component is Is 0 to 1%, and by making the glass of the resistor have a lower or equal yield point than the yield point of the overcoat, sintering of the resistor is accelerated and bubbles generated are generated on the overcoat glass side. Secondly,
By positively adding Ag to the resistor in addition to the electric resistance component of RuO 2 system or Bi 2 Ru 2 O 7 system, Ag is combined with this resistor material to promote sintering, and the same as above. This is because the bubbles generated by accelerating the sintering of the resistor escape to the overcoat glass side. Incidentally, the yield point used in the present invention corresponds to the softening temperature of the glass when the glass material is heated and the coefficient of thermal expansion almost linearly increases, but stops increasing at a certain temperature and starts to decrease. It is a thing. The method of measuring the coefficient of thermal expansion itself is specified in Japanese Industrial Standards.
【０００８】本発明のセラミック回路基板としては、セ
ラミックを絶縁体として使用するものであれば単層でも
多層でもよく、多層のセラミック回路基板の場合はその
製法として、グリーンシート積層法、グリーンシート印
刷法が挙げられる。又、基板の片面のみの回路基板でも
両面回路基板でもよい。本発明に用いられるセラミック
材料としては特に限定されず、アルミナ（Ａｌ2Ｏ3）、
窒化アルミニウム（ＡｌＮ）や炭化ケイ素（ＳｉＣ）及
びこれらを主成分とする各種セラミックが挙げる。又、
アルミナ粉末にガラス粉末を混入した低温焼成セラミッ
クも用いることができる。内層に用いられる導体材料は
基板材料によって異なり、アルミナや窒化アルミニウム
ではモリブデンやタングステンのような高融点金属が使
われる。比較的低温で焼成できる基板材料のときは、
金、銀、銀−パラジウム合金、銅、ニッケルなどの金属
が用いられる。セラミックグリーンシートと配線用導体
ペーストを同時焼成する同時焼成セラミック回路基板の
一つに、ＷやＭｏをアルミナまたは窒化アルミ等の基板
の配線用導体として使用し、導体が酸化しないように還
元雰囲気で同時焼成するセラミック回路基板がある。し
かしながら、酸化雰囲気で焼成する必要のある信頼性の
高いＲｕＯ2系やＢｉ2Ｒｕ2Ｏ7系の抵抗を形成しようと
すると導体が酸化してしまうという問題がある。The ceramic circuit board of the present invention may be a single layer or multiple layers as long as it uses ceramics as an insulator. In the case of a multilayer ceramic circuit board, the manufacturing method thereof is a green sheet laminating method or a green sheet printing method. There is a law. Further, a circuit board having only one surface or a double-sided circuit board may be used. The ceramic material used in the present invention is not particularly limited, and alumina (Al 2 O 3 ),
Examples thereof include aluminum nitride (AlN), silicon carbide (SiC), and various ceramics containing these as a main component. or,
A low temperature fired ceramic in which glass powder is mixed with alumina powder can also be used. The conductor material used for the inner layer differs depending on the substrate material, and refractory metals such as molybdenum and tungsten are used for alumina and aluminum nitride. For substrate materials that can be baked at relatively low temperatures,
Metals such as gold, silver, silver-palladium alloy, copper and nickel are used. One of the co-firing ceramic circuit boards that co-fires the ceramic green sheet and the conductor paste for wiring. W or Mo is used as a wiring conductor for a substrate such as alumina or aluminum nitride, and it is used in a reducing atmosphere so that the conductor does not oxidize. There are ceramic circuit boards that are co-fired. However, when attempting to form a highly reliable RuO 2 series or Bi 2 Ru 2 O 7 series resistor that needs to be fired in an oxidizing atmosphere, there is a problem that the conductor is oxidized.
【０００９】これに対して、Ａｇ、Ａｇ−Ｐｄ、Ａｇ−
Ｐｔ、Ａｇ−Ｐｄ−Ｐｔなどの導通抵抗が小さく、酸化
焼成が可能なＡｇ系導体を使用し、これらの導体材料の
融点（９００〜１２００℃）以下で焼成できるセラミッ
ク材料を絶縁体として用いた低温焼成セラミック多層配
線基板が開発されており、本発明のセラミック基板とし
て特に好ましい。一般に約１２００℃以下で焼成される
セラミック基板を低温焼成セラミック基板といい、導体
として内層および表層にＡｇ系またはＣｕ系等が用いら
れる。このように低温焼成セラミック絶縁体材料として
は、内蔵する例えばＡｇ系導体材料の融点よりも低い温
度で焼成できるものを使用するのが好ましい。Ａｇ導体
やＰｄおよびＰｔの含有率の低いＡｇ合金系導体を使用
する場合には、それらの多層に形成される金属の融点が
約９００〜１２００℃と低いので、８００〜１１００℃
で焼成できる材料を使用する必要があり、代表的なもの
としては、ホウケイ酸ガラスやさらに数種類の酸化物
（例えばＭｇＯ，ＣａＯ，Ａｌ2Ｏ3，ＰｂＯ，Ｋ2Ｏ，
Ｎａ2Ｏ，ＺｎＯ，Ｌｉ2Ｏなど）を含むガラス粉末とア
ルミナ、石英などのセラミック粉末の混合物を原料とす
るものや、コージエライト系、αスポジュメン系の結晶
化が生じるガラス粉末を原料とするものがある。On the other hand, Ag, Ag-Pd, Ag-
An Ag-based conductor such as Pt or Ag-Pd-Pt having a low conduction resistance and capable of being oxidized and fired was used, and a ceramic material capable of firing at a melting point (900 to 1200 ° C) or less of these conductor materials was used as an insulator. A low temperature fired ceramic multilayer wiring board has been developed and is particularly preferred as the ceramic board of the present invention. Generally, a ceramic substrate that is fired at about 1200 ° C. or less is called a low temperature fired ceramic substrate, and an Ag-based or Cu-based material is used for the inner layer and the surface layer as a conductor. As described above, it is preferable to use, as the low temperature fired ceramic insulator material, one that can be fired at a temperature lower than the melting point of the built-in Ag-based conductor material, for example. When an Ag conductor or an Ag alloy-based conductor having a low Pd and Pt content is used, the melting point of the metal formed in these multilayers is as low as about 900 to 1200 ° C, so 800 to 1100 ° C.
It is necessary to use a material that can be fired at, and typically, borosilicate glass and several kinds of oxides (for example, MgO, CaO, Al 2 O 3 , PbO, K 2 O,
A mixture of glass powder containing Na 2 O, ZnO, Li 2 O, etc.) and a ceramic powder of alumina, quartz, etc. as a raw material, or a cordierite-based or α-spodumene-based glass powder as a raw material. There is.
【００１０】かかる材料は上記のように単層としても用
いることができるが、積層して多層基板とするために
は、グリーンシートを使用したグリーンシート積層法が
用いられる。例えば、セラミック絶縁体材料粉末に溶
剤、樹脂等を加え、ドクターブレード法により成形し、
厚み０．１〜０．５ｍｍ程度のグリーンシートを得る。
そして必要な配線パターンをＡｇ、Ａｇ−Ｐｄ、Ａｇ−
Ｐｔ、Ａｇ−Ｐｄ−Ｐｔなどの導体材料ペーストを使用
してスクリーン印刷する。また、他の導体層が接続でき
るように、打ち抜き金型やパンチングマシーンでグリー
ンシートに０．１〜２．０ｍｍφ程度の貫通スルーホー
ルを形成する。配線用ビアホールにはＡｇ系導体材料を
充填しておく。同様の方法で回路を形成するのに必要な
だけ、他のグリーンシートにも配線パターンを印刷す
る。これらのグリーンシートを各グリーンシートに穴明
けした位置決め穴を用いて正確に積層した後、８０〜１
５０℃、１０〜２５０ｋｇ／ｃｍ2の条件で熱圧着し一
体化する。回路に内部抵抗を含む場合には、酸化雰囲気
で焼成されるＲｕＯ2，Ｂｉ2Ｒｕ2Ｏ7系の抵抗を形成す
る。その場合には抵抗用電極とともに内層用グリーンシ
ートに印刷しておく。Although such a material can be used as a single layer as described above, a green sheet laminating method using a green sheet is used for laminating a multilayer substrate. For example, solvent, resin, etc. are added to the ceramic insulator material powder, and molding is performed by the doctor blade method,
A green sheet having a thickness of about 0.1 to 0.5 mm is obtained.
Then, the required wiring patterns are Ag, Ag-Pd, Ag-
Screen printing using a conductor material paste such as Pt, Ag-Pd-Pt. Further, through holes having a diameter of about 0.1 to 2.0 mm are formed in the green sheet by a punching die or a punching machine so that other conductor layers can be connected. The via hole for wiring is filled with an Ag-based conductor material. Print wiring patterns on other green sheets as necessary to form a circuit in the same manner. After accurately stacking these green sheets on each green sheet using the drilled positioning holes, 80-1
Thermocompression bonding is performed under the conditions of 50 ° C. and 10 to 250 kg / cm 2 to be integrated. When the circuit includes an internal resistance, a RuO 2 , Bi 2 Ru 2 O 7 based resistance that is fired in an oxidizing atmosphere is formed. In that case, it is printed on the inner layer green sheet together with the resistance electrode.
【００１１】以上のようにしたものを酸化雰囲気で同時
焼成し、導体内蔵セラミック多層基板を得る。以上、低
温焼成セラミックを例にして説明したが、これらは本発
明の好ましい態様であるが、これに限定されるものでは
ない。本発明において用いられる抵抗体は、ＲｕＯ2系
やＢｉ2Ｒｕ2Ｏ7系の電気抵抗成分とガラス成分からな
るものであり、ペースト状でセラミック回路基板に厚膜
法で、通常は印刷される。印刷された抵抗体の上にオー
バーコートガラス成分、例えばＣａＯ−Ａｌ2Ｏ3−Ｓｉ
Ｏ2−Ｂ2Ｏ3系のガラスがやはり厚膜法で、通常は印刷
される。そして、本発明においてはこれら抵抗体とオー
バーコートガラスは同時焼成される。この焼成は通常の
空気中で行われる。The above-described products are co-fired in an oxidizing atmosphere to obtain a ceramic-embedded ceramic multilayer substrate. Although the low temperature fired ceramics have been described above as an example, these are preferred embodiments of the present invention, but the present invention is not limited thereto. The resistor used in the present invention is composed of a RuO 2 -based or Bi 2 Ru 2 O 7 -based electrical resistance component and a glass component, and is normally printed on a ceramic circuit board by a thick film method in a paste form. . Overcoat glass component over the printed resistor, for example, CaO-Al 2 O 3 -Si
In O 2 -B 2 O 3 based glass still thick film methods, usually printed. Then, in the present invention, these resistors and the overcoat glass are co-fired. This firing is performed in normal air.
【００１２】[0012]
【実施例】本発明を実施例及び比較例によって更に詳し
く説明する。セラミック回路基板は以下の方法によって
作成された低温焼成セラミックを用いた。重量組成がＣ
ａＯ２７％、Ａｌ2Ｏ3５％、ＳｉＯ2５９％、Ｂ2Ｏ3９
％であるガラス粉末６０重量％と平均粒径１．０μｍの
Ａｌ2Ｏ3粉末４０重量％を混合して粉末成分とした。EXAMPLES The present invention will be described in more detail with reference to Examples and Comparative Examples. As the ceramic circuit board, a low temperature fired ceramic produced by the following method was used. Weight composition is C
aO27%, Al 2 O 3 5 %, SiO 2 59%, B 2 O 3 9
% Of glass powder and 40% by weight of Al 2 O 3 powder having an average particle size of 1.0 μm were mixed to obtain a powder component.
【００１３】セラミックグリーンシートは上記粉末成分
と重量比でアクリル樹脂１０％、トルエン３０％、イソ
プロピルアルコール１０％及びジブチルフタレート５％
をボールミルで混合し、ドクターブレード法にて膜厚
０．４ｍｍのグリーンシートを作成した。次いでこのグ
リーンシートに金型で所定の位置に穴をあけ、Ａｇペー
ストを穴にスクリーン印刷法で充填した。乾燥後Ａｇペ
ーストで配線パターンをスクリーン印刷法で形成した。
同様の方法で他の配線パターンの印刷されたグリーンシ
ートを作成し、所定の層に重ね合せ熱圧着した。この積
層体を９００℃２０分ホールドで焼成し、セラミック回
路基板を得た。このセラミック基板に表１に示される組
成の抵抗体を抵抗体部が巾１ｍｍ、長さ２ｍｍになるよ
うに印刷した。オーバーコート材料としては、表２のＡ
〜Ｈに示されるガラス組成と屈伏点を有するものにＡｌ
2Ｏ3粉末を混合したものを上記抵抗体上に印刷した。The ceramic green sheet comprises acrylic resin 10%, toluene 30%, isopropyl alcohol 10% and dibutyl phthalate 5% in weight ratio with the above powder components.
Were mixed by a ball mill, and a green sheet having a film thickness of 0.4 mm was prepared by a doctor blade method. Next, a hole was formed at a predetermined position in the green sheet with a mold, and the Ag paste was filled in the hole by a screen printing method. After drying, a wiring pattern was formed by a screen printing method using Ag paste.
A green sheet on which another wiring pattern was printed was prepared by the same method, and was laminated on a predetermined layer and thermocompression bonded. This laminated body was baked at 900 ° C. for 20 minutes to obtain a ceramic circuit board. A resistor having the composition shown in Table 1 was printed on this ceramic substrate so that the resistor portion had a width of 1 mm and a length of 2 mm. As the overcoat material, A in Table 2
To H having a glass composition and a yield point shown in FIG.
A mixture of 2 O 3 powder was printed on the resistor.
【表１】 [Table 1]
【表２】 これらの抵抗体とオーバーコートガラスを各種組み合わ
せたものを８９０℃で１０分間、空気中で同時焼成し
た。なお、表１に示す抵抗体材料のＲｕＯ2の割合とは
ガラス成分を含めた抵抗体の全量に対する重量％であ
り、同じくＡｇの割合も、ガラス成分、ＲｕＯ2を含め
た抵抗体全量に対する重量％である。ここで、表３に示
す負荷テストとは１／３２Ｗの負荷を連続して１０００
時間与えたときの抵抗値の変化率の最大のものである。[Table 2] Various combinations of these resistors and overcoat glass were co-fired in air at 890 ° C. for 10 minutes. The ratio of RuO 2 in the resistor material shown in Table 1 is% by weight with respect to the total amount of the resistor including the glass component. Similarly, the ratio of Ag is also the weight with respect to the total amount of the resistor including the glass component and RuO 2. %. Here, the load test shown in Table 3 means that a load of 1/32 W is continuously measured for 1000
It is the maximum rate of change of resistance value when time is given.
【００１４】[0014]
【表３】 [Table 3]
【００１５】表３には、抵抗体１〜２４とオーバーコー
トガラスＡ〜Ｈを組み合せた場合の負荷テストの結果が
抵抗値の変化率の最大値を示し、又、表４は抵抗断面を
電子顕微鏡で観察し、３００μｍ×１５μｍの断面に含
まれる直径５μｍ以上の気泡の数を示している。Table 3 shows the maximum value of the change rate of the resistance value in the load test results when the resistors 1 to 24 and the overcoat glasses A to H are combined, and Table 4 shows the resistance cross section in the electronic section. Observation with a microscope shows the number of bubbles having a diameter of 5 μm or more included in a cross section of 300 μm × 15 μm.
【００１６】[0016]
【表４】 表３及び表４の抵抗体１〜２４とオーバーコートガラス
Ａ〜Ｈの組み合せにおいて、抵抗体のガラスの屈伏点が
オーバーコートガラスの屈伏点以下である本願発明の実
施例は、Ａの１〜１４、Ｂの３〜８、１３、１４、Ｃの
１〜１４、Ｄの３〜８、１１〜１４、Ｅの３〜８、１１
〜１４、Ｆの１〜１４、１６、１８、２１、２３、Ｇの
１〜１４、Ｈの５〜８、１３、１４である。又、Ａｇを
１．０％以上添加することにより、抵抗体の屈伏点から
１０℃低くした温度と同等の効果を奏するものの実施例
は、Ａの１５、１７、１９、２０、２２、２４、Ｂの１
５、１７、１９、２０、２２、２４、Ｃの１５、１７、
１９、２０、２２、２４、Ｄの１５、１７、１９、２
０、２２、２４、Ｅの１５、１７、１９、２０、２２、
２４、Ｆの１５、１７、１９、２０、２２、２４、Ｇの
１５、１７、１９、２０、２２、２４、Ｈの１７、２４
である。上記のもの以外は本願発明の比較例である。表
３及び４より、例えばオーバーコートガラスＧを用いた
場合には、抵抗体１〜１４との組み合せ例より、抵抗体
のガラスの屈伏点がオーバーコートガラスの屈伏点と同
等又は以下である時、抵抗体の焼結の方が早いため気泡
の数が非常に少なく、変化率が１％以下と負荷テストが
良好であることがわかる。なお、一般に厚膜抵抗の信頼
性の評価として、加速試験で±１％以内というのが目安
になっている。又、例えば、抵抗体１５、１７及び１
９、２０、２２、２４の組み合せ例と比較例である抵抗
体１６及び１８、２１、２３との組み合せ例を比較する
ことにより、Ａｇを添加することにより、抵抗体の焼結
を促進し、その結果、発生する泡の数がゼロか非常に少
ないため負荷テストが良好であることがわかる。Ａｇを
１．０％以上添加することにより、抵抗体の焼結の促進
は屈伏点から１０℃低くした温度と同等の効果があるこ
とが分かる。１０％より多くなるとＡｇの粒子が析出し
て抵抗値が低くなる。[Table 4] In the combinations of the resistors 1 to 24 and the overcoat glasses A to H in Tables 3 and 4, the glass of the resistor has a sag point equal to or lower than the sag point of the overcoat glass. 14, B 3-8, 13, 14, C 1-14, D 3-8, 11-14, E 3-8, 11
.About.14, F 1 to 14, 16, 18, 21, 23, G 1 to 14 and H 5 to 8, 13, 14. Further, by adding 1.0% or more of Ag, the same effect as the temperature 10 ° C. lower than the sag point of the resistor is obtained, but Examples are 15, 17, 19, 20, 22, 24 of A. 1 of B
5, 17, 19, 20, 22, 24, C 15, 17,
19, 20, 22, 24, D 15, 17, 19, 2,
0, 22, 24, E 15, 17, 19, 20, 22,
24, F 15, 17, 19, 20, 22, 24, G 15, 17, 19, 20, 22, 24, H 17, 24
Is. Except for the above, comparative examples of the present invention. From Tables 3 and 4, for example, when overcoat glass G is used, according to the combination example with resistors 1 to 14, when the sag point of the glass of the resistor is equal to or less than the sag point of the overcoat glass. It can be seen that the resistance test is faster and the number of bubbles is very small, and the rate of change is 1% or less, and the load test is good. In general, as a standard for evaluating the reliability of thick film resistance, an acceleration test is within ± 1%. Also, for example, resistors 15, 17 and 1
By comparing the combination example of 9, 20, 22, 24 and the combination example of the resistors 16 and 18, 21, 23 which is a comparative example, by adding Ag, the sintering of the resistor is promoted, As a result, it can be seen that the load test is good because the number of bubbles generated is zero or very small. It can be seen that, by adding 1.0% or more of Ag, the promotion of sintering of the resistor has the same effect as the temperature lowered by 10 ° C. from the yield point. When it is more than 10%, Ag particles are precipitated and the resistance value becomes low.
【００１７】[0017]
【発明の効果】以上の通り、本発明によれば低気泡の外
部抵抗体とそれと同時焼成されたオーバーコートを有す
るセラミック回路基板が得られ、トリミング後の抵抗体
の保護が十分であり、耐候性、安定性に優れた低抗性能
を発揮するものである。As described above, according to the present invention, a ceramic circuit board having a low-bubble external resistor and an overcoat co-fired with the external resistor can be obtained, the resistor after trimming is sufficiently protected, and the weather resistance is improved. It exhibits low resistance and excellent stability and stability.
【図１】従来の外部抵抗体を説明する図、FIG. 1 is a diagram illustrating a conventional external resistor,
【図２】図１の断面図。FIG. 2 is a sectional view of FIG.
１ セラミック基板 ２ 表面導体 ３ 外部抵抗体 ４ オーバーコートガラス ５ トリミング溝 ６ 気泡 ７ 外部抵抗体 1 Ceramic Substrate 2 Surface Conductor 3 External Resistor 4 Overcoat Glass 5 Trimming Groove 6 Bubble 7 External Resistor
Claims (5)
焼成してなる外部抵抗体を有するセラミック回路基板に
おいて、該外部抵抗体は低気泡性抵抗体を有することを
特徴とするセラミック回路基板。1. A ceramic circuit board having an external resistor formed by simultaneously firing a resistor and an overcoat glass, wherein the external resistor comprises a low-bubble resistor.
量が０〜１％であり、該抵抗体のガラスの屈伏点が上記
オーバーコートガラスの屈伏点以下であることを特徴と
する請求項１記載のセラミック回路基板。2. The content of the Ag-based component contained in the resistor is 0 to 1%, and the sag point of the glass of the resistor is equal to or lower than the sag point of the overcoat glass. Item 2. A ceramic circuit board according to item 1.
し、該抵抗体のガラスの屈伏点の１０℃低い温度が、上
記オーバーコートガラスの屈伏点以下であることを特徴
とする請求項１記載のセラミック回路基板。3. The resistor contains 1% or more of an Ag-based component, and the temperature at which the glass yield point of the resistor is lower by 10 ° C. is not more than the yield point of the overcoat glass. Item 2. A ceramic circuit board according to item 1.
2Ｏ3−ＳｉＯ2−Ｂ2Ｏ3系ガラスであることを特徴とす
る請求項１記載のセラミック回路基板。4. The glass component of the resistor is CaO-Al.
Ceramic circuit board according to claim 1, characterized in that the 2 O 3 -SiO 2 -B 2 O 3 based glass.
Ｏ−Ａｌ2Ｏ3−ＳｉＯ2−Ｃｒ2Ｏ3−Ｂ2Ｏ3系ガラス粉
末６０〜９０重量％とアルミナ粉末１０〜４０重量％を
含有し、かつガラスの屈伏点が７２０〜７４０℃である
ことを特徴とする請求項１記載のセラミック回路基板。5. The component of the overcoat glass is Ca
O-Al 2 O 3 -SiO 2 -Cr 2 O 3 -B 2 O 3 system containing glass powder 60 to 90 wt% and 10-40 wt% of alumina powder, and deformation point of the glass is at seven hundred twenty to seven hundred forty ° C. The ceramic circuit board according to claim 1, wherein the ceramic circuit board is provided.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP07049723A JP3093601B2 (en) | 1994-09-28 | 1995-03-09 | Ceramic circuit board |
| DE1995628802 DE69528802T2 (en) | 1994-09-28 | 1995-09-26 | Resistance on a ceramic plate |
| EP19950115134 EP0704864B1 (en) | 1994-09-28 | 1995-09-26 | Resistor on a ceramic circuit board |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23336594 | 1994-09-28 | ||
| JP6-233365 | 1994-09-28 | ||
| JP07049723A JP3093601B2 (en) | 1994-09-28 | 1995-03-09 | Ceramic circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08153945A true JPH08153945A (en) | 1996-06-11 |
| JP3093601B2 JP3093601B2 (en) | 2000-10-03 |
Family
ID=26390169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP07049723A Expired - Lifetime JP3093601B2 (en) | 1994-09-28 | 1995-03-09 | Ceramic circuit board |
Country Status (3)
| Country | Link |
|---|---|
| EP (1) | EP0704864B1 (en) |
| JP (1) | JP3093601B2 (en) |
| DE (1) | DE69528802T2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005129918A (en) * | 2003-09-29 | 2005-05-19 | Ngk Spark Plug Co Ltd | Ceramic substrate for thin film electronic component and thin film electronic component using this |
| JP2005126322A (en) * | 2003-09-29 | 2005-05-19 | Ngk Spark Plug Co Ltd | Ceramic substrate for thin film electronic component, method for producing the same, and thin film electronic component employing the substrate |
| JP2010514175A (en) * | 2006-12-21 | 2010-04-30 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for producing electrical resistance on a substrate |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH068801U (en) * | 1991-10-29 | 1994-02-04 | 自動車電機工業株式会社 | Actuator |
| KR100516043B1 (en) * | 1997-03-06 | 2005-09-26 | 라미나 세라믹스, 인크. | Ceramic multilayer printed circuit boards with embedded passive components |
| US6259151B1 (en) * | 1999-07-21 | 2001-07-10 | Intersil Corporation | Use of barrier refractive or anti-reflective layer to improve laser trim characteristics of thin film resistors |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT967290B (en) * | 1972-09-08 | 1974-02-28 | S E C I Spa | ELECTRIC RESISTOR AND MANUFACTURING PROCEDURE |
| JPS56147405A (en) * | 1980-04-17 | 1981-11-16 | Matsushita Electric Ind Co Ltd | Method of manufacturing thick film varistor |
| JPH01120003A (en) * | 1987-11-02 | 1989-05-12 | Narumi China Corp | Thick film resistor composite |
| JPH01212402A (en) * | 1988-02-19 | 1989-08-25 | Toyobo Co Ltd | Thick film resistor sintering paste |
| JP2644017B2 (en) * | 1988-12-12 | 1997-08-25 | 昭和電工株式会社 | Resistance paste |
-
1995
- 1995-03-09 JP JP07049723A patent/JP3093601B2/en not_active Expired - Lifetime
- 1995-09-26 DE DE1995628802 patent/DE69528802T2/en not_active Expired - Lifetime
- 1995-09-26 EP EP19950115134 patent/EP0704864B1/en not_active Expired - Lifetime
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005129918A (en) * | 2003-09-29 | 2005-05-19 | Ngk Spark Plug Co Ltd | Ceramic substrate for thin film electronic component and thin film electronic component using this |
| JP2005126322A (en) * | 2003-09-29 | 2005-05-19 | Ngk Spark Plug Co Ltd | Ceramic substrate for thin film electronic component, method for producing the same, and thin film electronic component employing the substrate |
| JP2010514175A (en) * | 2006-12-21 | 2010-04-30 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for producing electrical resistance on a substrate |
| JP4763833B2 (en) * | 2006-12-21 | 2011-08-31 | ローベルト ボツシユ ゲゼルシヤフト ミツト ベシユレンクテル ハフツング | Method for manufacturing electrical resistance on a substrate and substrate with current sensor resistance |
| US8115589B2 (en) | 2006-12-21 | 2012-02-14 | Robert Bosch Gmbh | Method for producing an electrical resistor on a substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0704864A2 (en) | 1996-04-03 |
| EP0704864B1 (en) | 2002-11-13 |
| DE69528802D1 (en) | 2002-12-19 |
| EP0704864A3 (en) | 1996-10-23 |
| DE69528802T2 (en) | 2003-04-10 |
| JP3093601B2 (en) | 2000-10-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3331083B2 (en) | Low temperature firing ceramic circuit board | |
| KR900004379B1 (en) | Multilayer ceramic substrate and method of making the same | |
| JP7569018B2 (en) | Ceramic wiring board, ceramic green sheet for ceramic wiring board, and glass ceramic powder for ceramic wiring board | |
| JP3019136B2 (en) | Thick film paste and ceramic circuit board using the same | |
| JP3093601B2 (en) | Ceramic circuit board | |
| US5955938A (en) | RuO2 resistor paste, substrate and overcoat system | |
| JP3630372B2 (en) | Multilayer ceramic substrate and manufacturing method thereof | |
| JP2872273B2 (en) | Ceramic substrate material | |
| JP3093602B2 (en) | Manufacturing method of ceramic circuit board | |
| JP3258231B2 (en) | Ceramic circuit board and method of manufacturing the same | |
| JP3130914B2 (en) | Multilayer circuit board | |
| JPH09298368A (en) | Ceramic wiring board | |
| JP4643778B2 (en) | Circuit board using glass ceramic composition and manufacturing method thereof | |
| JP2001072473A (en) | Production of ceramic substrate | |
| JPH01166599A (en) | Manufacture of laminated ceramic substrate | |
| JP2002076609A (en) | Circuit board | |
| JPH11186727A (en) | Wiring board and manufacture thereof | |
| JP2615970B2 (en) | Method for manufacturing an AＮN multilayer substrate in which conductors and resistors are wired inside | |
| JPH0612911A (en) | Conductive composition and multilayer circuit board | |
| JP2004119547A (en) | Ceramic wiring board and its manufacturing method | |
| JPH06104575A (en) | Ceramic circuit board provided with resistor | |
| JP2001102695A (en) | Ceramic circuit board and manufacturing method therefor | |
| JP4658465B2 (en) | Glass ceramic multilayer wiring board with built-in capacitor | |
| JPH06232528A (en) | Hybrid integrated circuit board and manufacture thereof | |
| JPH088505A (en) | Low temperature fired ceramic circuit board and manufacture thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20080728 Year of fee payment: 8 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090728 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090728 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100728 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100728 Year of fee payment: 10 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110728 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110728 Year of fee payment: 11 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120728 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130728 Year of fee payment: 13 |
|
| EXPY | Cancellation because of completion of term |