JPS59165437A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the breakage of wiring in case of multi-layer wiring by forming the steps-shaped wiring by use of isotropic etching and anisotropic etching. CONSTITUTION:An SiO2 film 12, an Al/Si layer 13 and an Si3N4 film 14 are formed on an Si substrate 11. The Si3N4 film 14 is etched by CDE method using a resist pattern 15 as a mask, thereby forming an Si3N4 film pattern 16 which is smaller than the pattern 15 in size. The Al/Si layer 13 is etched by RIE method to form an Al/Si layer pattern 17. The Al/Si layer pattern 17 is etched and about a half of the film thickness of it is removed by RIE method using the pattern 16 as a mask, thereby forming a wiring 18 which is the first layer of steps-shape. When a wiring 20 as a second layer is formed through an SiO2 film 19, the film 19 can be formed smoothly. Thus it is possible to prevent breakage of the wiring 20 as the second layer caused by difference in level of the wiring 18 as the first layer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device with improved wiring shape.

[Technical background of the invention and its problems]

As is well known, recently, the integration and density of devices has increased,
・Mother turn rule is example t [3.0μ for 64kd-RAM
m, 256 k dRAM has been miniaturized to 2.0 μm. Furthermore, with the miniaturization, there has been a remarkable progress in the growth, and patterning using wet etching has shifted to patterning using reactive ion etching (RIE) K, which has no difference in pattern conversion. Similarly, ht, ht
When forming gold alloy wiring, it is possible to perform RIE processing in a (cct4+ct2) gas/atmosphere, and the wiring, width, and wiring spacing can be turned up to 2.0 μm.

Conventionally, semiconductor devices using RIE have been manufactured by the method shown in FIG. First, for example, 5
After forming the i02 film 2, for example, At/Si is deposited on the entire surface to form an htlst layer (not shown). Next, after forming a resist pattern 3 on a predetermined portion of the Atys layer, using this pattern 3 as a mask,
RIE the t/Si layer in a (CCt4+C22) gas atmosphere
The wiring 4 made of At/Si is removed by anisotropic etching, and a semiconductor device is manufactured.

However, according to the above-mentioned manufacturing method, At/Si
Because RIE is used to form the wiring 4, the cross-sectional shape of the wiring 4 becomes steep, and when a second layer of wiring is formed on the wiring 4 through the glabella insulating film, breaks occur. There was a problem. That is, in the case of a single-layer wiring, the cross-sectional shape does not matter, since after forming the wiring 4, a printing film is simply formed on the entire surface. On the other hand, as recent LSIs require high speed performance and it becomes necessary to lower the resistance value of wiring, the demand for two-layer wiring has become stronger.

Therefore, after forming the first layer of steep wiring, an interlayer insulating film is formed on the entire surface, and two
When the second layer wiring was formed, a break occurred in the second layer wiring.

Furthermore, conventionally, semiconductor devices have been manufactured by the method shown in FIG. 2 as another example. This is because the etching selectivity between the A4781 layer and the resist pattern is small, so the At/S1 layer and the Si3N4 film are sequentially formed on the StO□ film 2, and the resist pattern 3 is formed on the 815N4 film. Using this resist/arm turn 3 as a mask, the 513N4 film is etched away using the CDE method to form an Si 3N4 film/f-turn 5, and then an At/Si layer is formed using the same resist/arm turn 3 as a mask. R.I.
In this method, the wiring 4 made of At/81 is formed by etching from EK.

According to such a method, the film 3p of the wiring 4 can be reduced compared to the case of the semiconductor device shown in FIG.

However, similar to the semiconductor device shown in FIG. 1, the problem of disconnection of the second layer wiring could not be solved.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that prevents disconnection of wiring in the case of multilayer wiring.

[Summary of the invention]

In the present invention, after sequentially forming a metal layer and a film on an insulating film on a semiconductor substrate, four turns of resist are formed on the film, and the film is etched away in the same direction using this resist pattern as a mask. A film pattern smaller in size than four turns of the resist is formed, and then the metal layer is anisotropically etched using the same resist/mother turn as a mask and removed by chipping to form a metal layer pattern. After removal, using the film pattern as a mask, the metal layer pattern is anisotropically etched to the middle of the thickness of the metal layer i4 turns to form a step-like wiring, thereby improving the wiring in the case of multilayer wiring. This prevents disconnection.

do.

[1] - First, for example, 510 is placed on the p-type $1 substrate 11.
After forming the two films 1-2, At is applied over the entire surface by sputtering.
/81 was deposited to a thickness of 1. An At/81 layer (metal layer) 13 of OAm was formed. Next, this At/S1 layer 1
3 by low-temperature Gradama method to a thickness of 10.3 as a coating.
A Si, N4 film 14 of μm was formed (Fig. 2(,)
(Illustrated). Next, a resist pattern 15 is formed by photolithography on a portion of the Si, N4 film 14 corresponding to a portion where wiring is to be formed, and then the Si, N4 film 14 is subjected to CDE using the resist pattern 15 as a mask. It was removed by etching. As a result, S under the resist pattern 15
The i3N4 film 14 was etched in the side direction by about 0.3 μm on one side, and a 513N4 film pattern 16 smaller in size than the resist pattern 15 was formed (as shown in FIG. 2(b)).

Note that the amount of etching in the side direction can be further increased by continuing etching, and can be controlled by changing the etching time.

[:ii:l Next, using the resist pattern 15 as a mask, the p AtlSt layer 13 was etched away by the RIIE method to form a steep At/S single layer mother turn 17 (as shown in FIG. 2(c)). ). Note that the 9th turn 17 of the At/St layer is etched by the RIF method, so
It was formed in the same shape as the resist pattern 15. Subsequently, the resist layer 15 was peeled off (as shown in FIG. 2(d)). Next, using the Si 3N4 film pattern 16 as a mask, the At/St layer turn 17 is etched away by RIE to about half the film thickness of the At/St layer turn 17 to form a step-like pattern made of At/S1. The first layer of wiring 18 was formed (as shown in FIG. 2(, )).

Thereafter, after removing the Sl and N4 film patterns 16, a SiO2 film 19 is formed on the entire surface as an interlayer insulating film, and a second layer of At is formed on the 5in2 film 19 corresponding to the wiring 18i.
/sx was formed, and a semiconductor device was manufactured (FIG. 3 (f>illustrated)).

Thus, according to the invention, the regimen) zJ? turn 1
After etching and removing the At/81 layer 13 by RIE using No. 5 as a mask to form a kl/81 layer/4' turn 17, a 513N4 layer having a width narrower than that of the resist pattern 15 is etched.
Using the film/f turn slag as a mask, repeat the process by RIE method.
In order to remove the tlst layer/♀ turn 17 by etching about half the film thickness of the A turn 17, a stepped first layer wiring 18 made of At/Si is formed as shown in FIG. I can do it. Therefore, when the second layer wiring 20 is formed on the first layer wiring 18 via the 5102 film 19 as shown in FIG. 3(f)K, sio. The film 19 can be formed smoothly, and the 2N
Breaking of the eye wiring 20 can be prevented.

Further, the mother turn 16 of the 513N4 film is formed by the CDE method using the resist pattern 15 as a mask.
Since the Si3N4 film pattern 1 is formed by etching away the Si3N4 film pattern 1, it is not necessary to change the etching time.
6 can be controlled. Therefore, this S i , the N4 film, and the AL/
By appropriately selecting the etching depth of the Si layer i4 turns 17, various step-like first layer wirings 18 can be formed.

Furthermore, Si3N4 as a coating on the At/S 1 layer 13
If the film 14 is formed by low temperature plasma method, A4781
The layer 13 can be prevented from melting, and the first layer wiring 18 can be formed in a stair-like shape according to the design.

In the above embodiment, the metal layer is A1. /S 1 layer is used, but the present invention is not limited to this, and for example, an At layer, a MoSi layer, etc. may be used.

Further, in the above embodiment, the Si 3N4 film is used as the coating, but the coating is not limited to this, and for example, a Si, 02 film or the like may be used. However, the coating must be selected in consideration of the melting point of the metal layer.

Furthermore, in the above embodiment, a case was described in which a wiring made of At/Si was formed on a p-type Si substrate via a 5102 film, but the invention is not limited to this. The same can be applied to the case where wiring is formed through a film.@ [Effects of the Invention] As detailed above, according to the present invention, a highly reliable semiconductor that prevents wiring breakage when multilayer wiring is formed. 0 which can provide the manufacturing method guarantee of the device.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional semiconductor device, FIG. 2 is a sectional view of another conventional semiconductor device, and FIGS. FIG. 11...p-type Si substrate (semiconductor base), 12...
S102 film, 13...At/S1 layer (metal layer), 1
4...S 13N4 film (coating), 15... Resist pattern, 16...81 N Film pattern, 17...
・Az/st layer arm 4 1, 18.20... wiring, 19... 5102 film.

Claims (1)

[Claims] (1) A step of sequentially forming a metal layer and a film on an insulating film on a semiconductor substrate, a step of forming a resist pattern on the film, and isotropically etching away the film using the resist pattern as a mask. , a step of forming a film pattern with a smaller dimension than the resist/arm turn, and a step of etching away the metal layer anisotropically using the resist pattern as a mask to form four turns of the metal layer;
After removing the resist pattern, using the film pattern as a mask, the metal layer pattern is anisotropically etched to the middle of the thickness of the metal layer or turns to form a stepped wiring. A method for manufacturing a semiconductor device, characterized in that: (2) A method for manufacturing a semiconductor device according to claim 1, characterized in that an At/81 layer is used as the metal layer, and an Si, N4 film formed by a low-temperature plasma method is used as the coating. .