JPS59164969A - Signal generation circuit - Google Patents

Abstract

PURPOSE:To make an efficient analysis using a logic analyzer feasible by setting an address on a specifying means corresponding to a microprogram for a desired analysis. CONSTITUTION:A microprocessor 1 reads out and processes a microprogram stored in a control storage 2. The reading and writing address of the storage 2 is specified by an address signal from a signal line 7. A comparator circuit 10 compares an address specifying signal 9 as output of an address circuit 8 with an address signal 7 sent to the storage 2 and outputs a trigger signal 11 for logic analyzer when both coincide with each other.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention is useful for checking the operation of a signal generating circuit, especially a device controlled by a microprogram, using a so-called logic analyzer, or for analyzing a failure. The present invention relates to a signal generation circuit that generates a signal suitable as a trigger signal for an analyzer.

[Prior art]

When checking the operation of electronic equipment and analyzing failures,
By using a logic analyzer, it is possible to improve the efficiency of analysis, etc. The logic analyzer converts the signal into a logical value of l'' or NOI+, stores it in a storage device within the logic analyzer at predetermined time intervals, and reproduces and displays the stored contents on a cathode ray tube or the like to change the time of the signal. This is a device for checking changes and relationships between signals, and the logic analyzer requires a signal to instruct the logic analyzer to start or end the storage.

The signals mentioned above are usually signals within the circuit of the device under test, but in devices controlled by microprograms, the progress state of control corresponds to the execution steps of the microprogram, and the logic It was often the case that there was no suitable trigger signal in the circuit.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and its object is to install the analyzer in a device controlled by a microprogram, and to cause the above-mentioned blasphemous analyzer to respond when the microprogram executes a predetermined step. An object of the present invention is to provide a signal generation circuit that generates a signal that can be used as a trigger signal to instruct the start or end of storage.

[Summary of the invention]

An object of the present invention is to generate an addressing signal and a trigger signal for a storage device (hereinafter referred to as "control storage") in which a microprogram is stored in a device controlled by a microprogram. This is achieved by a signal generating circuit configured to compare the signal specifying the address where the microprogram is stored and generate the trigger signal when the two match.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of a device suitable for applying the present invention. In the diagram, 1 is my.

2 is a control storage, 3 is a controlled circuit, and C is a circuit that outputs a control signal 6 such as a clock that controls the entire system.

In this device, a microprocessor 1 sequentially reads and processes microprograms stored in a control storage 2, and a controlled circuit 3 receives instructions, data and other data output from the control storage 2. Controlled by signal 5. The read and write addresses of the control storage 2 are designated by address signals sent via the address signal line 7.

FIG. 2 shows an embodiment of the present invention, and shows an example in which the signal generating circuit of the present invention is added to the device shown in FIG. In the figure, symbols 1 to 7 indicate the same components as shown in FIG. 1, and 8G-I! addressing circuit, l
0 indicates a comparison circuit, and 12 indicates a trigger signal output terminal. The comparison circuit 10 compares the address designation signal 9 output from the address circuit 8 with the address signal 7 sent to the control storage 2, and outputs a logic analyzer trigger signal 11 when the two match.

FIG. 3 shows details of the addressing circuit 8 and comparison circuit 10. The addressing circuit 8 includes a plurality of switches 21□, 21 . , ・・・21□
, and a resistor 22 that applies a predetermined voltage when the switch is opened.
, 22 , ...22□, and l
2. Further, the comparison circuit 10 is an exclusive OR circuit 13□
, 13. , . . . 13□, a NOR circuit 14 that outputs the negative of the logical sum thereof, and an AND circuit 15 that eliminates unnecessary signals caused by time lag of the circuits. Further, 16 is a signal for hollowing out used for the AND circuit 15 17 + 171 + . . . 1
7□ is an address signal sent via the address signal line 7.

As mentioned above, in the embodiment circuit shown in FIG. 3, there are 12 signal lines for specifying the address of the control storage 2, and addresses from 0 to 4095 are specified by these lines.

Further, 12 switches are provided corresponding to the 12 signal lines, and the trigger signal 11 is output when the settings of these switches completely match the state of the signal lines. ing.

The functions of the circuit of this embodiment will be explained below.

In devices controlled by microprograms,
The error occurred due to some kind of hardware malfunction or external disturbance.
When Durham outputs an error warning, the error warning can be confirmed, but in many cases it is not clear what the hardware malfunction or disturbance was that caused the error warning to be issued. The address of the control storage where the program routine that outputs the warning is stored is set in the pre-load self-addressing circuit 8, and the measurement probe of the logic analyzer is set to each part of the hardware where the failure is expected to occur. At the same time, a trigger signal probe is connected to the trigger signal output terminal 12.

If you connect as described above and set the logic analyzer to memorize the signal state before the trigger signal is generated,
It becomes possible to record and reproduce the state of the hardware at the time the expected phenomenon occurred.

The signal generating circuit shown in the above embodiment has the advantage that it can be produced relatively inexpensively and can be easily added to an existing device.

〔Effect of the invention〕

As described above, according to the present invention, in a device controlled by a microprogram, the addressing means compares the addressing signal of the control storage with the output of the addressing means, and when the two match, Since a comparison circuit that generates a trigger signal is provided, by setting an address corresponding to the microprogram desired to be analyzed in the addressing means, it becomes possible to efficiently perform analysis using a logic analyzer. This has a remarkable effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a device to which the present invention is applied, FIG. 2 is a block diagram showing an embodiment of the present invention,
Figure 3 is a detailed diagram of the main parts (1: microprocessor, 2: control storage, 32 controlled circuit, 4 = control bone generation circuit, 5:
Data no (sline, 6: control signal, 7: address signal line, 8 near address designation circuit, lO: comparison circuit, 11:
Trigger signal, output terminal for 12-bit signal, 13: exclusive OR circuit, 14: NOR circuit, 15: AND' circuit 0 Figure 1 Figure 2

Claims (1)

[Claims] A device controlled by a microprogram is checked and analyzed by an analysis device, and there is a setting means that can arbitrarily set a data pattern, and a data pattern that appears in the process of executing the program and a value set by the setting means. 1. A signal generating circuit comprising a comparing means for comparing, and configured to output a signal as an external trigger signal for an analysis device when the two match.