JPS59163672A - Processing system of analog signal - Google Patents

Abstract

PURPOSE:To attain the high-speed processing system of an analog signal by providing a shared memory to be accessed from both sides of a CPU and an A/D converter and eliminating the need for an operation processing at the CPU side after the data is written to the shared memory. CONSTITUTION:The shared memory 6 is accessed from the side of a CPU3 and also with the data of an A/D converter 1 as the address signal. The data on the processing result of the signal corresponding in 1:1 to the analog signal input of the converter 1 is operated by the CPU3 and written to the memory 6. Thus the subsequent data given from the converter 1 are used as an address and the operation result corresponding to the analog signal input is read out to a latch driver 10 from the memory 6. Thus an analog signal can be obtained from the signal processing at the output of a D/A converter 5.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on a microcomputer analog 1g method [1m fruO] which performs predetermined digital operations on an analog signal input and outputs it as an analog signal. It is used to digitally control an analog control system using a computer as the control center. The conventional analog signal processing method is
As shown in the figure, an analog-to-digital converter (A/
D converter) 1iC converts the analog No. 18 input into a digital signal [i], passes this digital signal through the entire bus 2, and takes it into the CPU 3. The CPU 3 uses the data in the data area of the memory 4 for the digital signal. A predetermined calculation is performed, and the calculation result is sent from the CPU 3 to the computer 2.
The signal is transferred to a digital-to-analog converter (D, /A converter) 5 via the /A converter 5, and the /A converter 5 converts the calculation result into an analog signal and outputs the result.

These analog signal acquisition, conversion to digital signals, predetermined calculations, conversion to analog signals, and output are repeated for analog signal input, and the processing mode is as shown in FIG. In this case, the analog signal output is taken out after a delay of a time TD approximately determined by the sum of the A/D conversion time TI, the CPU calculation time Tt, and the D/A conversion 1 inter-office T harm after the analog signal is taken in at time l. Ru. This delay between 1f# and TD becomes a problem in control systems that require high floor performance.
/D, D/AU converter and microcomputer (7) ensure responsiveness, but this results in an expensive control device. A shared memory that can be accessed OT from both is provided, and this shared memory IJVc contains an analog signal output data kit that corresponds one-to-one to analog signal input from the CPU.
An analog signal processing method that enables high-speed processing by reading the corresponding digital data from the shared memory using the digital output of the D/D converter as an address in the shared memory and obtaining an analog signal output through the D/A converter. The purpose is to provide.

FIG. 6 is provided in a schematic diagram illustrating one embodiment of the invention. The multiplexer 7 switches between the address data given from the CPU 3 through the entire address bus of the HCPU path line 2 and the address data that becomes the digital data output of the A/D converter 1, and outputs it as the address of the shared memory 6. This switching is controlled by the address switching command S of the control logic 8. The data to be written to the shared memory 6 is sent from the CPU 3 side to the data bus driver/receiver 9 through the data bus 2.
This driver/receiver 9 allows the data in the shared memory 6 to be taken into the CPU side by receiver operation, and the shared memory 1J6vc is given to the driver operation overall control logic 8 when specified by the command DIR. The read data from the shared memory 6 is temporarily sent to the launch driver 10 using the clock CLK from the control logic 8.
The data bx v / of this launch driver 10 is
It is applied as a digital data input to the A converter 5 and output from the converter 5 as a corresponding analog I word.

Shared memory 6 chip select C8, if out buttock R
/W is given from control logic 8. Also,
Variation start signal Sl and end signal S2 of A/D converter 1
The data is exchanged between the control logic 8 and the converter 1. The control logic 8 is given control commands by the CPO 2 through the entire control bus of the pass line 2.

In this configuration, the shared memory 6 becomes accessible from the C and PO2 sides, and the data from the A/D converter 1 becomes accessible as an address signal. Then, the shared memory 6 stores signal processing result data that corresponds one-to-one to the analog signal input of the A/D converter 1.
If 3 is calculated and written once, subsequent A, /D
Using the digital data from the f converter 1 as an address, the calculation result corresponding to the analog signal input is read from the shared memory 6 to the latch dry/<10, and an analog signal of the signal processing result is obtained at the output of the D/Af converter 5. be able to.

For example, when obtaining a value obtained by performing the calculation of analog signal output y Ic y = f (x) on analog signal human power X, the CPU 3 first shares digital data that corresponds one-to-one to analog signal human power X. Memo I) Set 6σ] addend and store y=f(x)fυ performance corresponding to the data in the shared memory 6. Access by address σ). After this, the analog 1g processing command is sent to the CrtJ3H control logic 8, and the multi-flexor 7 is sent to the control logic 8 to select the address of the A/D converter 1 ill VC switching unit 1j.

The shared memory 6 is put into a readout state 1j, and a conversion start signal S1 is given to the A/D converter 1. As a result, A/
The analog signal input to the D converter 1 is treated as address data of the shared memo I36, and the data corresponding to the address 9 is read out from the shared memo 1 to 5) and sent to the driver 10.
K is stored, and an analog signal output signal is taken out by conversion by the D/A converter 5. In parallel, the A/D converter 1
is given a new conversion start signal each time the conversion is completed.

According to the invention 1c, after writing data to the shared memory 6, there is no need for arithmetic processing on the CPUa side, and i/.

Only the conversion processing by the converter 1, the access to the shared memory, and the conversion processing by the D/A converter 5 are performed, allowing high-speed processing. In other words, the more complex the arithmetic processing for analog signal input, the more effective the improvement in processing speed becomes. Also, C.P.
The U side is freed from analog signal processing and can perform processing for other input/output devices in parallel, including the use of data in the shared memory 6 through the driver/receiver 9. Desaru n

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining the entire conventional analog signal processing system, Fig. 2 is a time chart for explaining MJ control of each part in Fig. 1, and Fig. 6 shows an embodiment of the present invention. It is a block diagram, ■...Akalog-digital converter, 2...Pass line, 3...CPU, 4
...Memory, 5...Digital to analog K exchange6.
6... Shared memory, 7... Address bus multi-record length, 8... Control logic, 9... Data bus driver/receiver, 1o... Launch driver. Figure 1 Figure 2

Claims (1)

[Claims] An analog-to-digital converter converts an analog signal input into a corresponding digital signal, and the data specified by the CPU is written by switching between the digital signal of this analog-to-digital converter and the digital signal given from the CPU side. a shared memory having a random access memory configuration, and a digital-to-analog converter that converts the read data of the shared memory into a corresponding analog signal to obtain an analog signal output, and The result of the arithmetic processing is written into the shared memory after waiting for address data that corresponds to the analog signal input VC 1 to 1, and the analog 1
The converted data of the analog-to-digital converter for the input of the signal ``g'' is the address of the shared memory, and the data read from the shared memory is used as the digital input of the digital-to-analog converter. 6-fill method.