JPS59161950A - バツフアメモリ方式 - Google Patents

バツフアメモリ方式

Info

Publication number
JPS59161950A
JPS59161950A JP58036917A JP3691783A JPS59161950A JP S59161950 A JPS59161950 A JP S59161950A JP 58036917 A JP58036917 A JP 58036917A JP 3691783 A JP3691783 A JP 3691783A JP S59161950 A JPS59161950 A JP S59161950A
Authority
JP
Japan
Prior art keywords
transmission information
period
read
transmission
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58036917A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0563979B2 (enrdf_load_html_response
Inventor
Kazuto Takaso
高祖　一人
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58036917A priority Critical patent/JPS59161950A/ja
Publication of JPS59161950A publication Critical patent/JPS59161950A/ja
Publication of JPH0563979B2 publication Critical patent/JPH0563979B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/42—Loop networks
    • H04L12/422—Synchronisation for ring networks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Facsimiles In General (AREA)
  • Small-Scale Networks (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP58036917A 1983-03-07 1983-03-07 バツフアメモリ方式 Granted JPS59161950A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58036917A JPS59161950A (ja) 1983-03-07 1983-03-07 バツフアメモリ方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58036917A JPS59161950A (ja) 1983-03-07 1983-03-07 バツフアメモリ方式

Publications (2)

Publication Number Publication Date
JPS59161950A true JPS59161950A (ja) 1984-09-12
JPH0563979B2 JPH0563979B2 (enrdf_load_html_response) 1993-09-13

Family

ID=12483114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58036917A Granted JPS59161950A (ja) 1983-03-07 1983-03-07 バツフアメモリ方式

Country Status (1)

Country Link
JP (1) JPS59161950A (enrdf_load_html_response)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398742A (en) * 1977-02-09 1978-08-29 Nec Corp Buffer memory circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5398742A (en) * 1977-02-09 1978-08-29 Nec Corp Buffer memory circuit

Also Published As

Publication number Publication date
JPH0563979B2 (enrdf_load_html_response) 1993-09-13

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