JPS59161825A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPS59161825A JPS59161825A JP3857183A JP3857183A JPS59161825A JP S59161825 A JPS59161825 A JP S59161825A JP 3857183 A JP3857183 A JP 3857183A JP 3857183 A JP3857183 A JP 3857183A JP S59161825 A JPS59161825 A JP S59161825A
- Authority
- JP
- Japan
- Prior art keywords
- wafers
- wafer
- photosensitive resin
- semiconductor
- oxygen gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 235000012431 wafers Nutrition 0.000 claims abstract description 72
- 238000000034 method Methods 0.000 claims abstract description 20
- 239000011347 resin Substances 0.000 claims abstract description 18
- 229920005989 resin Polymers 0.000 claims abstract description 18
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims description 13
- 229910001882 dioxygen Inorganic materials 0.000 claims description 13
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 241000257465 Echinoidea Species 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は酸素ガスプラズマを用いて感光性樹脂を除去
するウェハプロセスにおいて、反応器内に挿入されたウ
ェハへの物理的損傷を防止するようにした半導体素子の
製造方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention provides a method for preventing physical damage to wafers inserted into a reactor in a wafer process in which photosensitive resin is removed using oxygen gas plasma. The present invention relates to a method for manufacturing a semiconductor device.
最近の半導体素子、%に:集積回路の高性能化は飛躍的
な進歩があシ、ドライエツチング法あるいはイオン注入
法などのプロセス技術の必要上、感光性樹脂を除去する
ウェハプロセスにおいて、酸素ガスプラズマを用いる方
法が必須の方法として定着している。そして、この種の
感光性樹脂を除去するウェハプロセスでは、その処理能
力あるいは単なる除去作用の目的から複数のウェハを同
時に処理するバッチ方式が用いられる。第1図は従来の
半導体素子の製造方法を示す断面図であ夛、特に感光性
樹脂を除去するウェハプロセスを示す。Recent semiconductor devices: There has been dramatic progress in improving the performance of integrated circuits, and due to the need for process technologies such as dry etching or ion implantation, oxygen gas is used in the wafer process to remove photosensitive resin. A method using plasma has become established as an essential method. In a wafer process for removing this type of photosensitive resin, a batch method is used in which a plurality of wafers are processed simultaneously for the purpose of processing capacity or simply for the purpose of removing the resin. FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, particularly a wafer process in which photosensitive resin is removed.
同図において、(1)は石英製の反応管、(2)は複数
枚のウェハ(3)を支持する石英ガラス製のウェハ架台
、(4)は酸素ガスの導入口、(5)は酸素ガスの排気
口である。In the figure, (1) is a quartz reaction tube, (2) is a quartz glass wafer stand that supports multiple wafers (3), (4) is an oxygen gas inlet, and (5) is an oxygen gas inlet. This is a gas exhaust port.
なお、前記ウェハ(3)に示した矢印はウェハ表面の向
きを示し、ウェハ(3)はすべて一定の方向に向って配
置されている。Note that the arrow shown on the wafer (3) indicates the direction of the wafer surface, and all the wafers (3) are arranged facing in a certain direction.
次に、上記構成による感光性樹脂を除去するウェハプロ
セスでは、例えば周波数13.56 Mn2 。Next, in the wafer process for removing the photosensitive resin with the above configuration, the frequency is, for example, 13.56 Mn2.
放電出力IKW、酸素ガス圧2 Torrの条件下で操
作される。It is operated under the conditions of discharge output IKW and oxygen gas pressure 2 Torr.
しかしながら、従来の半導体素子の製造方法では、極在
するプラズマ放電の不均一にょシ、励起された分子ある
いは電子などの衝撃がウェハ間で不均一になる。この衝
撃にょシ受けるウェハへの物理的損傷によシ、半導体素
子の電気的特性が変化し、ウェハ間での電気的特性が不
均一になる。However, in the conventional semiconductor device manufacturing method, there is extremely non-uniform plasma discharge, and the impact of excited molecules or electrons becomes non-uniform between wafers. Physical damage to the wafers caused by this impact changes the electrical characteristics of the semiconductor elements, resulting in nonuniform electrical characteristics among wafers.
特にMO8型トランジスタを用いた半導体素子ではシリ
コンウェハ基板上のシリコン酸化膜中への影響によシ、
シリコン酸化膜のエネルギー準位を変化させ、代表的な
素子の特性である閾値電圧(VTH)を変化させる。す
なわち、第2図は例えば周波数13.56 MHz 、
放電出力IKW、酸素、/l/ス圧2 Torrの条件
下で、MO8型トランジスタの製造工程中、ゲート用の
シリコン酸化膜生成後、60分間プラズマ放電中に暴露
させたときの閾値電圧(vTa)を、ウェハ架台(2)
上のウェハ(3)の位置によシ、プロットしたものであ
る。この第2図において、横軸の阻1〜Nn25はウェ
ハ架台(2)上のウェハ(3)の順番を示し、縦軸は閾
値電圧(VTR)を示すが、(4)はNチャネルMO8
)ランジスタの場合を示し、(B)はPチャネルMO8
)ランジスタの場合を示す。この第2図によシ、ウェハ
架台(2)上の最も端に位置するNn1のウェハの特性
が異常であることがわかシ、しかも片側端であることが
わかる。In particular, in semiconductor devices using MO8 type transistors, the effect on the silicon oxide film on the silicon wafer substrate causes
The energy level of the silicon oxide film is changed to change the threshold voltage (VTH), which is a characteristic of a typical device. That is, in FIG. 2, for example, the frequency is 13.56 MHz,
The threshold voltage (vTa) when exposed to plasma discharge for 60 minutes after forming a silicon oxide film for the gate during the manufacturing process of an MO8 type transistor under the conditions of discharge output IKW, oxygen, /l/s pressure 2 Torr. ), wafer stand (2)
It is plotted according to the position of the upper wafer (3). In this FIG. 2, the horizontal axis indicates the order of the wafers (3) on the wafer stand (2), and the vertical axis indicates the threshold voltage (VTR), and (4) indicates the N-channel MO8.
) shows the case of transistor, (B) shows P channel MO8
) Indicates the case of a transistor. From FIG. 2, it can be seen that the characteristics of the Nn1 wafer located at the farthest end on the wafer stand (2) are abnormal, and moreover, it is found that it is located at one end.
このように、従来ではウェハ架台(2)上のウェハの位
置が最も端に位置するウェハの閾値電圧(VTH)が変
化する欠点があった。As described above, the conventional method has a drawback that the threshold voltage (VTH) of the wafer located at the end of the wafer on the wafer stand (2) changes.
したがって、この発明の目的は反応器内に挿入された複
数枚のウェハを物理的損傷させることなく、しかもウェ
ハの置かれた位置にかかわらず、すべてのウェハが一定
の閾値電圧(VTR)をもつように形成することができ
る半導体素子の製造方法を提供するものである。Therefore, an object of the present invention is to ensure that all wafers have a constant threshold voltage (VTR) regardless of the position of the wafers, without physically damaging the multiple wafers inserted into the reactor. The present invention provides a method for manufacturing a semiconductor element that can be formed as described above.
このような目的を達成するため、この発明は半導体素子
の製造工程中、酸素ガスプラズマによシ感光性樹脂を除
去する工程において、複数枚のウェハを反応器内に均等
に平行に、かつそのウェア1表面が一方向に向くように
配置すると共に最端部にある1枚のウニノ・のみ、その
ウニノ・表面が内側に向くように配置するものである。In order to achieve such an object, the present invention aims to place a plurality of wafers in a reactor evenly and in parallel in the process of removing photosensitive resin using oxygen gas plasma during the manufacturing process of semiconductor devices. The wear 1 is arranged so that its surface faces in one direction, and only one piece of clothing at the extreme end is arranged so that its surface faces inward.
さらにまた、最端部にあるウニノ・表面に対向して遮蔽
板を配置したものである。以下実施例を用いて詳細に説
明する。Furthermore, a shielding plate is placed opposite the unino surface at the extreme end. This will be explained in detail below using examples.
第3図はこの発明に係る半導体素子の製造方法の一実施
例を示す概略断面図であシ、特にMO8型トランジスタ
の製造工程中、ウニノ・架台(2)に複数枚のウェハ(
3)を配置し、感光性樹脂を除去するウェハプロセスを
示す。この実施例では複数枚のウェハ(3)をウェハ架
台(2)上に均等に平行に、かつそのウェハ表面が一方
向に向くように配置すると共に最端部にある1枚のウェ
ハのみ、そのウェア1表面が内側に向くように配置する
。これによシ、両端のウェハともその表面が内側に向く
ことになる。FIG. 3 is a schematic cross-sectional view showing an embodiment of the method for manufacturing a semiconductor device according to the present invention. In particular, during the manufacturing process of an MO8 type transistor, a plurality of wafers (
3) shows the wafer process for placing and removing the photosensitive resin. In this embodiment, a plurality of wafers (3) are arranged evenly in parallel on a wafer stand (2) with their wafer surfaces facing in one direction, and only one wafer at the end is Place the garment so that the surface of the garment 1 faces inward. This causes the surfaces of the wafers at both ends to face inward.
そして、感光性樹脂を除去する場合、例えば周波数13
.56 Mn2 、放電出力IKW、酸素ガス圧2To
rrの条件下で、MO8型トランジスタの製造工程中、
ゲート用のシリコン酸化膜生成後60分間プラズマ放電
中に暴露させたときの閾値電圧(VTR)をウェハ架台
(2)上のウニノ・(3)の位置によシブロットしたも
のを第4図に示す。この第4図において、横軸の陽1〜
陽25はウェハ架台(2)上のウェハ(3)の順番を示
し、縦軸は閾値電圧(VTR)を示すが、(4)はNチ
ャネルMO8)ランジスタの場合を示し、(B)はPチ
ャネルMO8)ランジスタの場合を示す。この第4図に
よシ、ウェハ架台(2)上に配置された複数枚のウェハ
(3)の感光性樹脂を除去することができ、しかもその
閾値電圧(VTR)をほぼ均一にすることができる。When removing the photosensitive resin, for example, a frequency of 13
.. 56 Mn2, discharge output IKW, oxygen gas pressure 2To
During the manufacturing process of MO8 type transistor under the condition of rr,
Figure 4 shows the threshold voltage (VTR) when exposed to plasma discharge for 60 minutes after the formation of the silicon oxide film for the gate, plotted by the position of Unino (3) on the wafer stand (2). . In this Figure 4, positive 1 to 1 on the horizontal axis
Symbol 25 indicates the order of the wafers (3) on the wafer stand (2), the vertical axis indicates the threshold voltage (VTR), (4) indicates the case of an N-channel MO8) transistor, and (B) indicates the P The case of channel MO8) transistor is shown. According to FIG. 4, it is possible to remove the photosensitive resin from a plurality of wafers (3) placed on the wafer stand (2), and to make the threshold voltage (VTR) almost uniform. can.
第5図は他の実施例を示す概略断面図である。FIG. 5 is a schematic sectional view showing another embodiment.
同図において、(6a)および(6b)は前記ウェハ架
台(2)の両端部に設置した例えば厚さ1stx程度で
、ウェハ(3)の形状とほぼ同一形状の遮蔽板である。In the figure, (6a) and (6b) are shielding plates installed at both ends of the wafer pedestal (2), each having a thickness of, for example, about 1stx, and approximately the same shape as the wafer (3).
なお、この遮蔽板(6龜〉よび(6b)はウェハ(3)
の配置間隔とほぼ同じ間隔で設置した場合を示す。Note that this shielding plate (6) and (6b) are attached to the wafer (3).
This shows the case where they are installed at approximately the same spacing as .
このように、遮蔽板(6a)および(6b)を配置する
ことによシ、例えば周波数13.56 MHz 、放電
出力IKW、酸素ガス圧2Torrの条件下で、MO8
型トランジスタの製造工程中、ゲート用のシリコン酸化
膜生成後、60分間プラズマ放電中に暴露させたとき、
第4図と同様な特性が得られた。このように、ウェハ架
台(2)上に配置された複数枚のウェハ(3)の感光性
樹脂を除去することができ、しかも、その閾値電圧(V
TH)をはソ均一にすることができる。By arranging the shielding plates (6a) and (6b) in this way, for example, under the conditions of frequency 13.56 MHz, discharge output IKW, and oxygen gas pressure 2 Torr, MO8
During the manufacturing process of type transistors, when exposed to plasma discharge for 60 minutes after forming a silicon oxide film for the gate,
Characteristics similar to those shown in FIG. 4 were obtained. In this way, it is possible to remove the photosensitive resin from a plurality of wafers (3) placed on the wafer stand (2), and moreover, the threshold voltage (V
TH) can be made uniform.
なお、上述の実施例では遮蔽板を2枚設けた場合を示し
たが、そのウニ八表面が必ず一定の方向に向くように配
列した場合、例えば図示の方向に配列した場合には遮蔽
板(6b)は必ずしも必要とせず、同様に、図示の方向
の反対の方向に配列する場合には遮蔽板(6a)は必ず
しも必要としないことはもちろんである。また、前記遮
蔽板(6a)、(6b)は着脱自在に設けても、固定し
て設けてもよい。In addition, although the above-mentioned example showed the case where two shielding plates were provided, when the sea urchins are arranged so that their surfaces always face in a certain direction, for example, when they are arranged in the direction shown in the figure, the shielding plates ( 6b) is not necessarily required, and similarly, it goes without saying that the shielding plate (6a) is not necessarily required when arranged in the opposite direction to the direction shown. Further, the shielding plates (6a) and (6b) may be provided removably or may be provided fixedly.
以上詳細に説明したように、この発明に係る半導体素子
の製造工程によれば酸素ガスプラズマを用いた感光性樹
脂を除去するウェハプロセスにおいて、複数枚のウェハ
の特性を均一にすることができるので、高集積度、高性
能化素子のゲート酸化膜の薄膜化など、プラズマ損傷を
受けやすいプロセスに特に効果がある。As explained in detail above, according to the semiconductor device manufacturing process according to the present invention, the characteristics of multiple wafers can be made uniform in the wafer process that uses oxygen gas plasma to remove photosensitive resin. It is particularly effective in processes that are susceptible to plasma damage, such as thinning gate oxide films for highly integrated, high-performance devices.
第1図は従来の半導体素子の製造方法を示す断面図、第
2図は第1図の各ウェハ位置における各ウェハの閾値電
圧(VTR)を示す図、第3図はこの発明に係る半導体
素子の製造方法の一実施例を示す概略断面図、第4図は
第3図の各ウェハ位置における各ウェハの閾値電圧(V
TH)を示す図、第5図は他の実施例を示す概略断面図
である。
+1)・・・・反応管、(2)・・・・ウェハ架台、(
3)・・・・ウェハ、(4j・・・・導入口、(5)・
・・・排気口、(6a) 、 (6b)・・・・遮蔽板
。FIG. 1 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device, FIG. 2 is a diagram showing the threshold voltage (VTR) of each wafer at each wafer position in FIG. 1, and FIG. 3 is a diagram showing a semiconductor device according to the present invention. FIG. 4 is a schematic cross-sectional view showing an example of the manufacturing method of
FIG. 5 is a schematic sectional view showing another embodiment. +1)...Reaction tube, (2)...Wafer stand, (
3)...Wafer, (4j...Inlet, (5)...
...exhaust port, (6a), (6b)...shielding plate.
Claims (2)
シ、半導体ウニ八表面に形成された感光性樹脂を除去す
る工程において、複数枚の上記半導体ウェハを反応器内
に均等に平行に、かつその半導体ウニ八表面が一方向に
向くように配置すると共に最端部にある1枚の半導体ウ
ェハのみ、その半導体ウニ八表面が内側に向くように配
置して、酸素ガスプラズマによシ上記感光性樹脂を除去
することを特徴とする半導体素子の製造方法。(1) During the manufacturing process of semiconductor devices, in the step of removing the photosensitive resin formed on the surface of the semiconductor wafer using oxygen gas plasma, a plurality of semiconductor wafers are placed evenly in parallel in a reactor, The semiconductor wafers are arranged so that their surfaces face in one direction, and only one semiconductor wafer at the end is placed so that its semiconductor wafer faces inward, and the semiconductor wafers are exposed to oxygen gas plasma as described above. A method for manufacturing a semiconductor device, which comprises removing a photosensitive resin.
シ半導体つェ八表面に形成された感光性樹脂を除去する
工程において、複数枚の上記半導体ウェハを反応器内に
均等に平行に、かつその半導体ウェハ表面が一方向に向
くように配置するとともに最端部に位置する半導体ウニ
八表面に対向して遮蔽板を配置して酸素ガスプラズマに
よ〕上記感光性樹脂を除去することを特徴とする半導体
素子の製造方法。(2) During the manufacturing process of semiconductor devices, in the step of removing the photosensitive resin formed on the surface of the semiconductor wafer using oxygen gas plasma, a plurality of semiconductor wafers are placed evenly in parallel in a reactor, In addition, the semiconductor wafer surface is arranged so as to face in one direction, and a shielding plate is arranged opposite to the surface of the semiconductor wafer located at the end, and the photosensitive resin is removed using oxygen gas plasma. Features: A method for manufacturing semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58038571A JPH0656845B2 (en) | 1983-03-07 | 1983-03-07 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58038571A JPH0656845B2 (en) | 1983-03-07 | 1983-03-07 | Method for manufacturing semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59161825A true JPS59161825A (en) | 1984-09-12 |
JPH0656845B2 JPH0656845B2 (en) | 1994-07-27 |
Family
ID=12528976
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58038571A Expired - Lifetime JPH0656845B2 (en) | 1983-03-07 | 1983-03-07 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0656845B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01137529U (en) * | 1988-03-14 | 1989-09-20 |
Citations (6)
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---|---|---|---|---|
JPS511732U (en) * | 1974-06-19 | 1976-01-08 | ||
JPS5143718U (en) * | 1974-09-27 | 1976-03-31 | ||
JPS542670A (en) * | 1977-06-08 | 1979-01-10 | Nec Corp | Plasma etching method |
JPS55169855U (en) * | 1979-05-24 | 1980-12-05 | ||
JPS5735322A (en) * | 1980-08-13 | 1982-02-25 | Fujitsu Ltd | Removal of photo-resist film |
JPS5738920U (en) * | 1980-08-14 | 1982-03-02 |
-
1983
- 1983-03-07 JP JP58038571A patent/JPH0656845B2/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS511732U (en) * | 1974-06-19 | 1976-01-08 | ||
JPS5143718U (en) * | 1974-09-27 | 1976-03-31 | ||
JPS542670A (en) * | 1977-06-08 | 1979-01-10 | Nec Corp | Plasma etching method |
JPS55169855U (en) * | 1979-05-24 | 1980-12-05 | ||
JPS5735322A (en) * | 1980-08-13 | 1982-02-25 | Fujitsu Ltd | Removal of photo-resist film |
JPS5738920U (en) * | 1980-08-14 | 1982-03-02 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01137529U (en) * | 1988-03-14 | 1989-09-20 |
Also Published As
Publication number | Publication date |
---|---|
JPH0656845B2 (en) | 1994-07-27 |
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