JPH05251197A - Dry etching method - Google Patents

Dry etching method

Info

Publication number
JPH05251197A
JPH05251197A JP4050282A JP5028292A JPH05251197A JP H05251197 A JPH05251197 A JP H05251197A JP 4050282 A JP4050282 A JP 4050282A JP 5028292 A JP5028292 A JP 5028292A JP H05251197 A JPH05251197 A JP H05251197A
Authority
JP
Japan
Prior art keywords
power
substrate
etching
dry etching
lower electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4050282A
Other languages
Japanese (ja)
Inventor
Yoshimasa Inamoto
吉将 稲本
Ichiro Nakayama
一郎 中山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4050282A priority Critical patent/JPH05251197A/en
Publication of JPH05251197A publication Critical patent/JPH05251197A/en
Pending legal-status Critical Current

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  • ing And Chemical Polishing (AREA)
  • Drying Of Semiconductors (AREA)
  • Plasma Technology (AREA)

Abstract

PURPOSE:To provide a dry etching method capable of preventing dust generation between a reverse surface of a base plate and an obverse surface of an electrode at the time of etching in an RF power applying method so as to enhance a yield of a product. CONSTITUTION:Required RF power is divided into a plurality of steps up to a predetermined value at the time of application of the RF power, to be increased. After etching, the RF power is divided into a plurality of steps to be decreased, thus obtaining an RF power applying method for stopping electric discharge.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はドライエッチング方法に
関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method.

【0002】[0002]

【従来の技術】近年、半導体デバイスの高性能化,コス
トダウンにともない、そのパターンは微細化されてお
り、この時、基板裏面に付着するダストが、その歩留り
により大きく影響するようになる。
2. Description of the Related Art In recent years, as semiconductor devices have become higher in performance and cost has been reduced, their patterns have been miniaturized. At this time, the dust attached to the back surface of the substrate has a great influence on the yield.

【0003】又、半導体デバイスのコストダウンのた
め、エッチング速度を大きくし、装置の処理能力を上げ
る必要がある。
In order to reduce the cost of semiconductor devices, it is necessary to increase the etching rate and increase the processing capacity of the apparatus.

【0004】そのため、RFパワーをより増加させる方
向にあるが、この時、基板のエッチング処理中の基板温
度の上昇が問題となってくる。これを解決するため電極
表面と基板裏面の密着性を大きくし、電極と基板間の熱
交換を効率よく行う必要がある。
Therefore, there is a tendency to increase the RF power, but at this time, the rise of the substrate temperature during the etching process of the substrate becomes a problem. In order to solve this, it is necessary to increase the adhesion between the front surface of the electrode and the back surface of the substrate and to efficiently perform heat exchange between the electrode and the substrate.

【0005】以下に従来のドライエッチング方法につい
て説明する。図3は従来のドライエッチング方法のRF
パワー印加方法を示す。RFパワーを印加した時、瞬時
に電極には、設定されたRFパワーが印加され、エッチ
ング終了後、RFパワーの供給は停止させる。図2にR
IEドライエッチング装置の反応室の構造を示す。11
は上部対抗電極で、電極下面のシャワー状の穴11aよ
りエッチングガスが供給される。12がRFが印加され
る下部電極で、内部は、冷却水が流れる構造となってい
る。その表面にはアルマイト等の絶縁膜13で被われて
いる。この下部電極12上に基板14を置き、電極12
にRFパワーを印加することで、基板14のエッチング
を行う。15は基板4の搬送のためのエレベーターユニ
ット、16は下部電極12とエッチングチャンバーの間
の絶縁物、17はRFパワーコントローラ、18はRF
パワー電源を示す基板14を置き、下部電極12にRF
パワーを印加した時、基板14は、静電気により帯電
し、この静電気の作用により、基板14は、下部電極1
2上の絶縁膜13の表面に密着し、基板14と下部電極
12との間の熱交換が効率よく行われ、基板14の温度
上昇が抑えられる。
A conventional dry etching method will be described below. FIG. 3 shows RF of a conventional dry etching method.
A power application method will be described. When the RF power is applied, the set RF power is instantly applied to the electrode, and the supply of the RF power is stopped after the etching is completed. R in Figure 2
The structure of the reaction chamber of the IE dry etching apparatus is shown. 11
Is an upper counter electrode, and an etching gas is supplied from a shower-shaped hole 11a on the lower surface of the electrode. Reference numeral 12 is a lower electrode to which RF is applied, and the inside has a structure in which cooling water flows. The surface thereof is covered with an insulating film 13 such as alumite. The substrate 14 is placed on the lower electrode 12,
The substrate 14 is etched by applying RF power to the substrate. Reference numeral 15 is an elevator unit for transferring the substrate 4, 16 is an insulator between the lower electrode 12 and the etching chamber, 17 is an RF power controller, and 18 is RF.
A substrate 14 showing a power source is placed and RF is applied to the lower electrode 12.
When power is applied, the substrate 14 is charged with static electricity, and due to the action of this static electricity, the substrate 14 moves to the lower electrode 1
The heat exchange between the substrate 14 and the lower electrode 12 is efficiently performed by adhering to the surface of the insulating film 13 on the substrate 2, and the temperature rise of the substrate 14 is suppressed.

【0006】[0006]

【発明が解決しようとする課題】しかしながら上記の従
来のドライエッチング方法では、RFパワー印加時に、
急激に基板14が下部電極12に密着する力が発生し、
基板14の裏面と下部電極12上の絶縁膜13の表面が
こすれてダストが発生する。さらに、エッチング終了
後、RFパワーを停止した後も、基板14に帯電した静
電気はそのまま保持されるため、基板14は、下部電極
12上に密着しつづけるが、そのような状態で基板14
の搬送のため、基板搬送用エレベーターユニット15を
作動させた場合、図4に示すように力が基板エレベータ
ーユニットのピン25周辺で発生し、基板14の裏面と
下部電極12上の絶縁膜13表面がこすれて、ダストが
発生する。このようにして発生したダストにより、反応
室内は汚染され以降に処理されるウェハーのダスト源と
なり、又、基板14の裏面に付着したまま装置外に搬出
されたダストは次工程でのダスト源となる。このように
従来のRFパワー印加方法では、デバイスの歩留りに大
きく低下させるという問題が発生していた。
However, in the above-described conventional dry etching method, when RF power is applied,
A force that causes the substrate 14 to adhere to the lower electrode 12 suddenly occurs,
The back surface of the substrate 14 and the surface of the insulating film 13 on the lower electrode 12 are rubbed to generate dust. Furthermore, since static electricity charged on the substrate 14 is retained as it is even after the RF power is stopped after the etching is completed, the substrate 14 continues to adhere to the lower electrode 12 in such a state.
When the elevator unit 15 for transporting the substrate is operated to transport the substrate, a force is generated around the pin 25 of the substrate elevator unit as shown in FIG. 4, and the rear surface of the substrate 14 and the surface of the insulating film 13 on the lower electrode 12 are processed. Scrape and generate dust. The dust thus generated contaminates the reaction chamber and serves as a dust source for wafers to be processed thereafter, and the dust carried out of the apparatus while being attached to the back surface of the substrate 14 serves as a dust source for the next step. Become. As described above, the conventional RF power application method has a problem that the yield of the device is significantly reduced.

【0007】又、エッチング終了後、RFパワーを停止
してからも基板14は下部電極12上に密着しつづける
ため、下部電極12上から基板14が取りはずせず、搬
送不良が頻繁に発生するといった問題も有していた。
Further, after the etching is completed, the substrate 14 continues to adhere to the lower electrode 12 even after the RF power is stopped, so that the substrate 14 cannot be removed from the lower electrode 12 and a defective conveyance frequently occurs. I also had problems.

【0008】本発明は上記従来の問題点を解決するため
のもので、基板14の裏面と下部電極12上の絶縁膜表
面で発生するダストの低減と、基板搬送不良を改善する
ことのできるドライエッチング方法を提供することを目
的とする。
The present invention is intended to solve the above-mentioned conventional problems, and reduces the dust generated on the back surface of the substrate 14 and the surface of the insulating film on the lower electrode 12 and can dry the substrate to improve the transport failure. It is an object to provide an etching method.

【0009】[0009]

【課題を解決するための手段】この目的を達成するため
に本発明のドライエッチング方法は、RFパワー印加時
に、複数のステップに分割して、所定値までRFパワー
を増加する工程と、エッチング終了後、複数のステップ
に分割してRFパワーを減少し、放電を停止する工程と
を有するものである。
To achieve this object, the dry etching method of the present invention comprises a step of increasing the RF power to a predetermined value by dividing the step into a plurality of steps when applying the RF power, and ending the etching. After that, the process is divided into a plurality of steps to reduce the RF power and stop the discharge.

【0010】[0010]

【作用】この方法により、RFパワー印加開始時に基板
が急激に下部電極に密着することがなくなり、その時の
基板の裏面と下部電極の絶縁膜の表面がこすれることに
より発生するダストが低減される。そして、エッチング
終了時も、RFパワーを徐々に下げることにより、帯電
した静電気が放電され、基板と下部電極の密着が解除で
き、基板搬送用エレベーターユニットを作動させた場合
に発生していたダストが低減される。又、この時、基板
と下部電極の密着がなくなるため、基板搬送不良も改善
される。
By this method, the substrate does not suddenly adhere to the lower electrode at the start of application of RF power, and dust generated by rubbing the back surface of the substrate and the surface of the insulating film of the lower electrode at that time is reduced. Even after the etching is completed, by gradually reducing the RF power, the charged static electricity is discharged, the contact between the substrate and the lower electrode can be released, and the dust generated when the substrate transfer elevator unit is operated is generated. Will be reduced. Further, at this time, since the substrate and the lower electrode are not brought into close contact with each other, the defective conveyance of the substrate is also improved.

【0011】[0011]

【実施例】以下本発明の一実施例について図面を参照し
ながら説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

【0012】図1にウェハー上にSiN膜をRIE方式
のドライエッチング装置によりエッチングした時のRF
パワー印加方法を示す。エッチング条件は、RFパワー
は200W、エッチング圧力は400mTon、エッチ
ングガスはCF4/O2=42/8SCCMで、SiNエ
ッチング速度は1500Å/minである。
FIG. 1 shows RF when a SiN film is etched on a wafer by a dry etching apparatus of RIE system.
A power application method will be described. The etching conditions are RF power of 200 W, etching pressure of 400 mTon, etching gas of CF 4 / O 2 = 42/8 SCCM, and SiN etching rate of 1500Å / min.

【0013】RFパワー印加開始時から、30秒で必要
とする200Wまで増加するが、その時の増加量を最初
の10秒で40W、次の10秒で100W、さらに次の
10秒で200WとなるようなRFパワー印加方法とし
た。そして、RFパワー200Wで90秒間エッチング
し、その後、40秒間で、放電を停止させるが、RFパ
ワーを10秒ずつの4ステップに分割し、各ステップで
それぞれ100W,50W,20W,0Wになるように
設定した。
From the start of RF power application, the required power is increased to 200 W in 30 seconds. The amount of increase at that time is 40 W in the first 10 seconds, 100 W in the next 10 seconds, and 200 W in the next 10 seconds. Such an RF power applying method was adopted. Then, etching is performed with RF power of 200 W for 90 seconds, and then discharge is stopped for 40 seconds, but the RF power is divided into four steps of 10 seconds each, and 100 W, 50 W, 20 W, and 0 W are obtained at each step. Set to.

【0014】図3に従来のRFパワー印加方法を示す。
エッチング条件は、前記実施例と同一である。RFパワ
ー印加時に瞬時に200Wになるように設定し、90秒
のエッチング終了後、RF印加を停止した。
FIG. 3 shows a conventional RF power applying method.
The etching conditions are the same as in the above embodiment. When the RF power was applied, the power was set to 200 W instantaneously, and after 90 seconds of etching, the RF application was stopped.

【0015】(表1)に本発明と従来のRFパワー印加
方法でのウェハー裏面のダスト数の比較を示す。6イン
チSiウェハーの裏面をダストカウンターにより測定し
た値である。0.3μm以上のダストをそれぞれ5枚ず
つエッチングし測定した結果であるが、従来例の測定
時、ダストが多すぎたため、ウェハー中心から半径約2
5mmの範囲のみの測定で、ダストカウンターのメモリー
容量をオーバーしてしまったので(表1)の従来例の測
定結果は、半径25mmの範囲の実測値と、6インチウェ
ハーでの換算値を示す。
Table 1 shows a comparison of the number of dusts on the back surface of the wafer between the present invention and the conventional RF power applying method. It is a value measured by a dust counter on the back surface of the 6-inch Si wafer. The results are obtained by etching 5 pieces of dust each having a size of 0.3 μm or more, and the radius of about 2 from the center of the wafer because there was too much dust during the measurement of the conventional example.
Since the memory capacity of the dust counter was exceeded by measuring only in the range of 5 mm, the measurement result of the conventional example in (Table 1) shows the measured value in the range of 25 mm radius and the converted value on a 6-inch wafer. ..

【0016】[0016]

【表1】 [Table 1]

【0017】このように、ウェハーの裏面ダストが大幅
に低減されていた。又、従来のRFパワー印加方法で、
発生していた、エッチング終了後にウェハーと電極の密
着が保持されることによるウェハー搬送不良も同時に改
善された。
Thus, the backside dust of the wafer was significantly reduced. Also, with the conventional RF power application method,
At the same time, the wafer transfer failure due to the fact that the contact between the wafer and the electrode was maintained after the etching was completed was also improved.

【0018】[0018]

【発明の効果】以上のように本発明は、RFパワー印加
時、複数のステップに分割して、所定値まで増加させる
RFパワー増加方法と、エッチング終了後、複数のステ
ップに分割して、RFパワーを減少し、放電を停止する
RFパワー減少方法を組み合わせたRFパワー印加方法
により、基板裏面と電極表面の間で発生していたダスト
が大幅に低減でき、製品の歩留りが改善できる。又、エ
ッチング終了後に基板と電極の密着が保持されることに
より発生したウェハー搬送不良も同時に改善される。
As described above, according to the present invention, when the RF power is applied, the method is divided into a plurality of steps to increase the RF power to a predetermined value. By the RF power application method that combines the RF power reduction method of reducing the power and stopping the discharge, the dust generated between the back surface of the substrate and the electrode surface can be significantly reduced, and the product yield can be improved. In addition, a wafer transfer defect caused by maintaining close contact between the substrate and the electrode after the etching is also improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例におけるRFパワー印加方法
を示す図
FIG. 1 is a diagram showing an RF power applying method according to an embodiment of the present invention.

【図2】ドライエッチング装置を示す構成図FIG. 2 is a block diagram showing a dry etching apparatus.

【図3】従来のRFパワー印加方法を示す図FIG. 3 is a diagram showing a conventional RF power application method.

【図4】従来のドライエッチング方法におけるウェハー
の突き上げ状態を示す図
FIG. 4 is a view showing a wafer push-up state in a conventional dry etching method.

【符号の説明】[Explanation of symbols]

11 上部対抗電極 12 下部電極 14 基板 11 Upper Counter Electrode 12 Lower Electrode 14 Substrate

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 電極上にエッチング対象となる基板を置
き、RF電力を印加するドライエッチング装置におい
て、RF電力の印加の際、複数のステップに分割して、
所定値までRF電力を増加する工程と、エッチング終了
後、複数のステップに分割してRFパワーを減少し、放
電を停止する工程とを有するドライエッチング方法。
1. A dry etching apparatus in which a substrate to be etched is placed on electrodes and RF power is applied, the RF power application is divided into a plurality of steps,
A dry etching method comprising a step of increasing the RF power to a predetermined value, and a step of dividing the RF power into a plurality of steps to reduce the RF power after the etching is finished and stopping the discharge.
JP4050282A 1992-03-09 1992-03-09 Dry etching method Pending JPH05251197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4050282A JPH05251197A (en) 1992-03-09 1992-03-09 Dry etching method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4050282A JPH05251197A (en) 1992-03-09 1992-03-09 Dry etching method

Publications (1)

Publication Number Publication Date
JPH05251197A true JPH05251197A (en) 1993-09-28

Family

ID=12854576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4050282A Pending JPH05251197A (en) 1992-03-09 1992-03-09 Dry etching method

Country Status (1)

Country Link
JP (1) JPH05251197A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227816A (en) * 2006-02-27 2007-09-06 Consortium For Advanced Semiconductor Materials & Related Technologies Plasma treatment ending method
JP2008226922A (en) * 2007-03-08 2008-09-25 Ulvac Japan Ltd Method and apparatus of manufacturing magnetic device
CN112103167A (en) * 2020-09-28 2020-12-18 上海华虹宏力半导体制造有限公司 Dry etching process

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227816A (en) * 2006-02-27 2007-09-06 Consortium For Advanced Semiconductor Materials & Related Technologies Plasma treatment ending method
JP4678688B2 (en) * 2006-02-27 2011-04-27 次世代半導体材料技術研究組合 Plasma processing end method
JP2008226922A (en) * 2007-03-08 2008-09-25 Ulvac Japan Ltd Method and apparatus of manufacturing magnetic device
CN112103167A (en) * 2020-09-28 2020-12-18 上海华虹宏力半导体制造有限公司 Dry etching process

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