JPS59160333U

JPS59160333U - interface circuit

Info

Publication number: JPS59160333U
Application number: JP5347383U
Authority: JP
Inventors: 康修鈴木
Original assignee: カシオ計算機株式会社
Priority date: 1983-04-12
Filing date: 1983-04-12
Publication date: 1984-10-27

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of the drawing]

第１図は、従来例を示した回路構成図、第２図および第
３図はこの考案の一実施例を示し、第２図は出力インタ
ーフェイス回路の構成図、第３図は入力インターフェイ
ス回路の構成図、第４図はこの考案の第２実施例を示し
た入出力インターフェイス回路の構成図である。ＩＭ・・・・・・内部機器、ＯＭ・・・・・・外部機器
、ＩＣ３・・・ＩＣ，。ＩＣ６，ＩＣ９・・・・・・レベルシフト回路付キハツ
ファ、ＩＣ，・・・・・−ＴＴＬバッファ、ＩＣ７・・
・・・・イネーブル入力付きバッファ、Ｒ２・・・・・
・プルアップ抵抗、ｖ２・−・・・・外部機器の電源電
圧信号、１・・・・・・信号ライン。Fig. 1 is a circuit configuration diagram showing a conventional example, Figs. 2 and 3 show an embodiment of this invention, Fig. 2 is a configuration diagram of an output interface circuit, and Fig. 3 is a configuration diagram of an input interface circuit. FIG. 4 is a block diagram of an input/output interface circuit showing a second embodiment of this invention. IM...Internal device, OM...External device, IC3...IC,. IC6, IC9...Kihatsufa with level shift circuit, IC,...-TTL buffer, IC7...
...Buffer with enable input, R2...
・Pull-up resistor, v2: power supply voltage signal of external equipment, 1: signal line.

Claims

[Scope of utility model registration request]

In an interface circuit between an internal device and an external device whose power supply voltage is different from that of the internal device connected to this internal device via a signal line, there is a means to prohibit the output of the internal device when the power of the external device is turned off, and An interface circuit comprising means for level shifting an input signal from an external device when the power is turned on. □