JPS59159193U - Gate circuit for variable voltage/variable frequency inverter - Google Patents

Gate circuit for variable voltage/variable frequency inverter

Info

Publication number
JPS59159193U
JPS59159193U JP5269483U JP5269483U JPS59159193U JP S59159193 U JPS59159193 U JP S59159193U JP 5269483 U JP5269483 U JP 5269483U JP 5269483 U JP5269483 U JP 5269483U JP S59159193 U JPS59159193 U JP S59159193U
Authority
JP
Japan
Prior art keywords
variable
frequency inverter
gate circuit
gate
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5269483U
Other languages
Japanese (ja)
Inventor
林 昭佳
茂俊 岡松
Original Assignee
株式会社日立製作所
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 株式会社日立製作所 filed Critical 株式会社日立製作所
Priority to JP5269483U priority Critical patent/JPS59159193U/en
Publication of JPS59159193U publication Critical patent/JPS59159193U/en
Pending legal-status Critical Current

Links

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  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の系統図、第2図は第1図の
動作状態のタイミングチャートである。−1・・・パル
ス巾変調回路、2・・・パルス波形リミッタ回路、3・
・・パルスアンプ回路、4・・・GTO三相インバータ
回路、5・・・三相誘導電動機、6・・・相短絡検知回
路。   −
FIG. 1 is a system diagram of an embodiment of the present invention, and FIG. 2 is a timing chart of the operating state of FIG. 1. -1...Pulse width modulation circuit, 2...Pulse waveform limiter circuit, 3.
...Pulse amplifier circuit, 4...GTO three-phase inverter circuit, 5...3-phase induction motor, 6... Phase short circuit detection circuit. −

Claims (1)

【実用新案登録請求の範囲】 ゲートターンオフサイリスタによって構成されるインバ
ータにおいて、 主回路が相短絡をおこしたとき、これを検知してケート
信号が変化しないようにロックするゲー−ドブロック機
能をパルス波形リミッタ回路に付加したことを特徴とす
る可変電圧・可変周波数インバータ用ゲート回路。
[Claims for Utility Model Registration] In an inverter configured with a gate turn-off thyristor, when a phase short circuit occurs in the main circuit, the gate block function that detects this and locks the gate signal so that it does not change is implemented using a pulse waveform. A gate circuit for a variable voltage/variable frequency inverter characterized by being added to a limiter circuit.
JP5269483U 1983-04-11 1983-04-11 Gate circuit for variable voltage/variable frequency inverter Pending JPS59159193U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5269483U JPS59159193U (en) 1983-04-11 1983-04-11 Gate circuit for variable voltage/variable frequency inverter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5269483U JPS59159193U (en) 1983-04-11 1983-04-11 Gate circuit for variable voltage/variable frequency inverter

Publications (1)

Publication Number Publication Date
JPS59159193U true JPS59159193U (en) 1984-10-25

Family

ID=30183044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5269483U Pending JPS59159193U (en) 1983-04-11 1983-04-11 Gate circuit for variable voltage/variable frequency inverter

Country Status (1)

Country Link
JP (1) JPS59159193U (en)

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