JPS59152664A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59152664A JPS59152664A JP2619783A JP2619783A JPS59152664A JP S59152664 A JPS59152664 A JP S59152664A JP 2619783 A JP2619783 A JP 2619783A JP 2619783 A JP2619783 A JP 2619783A JP S59152664 A JPS59152664 A JP S59152664A
- Authority
- JP
- Japan
- Prior art keywords
- film
- tiw
- electrode
- semiconductor device
- electrodes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract 5
- 229910000676 Si alloy Inorganic materials 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 claims 4
- 229910021339 platinum silicide Inorganic materials 0.000 claims 4
- CSDREXVUYHZDNP-UHFFFAOYSA-N alumanylidynesilicon Chemical compound [Al].[Si] CSDREXVUYHZDNP-UHFFFAOYSA-N 0.000 claims 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 229910001080 W alloy Inorganic materials 0.000 claims 1
- 229910052814 silicon oxide Inorganic materials 0.000 claims 1
- MAKDTFFYCIMFQP-UHFFFAOYSA-N titanium tungsten Chemical compound [Ti].[W] MAKDTFFYCIMFQP-UHFFFAOYSA-N 0.000 claims 1
- 239000000758 substrate Substances 0.000 abstract description 9
- 238000001312 dry etching Methods 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 4
- 238000004544 sputter deposition Methods 0.000 abstract description 4
- 229910018125 Al-Si Inorganic materials 0.000 abstract 4
- 229910018520 Al—Si Inorganic materials 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 229910000789 Aluminium-silicon alloy Inorganic materials 0.000 abstract 1
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は半導体装置、特に浅いｐｎ接合を有する耐熱性
電極構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a heat-resistant electrode structure having a shallow pn junction.
一つのＳｉ（シリコン）半導体基体にオーム接触する電
極とショットキーバリアをつくる電極となぞなえたショ
ットキーＴＴＬ回路等においては、在来のＡ、６（アル
ミニウム）電極に代って耐熱性電極としてｐｔ（白金）
・８ｉ−Ｔｉ （チタン）Ｗ（タングステン）−１の３
層構造の電極が使用されているう論理回路の高速化に伴
い、回路を構成するト、ランジスタ等のｐｎ１合の深さ
はますます浅くなる傾向にあるが、Ｐｔ＝Ｓｉ合金をコ
ンタクト部とする上記３層電極を形成する場合に下記の
問題を生じる。In Schottky TTL circuits, etc., which are likened to an electrode that makes ohmic contact with a single Si (silicon) semiconductor substrate and an electrode that creates a Schottky barrier, it is used as a heat-resistant electrode in place of the conventional A, 6 (aluminum) electrode. pt (platinum)
・8i-Ti (Titanium) W (Tungsten)-1-3
As the speed of logic circuits using layered electrodes increases, the depth of the pn1 junctions of transistors, transistors, etc. that make up the circuits tends to become shallower. When forming the above-mentioned three-layer electrode, the following problems occur.
Ｐｔ−８ｉ−ＴｉＷ−Ａ＃ ３層電極を形成する際、第
１図を参照し、′通常、Ｓｉ基体（ｐ型ベース）１の表
面にｎ型エミツタ層２を設け、表面Ｓ ｒ ０２膜３に
より囲まれたｎ型層２表面にｐｔを蒸着し熱処理し不要
のｐｔを除去することによりｐｔ・Ｓｉ 合金層４′を
形成する。この上にＳ ｔ Ｏｔと接着性のよいＴｉＷ
膜５及び電極材としてＡ！又はＭ−８ｉ膜６を蒸着、ス
パッタにより形成した後、上記ＡＡ等を選択的エッチし
て電極パターンを形成し、次いでこのＡＡの電極パター
ンに合せてＴｉＷ膜の不要部を除去するっこのＴｉＷ膜
のエッチには微細加工に適合したプラズマ放電を利用し
、ＣＦ。When forming a Pt-8i-TiW-A# three-layer electrode, refer to FIG. A pt.Si alloy layer 4' is formed by depositing PT on the surface of the n-type layer 2 surrounded by 3 and removing unnecessary PT by heat treatment. On top of this, TiW with good adhesion to S t Ot
A as the membrane 5 and electrode material! Alternatively, after forming the M-8i film 6 by vapor deposition or sputtering, selectively etching the AA, etc. to form an electrode pattern, and then removing unnecessary parts of the TiW film in accordance with the electrode pattern of this AA. To etch the film, plasma discharge suitable for microfabrication is used, and CF is used.
をエッチャントどするドライエッチによって行なうが、
このＣＦ４はＳｉも同時にエッチするため、ＰｔＳｉ膜
４とＳ ｔ Ｏｐ膜３との間がホトマスク位置誤差のた
めに開いて下地Ｓｉが露出するいわゆる「目あき」を生
じた場合に同図に示すようにＣＦ４により下地Ｓ１がお
かされて深い凹陥部７を生じ、例えば０．３μｍ程度し
かない浅いベース・エミッタｐｎ接合８を突き抜けて接
合破壊な生じることになった。This is done by dry etching using an etchant.
Since this CF4 also etches Si at the same time, if a gap occurs between the PtSi film 4 and the S t Op film 3 due to a photomask position error and the underlying Si is exposed, as shown in the figure. As shown, the underlying layer S1 was disturbed by the CF4, creating a deep recess 7, which penetrated through the shallow base-emitter pn junction 8, which was only about 0.3 μm, resulting in junction breakdown.
本発明の目的とするところはドライエッチによる微細加
工が可能な浅いｐｎ接合を有する素子の耐熱性電極構造
な提供することにある。An object of the present invention is to provide a heat-resistant electrode structure for an element having a shallow pn junction that can be microfabricated by dry etching.
〔発明の概要）
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、Ｓｉ＆体表面で５ｉｎｔ膜により
囲まれた領域にＰｉＳｉ膜が形成され、このＰｔ−８ｉ
膜上にＴｉ−Ｗ膜を介してＡｎからなるｔ極を有する半
導体装置において、上記Ｐｔ−８ｉ上及びそれを囲むＳ
ｒ ０２膜の表面を薄いＡ＃−８ｉ膜で覆っておくこ
とにより、ＴｉＷエッチの際にエッチャントによるＳｉ
基体のｐｎ接合破壊を防止するものである、
〔発明の実施例〕
第２図はＰｔＳｉ −ＴｉＷ−ＡｐＳｉ よりなる耐
熱性電極を有する半導体装置に本発明を適用した場合の
一実施例構造を示すものである。■はＳｉ基体となるｐ
型ベース、２はｎ型エミッタ拡散層、３は表面酸化膜（
Ｓ ＋ Ｏｘ膜）である、４はｎ型エミνり拡散層のＳ
ｉにオーミンク接触（低抵抗接続）するＰｔ−Ｓｉ合金
層である。９は上記Ｓｉｎ。[Summary of the Invention] To briefly explain the outline of a representative invention among the inventions disclosed in this application, a PiSi film is formed in a region surrounded by a 5-inch film on the Si & body surface, and this Pt-8i
In a semiconductor device having a t-pole made of An via a Ti-W film on the film, the S
By covering the surface of the r02 film with a thin A#-8i film, Si
[Embodiment of the Invention] Fig. 2 shows the structure of an embodiment in which the present invention is applied to a semiconductor device having a heat-resistant electrode made of PtSi-TiW-ApSi. It is something. ■ is p which becomes the Si substrate
Type base, 2 is n-type emitter diffusion layer, 3 is surface oxide film (
4 is the S + Ox film of the n-type emitter diffusion layer.
This is a Pt-Si alloy layer that makes ohmink contact (low resistance connection) to i. 9 is the above Sin.
膜３とＰｔＳｉ合金層４σユ表面に形成された５００Ａ
程、度の薄いＡ６−８ｉ膜である。５はバリアーメタル
として形成されたＴｉ−Ｗ膜である。６はＴ ｉ Ｗ膜
上に形成されたＡ６−３ｔ（２％Ｓｉ）！極である。500A formed on the surface of film 3 and PtSi alloy layer 4σ
It is a thin A6-8i film. 5 is a Ti-W film formed as a barrier metal. 6 is A6-3t (2% Si) formed on the TiW film! It is extreme.
第３図〜第６図は−っの基板上でベース及びエミッタの
電極に耐熱性合金を使用する半導体装置の電極形成プロ
セスを示すものである。FIGS. 3 to 6 show a process for forming electrodes of a semiconductor device using a heat-resistant alloy for base and emitter electrodes on a second substrate.
ｉｄｌ 第３図に示す表面にｐ型ベース１、ｎ＋型エ
ミッタ２を拡散（接合深さ０．３μｍ）により形成した
Ｓｉ基体を用意し、拡散のため表面に形成したＳｉｎ、
膜をマスクとして、ｐｔを約５００にの厚さに蒸着（又
はスパツク）し、例えば４５０〜５００Ｃで熱処理する
ことにより厚さｘｏｏｏｉ程度のＰｔＳｉ合金膜４ａ、
４ｂを得る。コ（７）後Ｓ ｒ ０２膜上とｐｔをエッ
チ除去する。idl Prepare a Si substrate on which a p-type base 1 and an n+-type emitter 2 are formed by diffusion (junction depth 0.3 μm) on the surface shown in FIG.
Using the film as a mask, PtSi alloy film 4a having a thickness of about xoooi is formed by vapor depositing (or sprocketing) PT to a thickness of about 500 nm and heat-treating it at, for example, 450 to 500 C.
Get 4b. After step (7), the S r 02 film and the PT are removed by etching.
ｔｂ＋ 第４図に示すように全面にＡ６’Ｓｉ膜９を
薄くスパッタにより形成する。このＡ、、６Ｓｉ膜は厚
すぎるとＡ＃−８ｉ中１７） Ａ−ｇＩＪ’Ｐｔ５ｉ
ｍヲ突き抜はルタめ５００＾程度又はそれ以下の厚さと
することがのぞましい。tb+ As shown in FIG. 4, a thin A6'Si film 9 is formed on the entire surface by sputtering. If this A,,6Si film is too thick, A#-8i 17) A-gIJ'Pt5i
It is desirable that the thickness of the punching be approximately 500 mm or less.
（Ｃ１第５図に示すように全面にスパッタにより０．１
５μｍ程度の厚さにＴｉＷ膜５を形成し、次いでＡ、１
３−８ｉ （２％Ｓｉ）を１μｍの厚さに形成し、この
あとＡ＃−８ｉ膜６の一部Ｃ（１，をエッチャントとす
るドライエッチにより選択的に除去し、へ召−８ｉ電極
５ａ、５ｂを形成する。(C1 As shown in Fig. 5, the entire surface is sputtered with 0.1
A TiW film 5 is formed to a thickness of about 5 μm, and then A, 1
3-8i (2%Si) is formed to a thickness of 1 μm, and then a part of the A#-8i film 6 is selectively removed by dry etching using C(1) as an etchant, and then the A#-8i electrode is formed. 5a and 5b are formed.
ｉｄｌ 次いで第６図に示すようにＡ＃−８ｉ電極５
ａ。idl Then, as shown in FIG. 6, the A#-8i electrode 5
a.
６ｂをマスクとしてＣＦ４をエッチャントとするドライ
エッチにより露出しているＴｉＷを除去する。The exposed TiW is removed by dry etching using 6b as a mask and CF4 as an etchant.
以上実施例で述べた構成によればベース及びエミッタの
コンタクト部のＰｔＳｉ上とそれ１を囲むＳ ｉＯｐ
ＨＡ上に５すいＡ＃−５ｉ膜を形成することにより、Ｔ
ｉＷ膜エッチ時にＣＦ４によりＡ、ｅがエッチされるこ
とがないので、たとえ、ＰｔＳｉとＳｉｎ、膜との間に
「目あき」を生じることがあっても下地のＳｉがエッチ
されることがなく、またＡ−８ｉ膜が５すいためその後
の加熱によりＡでが浅いｐｎ接合を有する８１基体への
突き抜けを防止できる効果を有する。According to the configuration described in the embodiments above, the SiOp that surrounds the PtSi of the base and emitter contact portions 1 is
By forming a pentagonal A#-5i film on HA, T
Since A and e are not etched by CF4 during iW film etching, the underlying Si will not be etched even if "openings" may occur between the PtSi and Sin films. Moreover, since the A-8i film is five-dimensional, it has the effect of preventing A from penetrating into the 81 substrate having a shallow pn junction by subsequent heating.
したがって本発明によればドライエッチによる微細加工
が可能な浅いｐｎ接合を有する素子の耐熱性電極を提供
できる。Therefore, according to the present invention, it is possible to provide a heat-resistant electrode for an element having a shallow pn junction that can be microfabricated by dry etching.
以上本発明者によってなされた発明を実施例にもとづき
説明したが、本発明は上記実施例に限定されるものでな
く、その要旨な逸脱しない範囲で種々変更可能である。Although the invention made by the present inventor has been described above based on the embodiments, the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.
例えば一つの半導体基体上に形成されるシロットキバリ
ア・トランジスタのエミッタ・ベースのための電極に本
発明を応用することができる。For example, the present invention can be applied to electrodes for the emitter and base of a Sirotchi barrier transistor formed on one semiconductor substrate.
本発明は高速バイポ〜うＩＣ特にメモリ及びロジックの
各セルに設ける耐熱性電極に適用して有効である。The present invention is effective when applied to heat-resistant electrodes provided in high-speed bipolar ICs, particularly memory and logic cells.
□第１図は耐熱性３層構造電極の例を示す断面図である
。
第２図は本発明による耐熱性！極の実施例を示す断面図
である。
第３図〜第６図は本発明による耐熱性電極の製造プロセ
スの実施例を示す工程断面図である。
１・・・ｐ型Ｓｉ基体（ベース）、２・・・ｎ型層（エ
ミッタ）、３・・・５ｉＯｙ膜、４・・・Ｐｔ−８ｉ合
金膜、５・・・ＴｉＷ合金膜、６・・・ＡＪ−８ｉ膜、
７・・・凹陥部。
８・・・ｐｎ接合、９・・・うすいＡノＳｉ膜。
第 １ 図
第 ２ 図
第 ３ 図□Figure 1 is a cross-sectional view showing an example of a heat-resistant three-layer structure electrode. Figure 2 shows the heat resistance according to the present invention! FIG. 3 is a cross-sectional view showing an example of a pole. 3 to 6 are cross-sectional views showing an embodiment of the process for manufacturing a heat-resistant electrode according to the present invention. DESCRIPTION OF SYMBOLS 1... P-type Si substrate (base), 2... N-type layer (emitter), 3... 5iOy film, 4... Pt-8i alloy film, 5... TiW alloy film, 6...・・AJ-8i membrane,
7... Concavity. 8...pn junction, 9... thin A-Si film. Figure 1 Figure 2 Figure 3
Claims (1)
絶縁膜によって囲まれた領域に白金シリサイド膜が形成
され、この白金シリサイド膜の上にチタン・タングステ
ン合金膜な介してアルミニウムからなる電極を有する半
導体装置において、上記白金シリサイド膜ト及びそれな
囲む絶縁膜上が上記電極のアルミニウムが少なくとも白
金シリサイド膜を突き抜けることのない程度の厚さのア
ルミニウム・シリコン合金膜で覆われていることを特徴
とする半導体装置。 ２゜上記アルミニウム・シリコン合金膜は５００Ａ程度
である特許請求の範囲第１項に記載の半導体装置。[Claims] 1. A platinum silicide film is formed in a region surrounded by a thick insulating film made of silicon oxide on the surface of the silicon segment, and a titanium-tungsten alloy film is formed on top of the platinum silicide film. In a semiconductor device having an electrode, the platinum silicide film and the surrounding insulating film are covered with an aluminum-silicon alloy film having a thickness such that at least the aluminum of the electrode does not penetrate through the platinum silicide film. A semiconductor device characterized by: 2. The semiconductor device according to claim 1, wherein the aluminum-silicon alloy film has a current of about 500A.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2619783A JPS59152664A (en) | 1983-02-21 | 1983-02-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2619783A JPS59152664A (en) | 1983-02-21 | 1983-02-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59152664A true JPS59152664A (en) | 1984-08-31 |
Family
ID=12186756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2619783A Pending JPS59152664A (en) | 1983-02-21 | 1983-02-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152664A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246732A (en) * | 1991-07-16 | 1993-09-21 | U.S. Philips Corporation | Method of providing a copper pattern on a dielectric substrate |
-
1983
- 1983-02-21 JP JP2619783A patent/JPS59152664A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5246732A (en) * | 1991-07-16 | 1993-09-21 | U.S. Philips Corporation | Method of providing a copper pattern on a dielectric substrate |
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