JPS59152484A - Read only memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a read-only memory (hereinafter referred to as ROM),
In particular, the present invention relates to a read-only memory for generating character stamps that allows the output format to be selected.

ROM has conventionally been used to generate character patterns for outputting alphanumeric characters and numbers to display devices or printing devices. Recently, especially with the spread of Japanese information processing and advances in semiconductor integrated circuits, kanji patterns with many equivalent strokes have been used as output for information processing, and the use of ROMs for character pattern generation is increasing. FIG. 1 shows an example in which A is output in a 5×7 pattern. In this example, the character pattern (represented by 35 points of 5 x 7 fli), RO
The output of M is composed of 5 bits and outputs a total of 1t35 points at address 7. 01 to o5 are outputs of R and OM, address AO, AI, A203 bit is 000
The pattern is decomposed and stored in the 7th address from 110. The black background corresponds to logic output 1, and the white background corresponds to logic output 0. When a signal is supplied to a display device, the address is changed from ooo to 1'IO, and the signal is divided into seven parts and output.

FIG. 2 is an example of printing on printing devices of different types. In this case, the output consists of 7 bits from 01 to o7, and the 3-bit address of Ao, AI, and A2 is 000.
It is divided into 5 locations from 100 to 100. In this way, even if the same character pattern is output, the arrangement of data in the ROM differs depending on the connected device. Conventionally, even for the same character pattern, separate It OMs were prepared according to the data arrangement required by the printing device or display device.

An object of the present invention is to provide an RO configured to be able to switch according to the character output direction when outputting the same character pattern.
The goal is to provide M.

In the present invention, the output bit string of a character pattern composed of dots and the division in the address direction are selectively switched using a control terminal.

FIG. 3 shows an embodiment of the invention. 1 is ROM
It targets a character pattern of 35 points (5 x 7) in the memory section of , and outputs 35 characters, which is the same number as the number of points. This output is the input of the first output address select circuit 2.■
There are 35 inputs from 1 to 135. Address select circuit 2 inputs ■1 to '350 as Ao, AI
, A2 selects and outputs 7-bit outputs from X to X7. 3 is the second output address select circuit;
The 5-bit output from Yl to Y is selected and output using the 2 3-bit address signal. 4 selectively switches the outputs of the two address selectors from 01 to 0 using the control signal S.
This is a switching circuit that outputs to the output terminal of □.

The structure of the address selector 2 of this embodiment corresponds to the character pattern shown in FIG. 2, and the structure of the address selector 3 corresponds to the character pattern shown in FIG.

X1 to X7 correspond to 01 to o7 of the pattern in Fig. 2,
Y1 to Y6 are 01 to 0.0 in FIG. It corresponds to In this embodiment, it is possible to select and output either X1 to X7 or Y1 to Y using the control signal S, and two character pattern arrangements can be made using the stored contents of the same ROM. You can choose. As described above, if the present invention is used, it is possible to select a plurality of output methods with one ROM, which has a very large economical effect.

Naturally, in the present invention, the number of types that can be switched and the number of address select circuits with outputs can be three or more, and it is clear that the same effect can be obtained even if the character pattern used is multi-point, such as 32x32. .

[Brief explanation of drawings]

1 and 2 are diagrams showing the output of a character pattern composed of 5×7 points, and FIG. 3 is a hypothetical example of the present invention. 1...ROM memory section, 2, 3...
Address select circuit, 4...Switching circuit, 0□
~07...Corresponds to the output of ROofVi, AOlA
I, A2゛゛゛ address input. γ toss 1st output grass 1 coral rod 2 times

Claims (1)

[Claims] A read-only memory that outputs stored contents in response to address input, characterized in that the output section includes a plurality of address selection circuits and a switching circuit that selects and outputs one of the plurality of address selection circuits. Read-only memory.