JPS59151373A - Automatic address controller - Google Patents

Abstract

PURPOSE:To improve the transfer efficiency of a data and the processing of a CPU by the software by switching a counting output of a counter according to the transfer mode every time a data is transferred to a memory. CONSTITUTION:An address control section 30 has three clock output terminals 301, 302, and 303, and the output terminals 301, 302 and 303 are connected respectively to a clock input terminal CK of a counter 25, an up-clock input terminal up of a counter 26 and a down clock input terminal down. Further, a clock pulse CP is applied to counters 25, 26 as an counting clock pulse, thus an address data outputted from the counters 25, 26 is changed sequentially. In this case, the address control section 30 decides to which terminal 301, 302 and 303 a clock pulse CP is to be outputted depending on the data transfer mode. Therefore, the address designating operation in response to the data transfer mode is attained.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a central processing unit (hereinafter referred to as CPU) that transfers image data sent by boat to a central processing unit (hereinafter referred to as CPU) in, for example, a captain system or a teletext system. The present invention relates to a device for transferring information to a memory, and more particularly to an automatic address control device that automatically controls a write address to a memory.

[Technical background of the invention]

In the captain system and teletext system, the image data that has been sent is transferred from the CPU to the memory.
Once stored in memory, it is read out as appropriate and displayed on the screen.

The following two methods can be considered as methods for transferring image data for memo IJK display from the CPU.

(1) Memory transfer method from CPU to KM.

(2) Method of transferring data from the CPU to the memory in the form of a boat transfer The eleventh circuit is a circuit diagram showing the child transfer method of (1). In this method, tr:J, cPUl and memory 1
21”t:'n'?-Kubas T) Let's meet at B,
1 contact memo IJ from the image data CPU 11.
Transferred to l2. The address data that specifies the write address at this time is sent to switch 13 from CPTJJJ.
The data is supplied to the memory 12 via.

The image density data stored in the memory 12 is sequentially read in accordance with the address data for specifying the read address supplied from the display address generation circuit 14 to the memory 12 via the switch 13, and the image is received via the decoder 15. The pipe 16 is completely supplied.

It is a circuit that converts the image data from the decoder 15 memory 12 into a signal that is supplied to the brass tube 11 tube 16. Note that (AB) in the figure is an address bus, and MAR is an address bus for 1 memory. be.

In this method, in order to avoid collision between the image data for memo 'J 121'r it # and the one-page image data read out from the memory 12, a blanking period, etc. is generally used. Data is transferred from the CPU 11 to the memory 12 after a period unrelated to the program. Therefore, there are problems in that the CPUJi cannot be used unless the blanking period is detected, and that data can only be transferred during the blanking period, resulting in poor transfer efficiency.

84'', 2+1 is a circuit diagram showing the data transfer method of (2).For example, the data transfer method of (2) was patented by the patent applicant on November 11, 1988. There is a technique disclosed in Samurai Patent Application No. 1982-1982.
This is a schematic representation of the parts related to the explanation of this invention of the technique disclosed in No. 6. In the figure, 17 is a display control section, and the CPU 77
The image data output from the CPUJJ inserted between the CPtJWl and the memory 12 as an external circuit is -
After being stored in the data register 171 of the B display control section 173-, it is supplied to the memory 12 via the memory data bus MDR.

The address data at this time is also output from CPU1,
Once the address register 172 of the display control section 17
After being stored in the memory month 1A,
The signal is supplied to the memory 12 via Rf. The display control section 17 performs a function of periodically generating the memory 2 (access period for writing all the data) between the display 1 and 1. Reference numeral 173 is a display address generation circuit.

According to such a configuration, image data can be transferred from the CPU 77 to the memo IJ J, ? without distinguishing between the display period and the displayable period, and the transfer efficiency is improved compared to the method (1). However, this method Even with this method, every time image data is transferred in the entire memory 12&, new data is sent from the FSCPU 7J to the data register 171 and address 1/register 172.
- There are still problems in terms of the complexity of the CPU software and transfer efficiency.

4- [Object of the invention] This invention was developed to deal with the above-mentioned circumstances, and can improve the data transfer efficiency and improve the CP
The purpose of the present invention is to provide an A)-responsive control device that can improve the processing by software of the U.

[Critique of the invention]

The present invention includes means for storing data indicating a data transfer mode and a counter means for outputting an address data indicating an old address, and the transfer mode data and the first address data of the write address are set as initial settings at the time of data transfer. Each time the data is transferred to the memory, the counting output contents of the counter means are switched in accordance with the transfer mode.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 3 is a circuit diagram of one embodiment. In the figure,
21 is a CPU, and 22 is a memory for storing image data of the display Jll. 23U is the write data register. Sent to / Neryo (+4 Nodeku Vsu CPUz
7 to 111 theta l/jis 1. ? 3, and is transferred from this child storage disk 23 to the memory 22. Z
This is a register for storing the image data transfer mode, the increment of the address in the memory 22, and the transfer mode in the 4-digit mode 2).This transfer mode data is CPU
It is sent from. 25 and 26 are counters that specify the address of the memory. Of these, 25 is an in-address counter for writing, which is the address in the mold direction of the screen surface position 1,
Address data flf that specifies the line address
I will force myself.

On the other hand, 26d flat! The reading byte completion code 1/sub/down counter outputs address data specifying the horizontal address of the screen's display position and the switching byte address l-'L. Address data indicating the start address is set in these counters 25 and 26 at the time of data transfer.

The above-mentioned image data, transfer mode data, and address data are transferred from the CPU 21 to the address data bus (A, -DB).
) via 17 to the corresponding registers 23 and 24, counter 2
．． In the evening, it will be set on the 26th. Latch pulse L in this case
, ~L4 are output from the address decoder 27 according to the boat number. In this case, data is set to the data register 23 sequentially during the data transfer period, but data is set to the register 24 and counters 25 and 26 as initial settings at the time of data transfer. be.

28 (l-'t data transfer period, this is a write piece access control section that creates an access period for writing both I and 1 codes into the memory 22 during the light display period. This write access control section 28 An access pulse AP indicating the above-mentioned access period is generated using a start pulse AGF indicating the start of the access period and an end pulse AGRf indicating the end v. This access pulse AP is 7.
- When the output is started, image data can be supplied to the memory 22 through the entire mode register 23kt memory data bus MDB. ′! ), counter 2. ';, 2
Atnos bus MABI for memory that connects all 6 and memory 22
/i1'' The inserted buffer gate 29 is fully opened, and address data is supplied to the memory 12.The write access fill @l 428 creates the entire access period at the timing of the first latch signal L4. The details of this 3G access control section 28 are described in the above-mentioned Japanese Patent Application No. 1982-1982, so a detailed explanation will be given here. Be agile.

This is a 30r address control unit. This address control Ni
,? o Vi three clock output terminals 30 J.

3o 2, 3o 3 [-5 each output terminal 301°3
02, 303 Clock input terminal CK of counter 25, lock input terminal 1 for up of counter 26
This address is connected to the clock input terminal down l, and the clock pulse CP is output from the convolution access control unit Z8 during the above-mentioned access period. This clock pulse CP is supplied to counters 25 and 26.
The counters 25 and 26 sequentially change the address data output from the counters 25 and 26 as clock pulses for counting. In this case, the address control unit 30 selects which clock output terminal 30].

,? 02, 30 ;? 0, which determines whether to output the K clock pulse CP according to the data transfer mode;
Accordingly, addressing operation is performed according to the data transfer mode. Note that the clock pulse CP is outputted every time data stored in the data register 23 is transferred to the memory 22 and new image data is stored in the register 23.

As a result of the above 114 configuration, data indicating the data transfer mode is set in the mode register 24, and the address data counter 25, which specifies the first address of the transfer data,
If you set -f to 26, then data resis 6123
By simply setting image data one after another, the address control unit 30 controls all addressing operations in the data transfer mode. Become.

The address control section will now be explained using some specific examples of the C1 router transfer mode. In the image data display position (t), as shown in Figure 4, the display position of the image data is as shown in Figure 4. This can be indicated by a line address in the range 0 to 203. Therefore, the byte address block/down counter is 22 digits, 5 bits, and the write address counter 21 is 5 bits.
has an 8-bit configuration.

Furthermore, as the image data display mode and data transfer mode, there are mainly three types as shown in FIG. First of all, Figure 5: The mode shown in (a) is a mode in which data is sequentially written from left to right on the same line at positions f1 bytes e, and the horizontal scanning dot pattern display in the captain system is in this mode. Equivalent to. The mode shown in FIG. 3B is a mode in which all data are read in units of 1 byte in the direction of the line address, and the 4th display in the captain system corresponds to this mode. The mode shown in figure (c) is a mode in which data is written in 1-byte units when displaying printed characters (15 dots x 18 dots) using a code transmission method, etc., and 2 bytes are omitted in the horizontal direction. and move on to the next line.

In the mode shown in FIG. 5(a), image data is stored in the memory 2.
It is sufficient that the count output of the byte address up/down counter 26 is incremented every time the byte address up/down counter 26 is transferred. Therefore, the address control section 30 outputs a clock pulse CP'f to the clock output terminal 302.

#[5 Each time 1d5 image data is transferred in the mode shown in FIG. 5(b), the count output of the line address counter 25 must be incremented. Therefore, the address control unit 30 outputs the clock output ZM, ? Clock pulse CP is output at 01.

In the mode shown in FIG. 5(c), the count output of the byte address up/down counter 25 is incremented after the first byte image data is transferred, and the byte address is incremented after the second and third byte data is transferred. It is sufficient to increment the up/down counter 26 and at the same time increment the line address counter 26. Therefore, after transferring the first byte of image data, the address control unit 30 uses the clock output terminal, ? Clock pulse C on 02
P? Output [After the transfer of the 7th and 2nd byte data from both sides, a clock pulse C is sent to the clock output terminal -f-301 and 303.
The power to output P is fine.

The address control unit 30 operates in a two-way manner depending on the data transfer mode 1τ. No. 61.1 is a circuit diagram showing an example of a specific configuration of the address control section 30. The operation of the sixth shifter 1 will be explained below based on the three data transfer modes mentioned above.

Here, each bit of the mode register 24 is named p(, HV, V, H) shown in FIG. 6, and each mode and each bit data are associated as follows.

In the mode shown in Fig. 5(a), HV, V, H = 0°12
- 0.1 #5 Figure 1(b) Nomo-1 #) %, 'HV, V, I
I=o, i, .

The mode of Figure 5 (c) and p, IIV, V, H = 1,
0. 0 Yes, the clock pulse CP is a positive pulse.

First, the mode (τ) shown in Figure 5(a) will be explained.

(j7) mode, HHV, V, H = 0, O, I, so NAND circuit, 91 out of 91 to 34.
Only when the gate is fully opened in response to the clock pulse CPK. In this case, the phase of the clock pulse CPU is inverted, and the negative polarity pulse and 1. The signal is output from the NAND circuit 3 and supplied to one input terminal of the AND circuit 35. At this time, since the output of the NAND circuit 34 supplied to the other input terminal of the AND circuit 35 is always at the 1" level, the clock pulse CP is output to the negative polarity switching clock output terminal, q o z. In this way, in the mode shown in FIG.
The count output of 5 is incremented.

Next 1/i17 Figure 5 ([]) The seventh card will be explained and explained. In this mode Id:,)IV,V,H=0. ], O
Since only the v bit has a 1" point, the clock pulse cpa NAND circuit 32, AND circuit 36 sides 1
0 However, in this case as well, the clock pulse CP is output with a pulse of negative polarity and 1~. Therefore, the total p il- force of the Raicia 1-Res counter 25 is incremented. Ne7ru.

Next, regarding the mode of Section 541 (C), refer to all of Figure 7.
While explaining. In this mode, )(V, V, H
= 1.0.0, so only the HV bit becomes ``1'', so the outputs of the NAND circuits 91 and .92 are always ``.
]". Also, at the falling timing of the latch pulse L1 shown in FIG. 7(a) K, the Q output of the D flip-flop circuit 37 becomes "O" as shown in FIG. 7(c) I/i7. The initial setting is as follows. Therefore, 1
The clock pulse CP (see FIG. 7(b)) output to the image data transfer unit for the byte is the 7th byte.
*As shown in (h), a NAND circuit 34 and an AND circuit 35
is passed through the groove and guided to the output terminal 302. therefore,
The counting output of the bypass up/down counter 26 is incremented.

At this point, at the falling edge of the clock pulse CP, the state of the D flip-flop circuit 37 is inverted ζN2, as shown in FIG.
) As shown by K<, the Q output becomes high level. Therefore, the clock pulse CP is as shown in FIG. 7 (f), (i
), now the NAND circuit 33 and the AND circuit, q
It passes through 6f and 15 σ is applied to the output terminals 301 and 303.

As a result, the count output of the line address counter 25 is incremented, and the count output of the byte address up/down counter 26 is decremented. In the figure, 389, 79id' inverters are shown.

According to the embodiment described in detail above, as an initial setting, the transfer mode data is set to the mode register 24 = 15-, and the address data at the beginning of the address to be entered into field 1 is set to the counters 25 and 26. By simply setting the data to be transferred to the memory 22 one after another in the data register Z3, the address control section 30 automatically controls the operation of specifying the address in accordance with the data transfer mode. Therefore, the CPU 2 does not need to set address data every time image data is transferred, which improves transfer curvature and reduces software load.
It is possible to plan.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an automatic control device that improves data transfer efficiency and improves processing by CPU software.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing a method for directly transferring data from the CPU to memory, and Figure 2 is a circuit diagram showing how data is transferred directly from the CPU to memory.
FIG. 3 is a circuit diagram showing an embodiment of the automatic address control device according to the present invention; FIG. 4 is a screen diagram of a captain system, teletext system, etc. A diagram showing the configuration, FIG. 5 is a diagram showing three examples of data transfer modes,
FIG. 6 is a circuit showing an example of a specific configuration of the address control section shown in FIG. 3. FIG. 7 is a timing chart for explaining the operation of FIG. 6. 2) CPU, 22 Memory, 23 Write data register, 24 Mode register, 2
5...Line address counter for writing, 26...
・Byte address up/down counter for writing,
27... Address decoder, 28... Write access control unit, 29... Buffer gate, 30...
Address control section, 31-34... NAND circuit 1. 'r
5. ．． '46...AND circuit, 37...97971
7071 circuit, 3B,, 99...inverter circuit.

Claims (1)

[Scope of Claims] A storage means for storing all data written into the memory (+'+1,000). a transfer mode storage means for outputting address data for specifying a write address of the input data to the memory; and initial setting means for setting a previous h1 transfer mode storage means to a previous h1 transfer mode storage means, and setting at 1/s data indicating a first address of the above-mentioned h1 transfer address to the counter means. and address control means for switching the output data of the previous *++ counter means each time the mode data is transferred to the previous H1-"memory in accordance with the Mizuko mode, and the written data that is not stored in the data storage means is transferred to the previous H1-"memory. Address automatic control laceration.