JPS59151332U - Memory circuit control device - Google Patents
Memory circuit control deviceInfo
- Publication number
- JPS59151332U JPS59151332U JP4633383U JP4633383U JPS59151332U JP S59151332 U JPS59151332 U JP S59151332U JP 4633383 U JP4633383 U JP 4633383U JP 4633383 U JP4633383 U JP 4633383U JP S59151332 U JPS59151332 U JP S59151332U
- Authority
- JP
- Japan
- Prior art keywords
- memory circuit
- block
- control device
- setting means
- circuit control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はマイクロプロセッサを用いた一般回路を示すブ
ロック図、第２図は本発明の基本回路を示すブロック図
、第３、図１．２はマスクＲＯＭおよびＰ−ＲＯＭの構
成を示す説明図、第４図は本発明の具体回路例を示す電
気回路図である。
２Ａ、 ２Ｂ、 ２Ｃ・・・・・・マスクＲＯＭ、
３・・・・・・プログラマブルＲＯＭ、５・・・・・・
ブロック設定回路、６・・・・・・アドレス設定回路。Fig. 1 is a block diagram showing a general circuit using a microprocessor, Fig. 2 is a block diagram showing a basic circuit of the present invention, and Fig. 3 and Fig. 1.2 are explanatory diagrams showing the configurations of mask ROM and P-ROM. , FIG. 4 is an electric circuit diagram showing a specific circuit example of the present invention. 2A, 2B, 2C...Mask ROM,
3...Programmable ROM, 5...
Block setting circuit, 6...address setting circuit.
Claims (1)
と、制御プログラムの変更プログラムをブロック分けし
て格納する補助記憶回路と、変更にかかる各記憶回路の
ブロックを選択するブロック設定手段と、選択動作に基
づき補助記憶回路のブロックをアドレス指定するアドレ
ス設定手段とから成る記憶回路制御装置。A main memory circuit that stores a control program in blocks, an auxiliary memory circuit that stores a control program change program in blocks, a block setting means for selecting a block of each memory circuit to be changed, and a block setting means for selecting a block of each memory circuit to be changed. and address setting means for addressing a block of the auxiliary memory circuit based on the address setting means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4633383U JPS59151332U (en) | 1983-03-29 | 1983-03-29 | Memory circuit control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4633383U JPS59151332U (en) | 1983-03-29 | 1983-03-29 | Memory circuit control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59151332U true JPS59151332U (en) | 1984-10-09 |
Family
ID=30176886
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4633383U Pending JPS59151332U (en) | 1983-03-29 | 1983-03-29 | Memory circuit control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59151332U (en) |
-
1983
- 1983-03-29 JP JP4633383U patent/JPS59151332U/en active Pending
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