JPS59149545A - Data error correcting system - Google Patents

Abstract

PURPOSE:To process a large quantity of data continuously and at a high speed by reading in the next data block while one data block is corrected. CONSTITUTION:A memory RAM has three areas, and these areas are switched in response to the value produced from a counter 3CNT. The input data is written to the memory RAM. When the 1st data block is read out for correction, the 2nd data block is read in. The 1st data block is supplied to a syndrome register SSR for check of errors. Thus an error is detected while the data is supplied to the SSR. Then the data is corrected with an adverse shift given into the SSR. The tested data block is written into the RAM again, and the corrected information is read successively out of the RAM.

Description

[Detailed description of the invention] The present invention relates to a data error correction method.

Conventionally, in order to check whether there is an error in the data being sent, or if there is an error, where in the data the error is, a specific code is added on the side sending the data. There was an idea of transmitting the code string and processing the data with such a code string on the receiving side to correct errors. For example, as shown in Computer Fundamentals Course 181' Shokodo Publishing, the data to be sent is processed, a shortened cyclic code is created, the shortened cyclic code is transmitted along with the above data, and the receiving side processes them. This is a method of correcting the data by checking whether there are errors in the data and where the errors are. However, the conventional correction method described above performs the above-mentioned processing on the next code string after passing through the three steps of reception, inspection, and correction of code number 1. Therefore, it was not suitable for handling extremely large amounts of data continuously and at high speed.

In view of the two points, the present invention provides a data error correction method that can quickly correct data errors in a code string.

In view of the two points, the present invention provides a burst error correction method that can quickly correct burst errors in a transmitted code string.

Other objects of the present invention will become clear from the following description of embodiments with reference to the drawings.

One piece of data sent to help understand the content of the present invention is 96 bits, which includes 179 bits for information points and 17 bits for correction code.

An embodiment according to the present invention will be described below.

FIG. 1 is a block diagram illustrating one embodiment of the present invention.

In the figure, IDL is a signal line to which input data is sent. Here, the length of one piece of data is 96 bits, and multiple pieces of data are sent successively. MPX
is a multiplexer, which has three input sections, multiplexes them, and outputs them. RAM is memory, signal line IDL
It temporarily stores data sent through the circuit, input data inspected by a circuit described later, and input data corrected. Here, the memory capacity is, for example, 51
There are 2 hits. Further, Di is an input section of the memory, Do is an output section of the memory RAM, and R/W is a terminal for applying signals for reading and writing to the memory. AD is memory RA
This is an address application unit for accessing M. ADDS
is an address shifter, which generates an address for accessing the memory RAM based on three counters to be described later. 4CNT is a quaternary counter, and the count value of this counter is provided to switch between storing input data, outputting to the testing circuit, inputting from the testing circuit, and outputting data, as shown in FIG. The carry is the input clock of the counter 192CNT.

Furthermore, the color converter 4CNT operates with a 6.144 MHz clock, which is also applied to the address shifter ADDS. 192cNT is a 192-decimal counter that increments with the carry of counter 4CNT. Addr the contents
It is expressed as 3CNT is a counter, counter 192CN
The T carry is used as a clock to receive the ball. This counter divides the memory RAM area into three areas, and the contents change each time. 6ENC is an encoder, and counter 3CN is an encoder.
Depending on the value of T, the three areas I, m, and n take values as shown in FIG. 6, which are repeatedly generated. SR is a shift register that can be reversibly shifted and has a capacity of 8 pins. mod2 is an adder that outputs an addition result without a carry.SSR is a syndrome register that can be reversibly shifted and has a capacity of 17 bits.FIG. 2 shows a more detailed block 1Δ of the syndrome register SSR. In the figure, EOI-EO5 are exclusive OR gates, and SRI, SR2, and SR3 are bidirectional shift registers. Exclusive OR gates EO4-EO5 are used for correction.Shift registers 5R1-SR3 and exclusive OR gates EOI-EO5 are switched and operated depending on the mode.ZD is 0.Detector Then, the contents of 9 pins of the syndrome shift register SSR, that is, F8 to F16 are changed.DMPX is a demultiplexer and restores the three multiplexed data.

Data error correction will be explained with reference to a block diagram of the above-described configuration and a timing chart.

The information sent here has a code length n=96, a number of information points of -79, and a correction code length 17. Information with code length n=96 is sent serially every 125 microseconds as shown in FIG. First, it is assumed that each part in the block diagram shown in FIG. 1 is in an initial state. The above information is stored in the memory RAM via the signal line IDL and multiplexer MPX. The storage location on the memory RAM is the counter 192.
An encoder ENC that outputs the values of l, m, and n based on the values of CNT, counter 4CNT, and counter 3cNT.
The address shift l A D D S is 192 CNT.
It is determined by executing the calculation of /2+lX128, and one piece of information having a code length of 96 is written to the memory RAM in the first state of the counter 4CNT (for example, when the count is 0).

When the 96 pieces of information are written to the memory RAM based on the addresses determined as described above, the inspection of the 96 pieces of data stored in the memory RAM begins as shown in FIG.

Further, information of the next code length 96 is stored in the memory location determined by the calculation of the memory 7 address as described above. It will be appreciated that since the value of the counter 3CNT is changed and the value of 1 is changed, the first information (data block) is stored in a 128 hit position different from the memory block for inspection. Initial code length 96 stored in RAM
The information is 192 CN T in Address Chic ADDS.
It is produced and read out under the operation + m ×128.

Since the value of m is O as shown in FIG. 6, the information of the first code length 96 is outputted from the mechanized RAM to the second state of the counter 4CNT (for example, when the count is 1). The information output from the memory RAM is sent to the demultiplexer DM.
PX, applied to multiplexer MPX via syndrome register SSR and shift register SR,
192CNT-8+m by address shifter ADDS
is stored at the memory address obtained by the calculation.

It is rewritten in the third state (for example, count 2) of the counter 4CNT to the location where the initial code length 966'' information is stored.

1-While rewriting is performed as described above, the first code length 96 information output from the demultiplexer DMPX is input to the syndrome register SSR and checked for errors. In the check process, exclusive OR gates E01, FO2, and FO3 shown in FIG. 2 operate, and shift registers SRI to SR3 shift information to the right. Information with code length 96 is stored in syndrome register SS
At the point when it enters H, F of shift register 5RI-SR3
If there is a 1 in 8 to F16, it indicates that there is an error, and if there is no 1, it indicates that there is no error. Such inspection is
This is done on the detector ZD.

” - When the above-mentioned inspection process is completed, the process moves to the correction process. This process is performed by determining that the content of the counter 192CNT has reached 95, and is performed regardless of whether there is an error or not. An explanation will be given in case there is an error.

At the end of the inspection process, the O detector ZD checks whether there is a 1 in F8 to F16, and if the result of the check is 1,
The OR gates EO4 to EO'5 are activated to shift the shift registers 5RI-3R3 in the opposite direction. 19'l -192C of the address shifter at such L
By the operation of NT-8+mX 128, the contents of the shift register SR are also reversely shifted and stored in the memory RAM, and at the same time, the verified information stored in the memory RAM is transferred to the address register SR by the address shifter ADDS.
-192cNT-8+mX128 is read from the address determined by the calculation result.

When F8 to F16 becomes O, the bit of information corresponding to the location where the error occurred in the data in FO-R7 becomes 1, and this bit is transferred to shift register SR.
and the contents of adder mod2, and shift register SR
Return to. Such processing corrects errors.

Shift information with a code length of 96 in the opposite direction like J double series, and store it in the memory RAM by address chic ADDS to 191-
It is stored at a memory address determined by the result of the operation of 192CNT-8+mX128.

] - After 250 microseconds have passed, the information that has been inspected and corrected as described above is sequentially read out from the memory address determined by the calculation of 192CNT/2+nX128 by the address chic ADDS, and then sent to the demultiplexer D.
Output via MPX.

In the embodiment described above, an 8-bit shift register and memory were used, but two 96-bit shift registers were provided,
Two syndrome registers are used. First, information is input into the first 96-bit shift register, and the same information is input into the first syndrome register at the same time for inspection. Then, information is input into the second 96-bit shift register. The contents of the first syndrome register are input in parallel and shifted in the opposite direction, and the contents of the first syndrome register are input in parallel to the second syndrome register and shifted in the opposite direction. It is checked whether the predetermined contents of the syndrome register are 1, and if so, the contents of the second syndrome register are added to the contents of the second shift register as in the above-mentioned next command to correct the information. Therefore, information can be inspected and corrected with a delay of 125 microseconds.

As described above, according to the present invention, sent information can be processed continuously, so it can be processed faster than in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIG.
The figure is a diagram explaining the syndrome register, Section 3.4.5
．． FIG. 6 is a diagram explaining the timing. SR is shift register RAM is memory 5DDS is address shifter Applicant: Canon Corporation

Claims (1)

[Claims] A data error correction method that performs at least a data block correction on a data block containing a correction code while inputting a data block containing a correction code and subsequently inputting a data block containing another correction code.