JPS5914928B2 - Line display signal generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for generating a line display signal, such as a scanning signal for, for example, a radar PPI display.

Both an analog method and a digital method are used as methods for performing PPI scanning used in radar display devices.

Although the digital method was superior in terms of accuracy, it was one step ahead of the analog method in terms of circuit complexity, cost, and appearance.

In particular, a clean appearance is very important for a display device, but in the case of digital PPI scanning, the signal has a discrete staircase waveform, so the display becomes grainy.

If the number of constituent pits is increased to subdivide this staircase, it can be seen as a continuous straight line when viewed with the naked eye, resulting in a cleaner appearance, but in this case, the conversion speed of the DA converter can be reduced. There is a problem of having to do it quickly.

An object of the present invention is to provide a line display signal generation device that can display smooth lines even when using a DA converter with a relatively slow operating speed.

According to this invention, the coordinate signal is generated as a digital quantity,
This coordinate signal is stored in a register at regular intervals.

The contents of this register are converted into an analog signal by a DA converter, and a plurality of delayed signals are created by applying different delays to the analog signal by a delay means, each having an amount shorter than the first period constant period.

These delayed signals are added to form a line display signal.

In this way, even if the operation of the DA converter is relatively slow, the delay means interpolates the data and provides a smooth display.

Next, an embodiment of the line display signal generating device according to the present invention will be described with reference to the drawings.

In this example, a scanning signal for displaying PPI of a radar is generated, and a signal of, for example, two inverted signs indicating the rotational angular position of the radar antenna is supplied from a terminal 11 to a sine and cosine signal generator 12. Ru.

The sine and cosine signal generator 12 is, for example, a read-only memory, which uses the input angular position signal as an address and outputs the sine (sin) and cosine (cos) of the angle as digital quantities (2 inverted symbols), respectively. .

These register 1 every time the input address changes.
They are set to 3x and 13y, respectively.

The contents of these registers 13 By multiplying, pulses with frequencies corresponding to N5inθ and Ncosθ are obtained.

This multiplication operation starts with the radar A trigger from the terminal 16 and ends with the one-scan end signal EO8 from the overflow detection circuit 17.

Each pulse train of the multiplication outputs N5inθ and Ncosθ is counted by counters 18x and 18y, respectively.

When the counters 18x, 18y are about to overflow, an overflow detection circuit 17 detects this and generates a scan end signal EO8, which is supplied to the gate oscillation circuit 14, in order to prohibit counting beyond the displayable area.

The count contents of the counters 18 x and 18 y are transferred to registers 21 x and 21 y through display distance switching (hereinafter referred to as range switching) circuits 19 x and 19 y.

The above-mentioned part is the P of the conventional rate multiplier method.
Although they are also used in the PI scan generation circuit, in order to facilitate understanding of the present invention, a specific example of the gate oscillation circuit 14, rate multiplier 15x, and range scale 19x is shown in the second section.
This will be explained in the figure.

Radar A from terminal 16 in gate oscillation circuit 14
The flip-flop 22 is set by the trigger, and the gate 23 is opened by the set output.

This gate 23 receives E from the overflow detection circuit 17.
The flip-flop 22 is reset and closed by the O8 signal.

While the gate 23 is open, the clock from the oscillator 24 is applied to the rate multiplier 15x through this gate 23.
The signal is supplied to the binary counter 25 in the inner part and counted.

The 1/2 frequency divided output to the 1/23 frequency divided output of the counter 25 are obtained from the AND circuits 26□ to 26s, and these are ANDed.
S-bit signals 11-Is indicating sin θ of the register 13x and the output of the gate 23 are supplied to the circuits 26□-26s, respectively.

The outputs of the AND circuits 26□ to 26s are sent to the binary counter 1 as the output of the multiplier 15x through the OR gate 27.
8x.

Therefore, a pulse signal with a density equal to the value multiplied by the number of output pulses NKsinθ of the gate 23 is obtained.

These pulses are counted by a binary counter 18x, and any successive counting stage of this counter 18x is selected by a range signal.

The number of counting stages to be selected is determined by how many bits represent the length of one scanning line, and the longer the detection distance, the higher the counting stage is selected.

In the figure, the range signal from the terminal 28 is used to select either the gate G1 group or the gate G2 group, thereby switching between the two ranges.

Returning to the explanation of FIG. 1, in the conventional device, the signal selected by the range scale 19x t 19y is converted into an analog signal by the DA converters 31x and 31y each time the least significant bit changes. These converted signals are sent to a deflection amplifier 32X.

32y to the deflection device 34 of the cathode ray tube 33.

The output of the video amplifier 35 of the radar receiver is used to modulate the brightness of a cathode ray tube 33 through a brightness control circuit 36, and the cathode ray tube 33 is supplied with a required voltage from a high voltage power supply 37.

For example, as shown in FIG. 3, the output of the rate multiplier 15x becomes narrower as the angle θ becomes larger (
The pulse interval changes depending on the angle θ.

These pulses are counted by a counter 18x and directly sent to the DA.
When converted into an analog signal by the converter 31x, the output thereof is as shown in FIG. .

Therefore, the DA converters 31
It is necessary to operate with a change period Δt.

In order to make the display smooth and not rough, it is necessary to increase the number of bits forming one scanning line, and accordingly, the DA converters 31 x and 31 y that operate at high speed are required. It is difficult to obtain a DA converter that operates at a high enough speed to provide a good display.

In this invention, signals are stored in the registers 21x and 21y at regular intervals, and the DA converter 31X.

Create a plurality of delayed signals each giving a different delay shorter than the above-mentioned constant period to the converted output of 31y,
These are added and supplied to the deflection amplifier.

That is, as shown in FIG. 1, the oscillation output of the gate oscillation circuit 14 is frequency-divided by the pulse frequency divider circuit 38, and the frequency-divided output is used to set the registers 21x and 21y.

For example, as shown in FIG. 2, the pulse frequency divider circuit 38 is supplied with a shift register 39 which is shifted by the output of the gate 23 of the oscillation circuit 14, and the outputs of a plurality of shift stages thereof, and the output is fed back to the first stage. NAND circuit 41 and NA
It is composed of an inverter 42 that inverts the output of the ND circuit 41 and a delay line 43 that matches the phase of the inverted output with the outputs of the range scales 19x and 19y, and the output of the delay line 43 becomes the output of the frequency dividing circuit 38.

The delay line 43 is terminated with a non-reflective resistor 40.

The outputs of the DA converters 31x and 31y are each connected to a delay line 44.
x t 44 y, these delay lines 44x,
Taps are derived from 44y, and these taps are connected to summing resistors 45X1 to 45xk and 45yx to 4, respectively.
5yk to the input side of the summing amplifier 46 x t 46 y.

The delay lines 44x, 44y have non-reflection terminations 47x, 47
It is terminated at y.

The outputs of summing amplifiers 46x, 46y are provided to deflection device 34 through deflection amplifiers 32x, 32y, respectively.

Summing amplifier 46X. 46y has a feedback resistor 48 x t
48 y are connected respectively.

A plurality of delayed signals with different delay amounts are obtained through the delay lines 44x and 44y.
It is made shorter than the set pulse period for 1 x t 21 y.

For example, delay line 44X. 44y taps are placed at equal intervals, and the maximum delay is selected to be the set pulse period minus the amount of delay between adjacent taps.

Taking one delay line 44x side as an example, FIG. 5 shows a case where there are four taps.

Each resistance value of resistors 45X1 to 45X4 is set to R1 resistor 48.
If the resistance value of x is R/4, and a staircase waveform input E as shown in FIG.
2, 45X3, and 45X4 have signals S, c, and d sequentially delayed by T1, respectively, and these and the input E are added with the amplitude of 1/4 of each in the summing amplifier 46x. An output e is obtained.

The period T in which the level of the input E changes is the set period for the register 21x, the delay time of the delay line 44x is D, and the delay time between adjacent taps is T1,
T=D+T1 is selected, and therefore, the output e is divided into k=4 by the increase in the input E within the period T, and increases sequentially every period T1.

In other words, changes in the input cycle T are interpolated, resulting in smooth changes.

The delay line 44y side operates similarly.

As described above, in this invention, the DA converter 31x
, 31y operating speed is in register 21X.

The DA converter 31X only needs to be operable with respect to the change period of the contents of the signal 21y, that is, the period T of the set pulse from the pulse frequency divider circuit 38.

The change in the output of the 31y is fast (even with a period T, but the change in this period T is interpolated by a plurality of delay signals by the delay line 44 It doesn't look jagged.

In addition, as shown in FIG. 4, in the conventional method, the period of change in the output of the DA converter is not constant, and the amplitude of the change is constant, but in this invention, as shown in FIG. 7, the output of the DA converter is The period of change is constant as shown by curve 51, and the amount of change in amplitude is different, and the output of the summing amplifier becomes a signal with a small period and small amplitude change as shown by curve 52.

If the output pulse frequency of the gate oscillation circuit 14 is made relatively high as in the above example, the amplitude precision of the output of the DA converter becomes high, and high precision can also be obtained by the above-mentioned interpolation.

In the above description, the present invention was applied to the scanning of a digital PPI display, but the present invention can also be applied to the case where X, Y coordinate signals are supplied as digital signals in so-called cathode ray tube display devices, XY recorders, etc. It can also be applied to display cases.

[Brief explanation of drawings]

FIG. 1 is a system diagram showing an example in which the line display signal generator according to the present invention is applied to a radar display device, and FIG.
FIG. 3 is a waveform diagram showing an example of a pulse train of N5inθ, and FIG. 4 is a conventional digital scanning device OD.
A waveform diagram showing the output of the A converter, Figure 5 is a diagram showing the delay and addition circuit portion, Figure 6 is a waveform diagram showing its operation, and Figure 7 is a waveform diagram showing the output of the A converter.
The figure is a diagram showing a DA converter output waveform and a summing amplifier output waveform. 21 x t 21 y: Register as coordinate signal source, 31x, 31y: DA converter, 33: Cathode ray tube, 3
4: Deflection device, 38: Circuit for generating set pulses for registers 21 x and 21 y, 44X. 44y: Delay line, 46 x y 46 y' summing amplifier.

Claims (1)

[Claims] 1. A coordinate signal source that generates a coordinate signal as a digital quantity, a register in which the coordinate signal is stored at a constant period, a DA converter that converts the contents of the register into an analog signal, and the above-mentioned constant value for the conversion output. A line display signal generating device comprising: delay means for generating a plurality of delayed signals by applying different delays shorter than a period; and an adding circuit for adding these delayed signals to form a line display signal.