JPS59148193A - Information processor - Google Patents

Abstract

PURPOSE:To attain continuous access to a main memory and to accelerate the processing speed by converting a part of the request address to a buffer memory into the prescribed address of the main memory. CONSTITUTION:A main memory 300 is provided together with a buffer memory 200, a central processing part 100, an address register 110, a data register 120, address converting part 251 and 252, and an address selecting part 253 respectively. When an access is given to the memory 200, whether the request data information exists inside the memory 200 is checked by an address array. If no data information exists, a data block to be replaced is decided by a replace array. While the contents of the data block to be replaced are written to the corresponding address of the memory 300 in case it is indicated that the contents of the data block are already changed by the change bit on the address array corresponding to the data block to be replaced. Then the contents of the requested address on the memory 300 are written into the data block.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to control of a buffer memory in an information processing device, and particularly to improvement of a correspondence system between buffer memory addresses and addresses on a main storage device.

(Prior art) Conventionally, in store-in buffer memory,
If requested data information misses in the buffer memory, a new data block to be replaced is determined and the data information on the main memory is loaded into that data block, but before that, the data block is Check whether the data information has already been rewritten, and if it has been rewritten, perform the write operation of Fang 1 to write the data information of that data block to the main memory, and then write the requested data information. A write operation of the tooth 2 is performed to read from the main memory and write to the buffer memory.

At this time, the address of the main memory to which the data information from the buffer memory is written is the same as the address of the part of the address information read from the main memory that indicates the internal bank of the main memory. Ta.

Since the main memory device employs an interleaved structure in bank units, access can be made quickly when different banks are used, but there is a problem in that the cycle time is long when the banks are the same.

Therefore, in the conventional device having the above configuration, there are two operations: a write operation to write the contents of the buffer memory to the main memory, and a read operation to read the contents of the main memory to the outside. There is a drawback that it is not possible to perform fil'1 in succession no matter what sequence order is used.

Therefore, in this specification, in order to clarify the scope of the present invention, the configuration and operation of a conventional information processing device will first be explained.

FIG. 1 is a block diagram showing the configuration of an example of a conventional information processing device.

In FIG. 1, the information processing device includes a central processing unit 100,
an address register 110, a data register 120,
It includes a buffer memory 200 and a main storage device 300, and the buffer memory 200 includes a data array 210, an address array 220, a replace array 230, a buffer control section 240, and an address conversion control section 250. .

In Figure 1, the central processing unit 100 is connected to a buffer memory 200 via an address register 110 and a data register 120, and the buffer memory 200 is connected to a main storage device 300.

The address array 220 is the main memory 30 of data blocks corresponding to the contents stored in the data array 210.
0 and a change bit indicating whether the contents of the data array 210 have already been rewritten.

The central processing unit 100 sends a read request or a write request for address information to the buffer memory 200 via the address register 110.

Upon accepting a read request, the buffer memory 200 determines whether the requested address information exists in the data array 210 inside the buffer memory 200.
20, and if it exists, the requested address information is sent from the data array 210 to the central processing unit 100 via the data register 120.

If the address array 220 checks the existence of the above information and it is found that the corresponding information does not exist, the replace array 230 determines the next data block to be replaced within the data array 210, and then replaces the data block corresponding to that data block. Read the change bit of the address array to check whether the data block has already been changed. As a result, if it is found that the data block has not been changed as described above, the buffer control unit 24
0 is the contents of the corresponding data block address array 2
The main storage device 3 according to the address information successively output from 20
Write to 00.

Thereafter, in order to read the contents of the data block containing the requested address information, a read request is sent from the central processing unit 100 to the main storage device 300, and if the requested information is returned, the replacement array Write to the data block determined by 230.

In addition, if the change bit does not indicate a change in the data block, a read request is immediately sent without writing the contents of the corresponding data block to the main storage device 300, and the returned data information is read. Write to that data block.

On the other hand, when a write request is accepted, it is checked whether the corresponding data block exists on the data play 210 using the same method as for reading, and if it exists, the data is written there. If it does not exist, the same processing as in the case of reading is performed to read the data information of the corresponding data block from the main storage device 300.

Here, in the case of reading, the corresponding data information is written to the data array 210 of the buffer memory 200, but in the case of writing, the requested address information in the corresponding data block is used as the write data. After replacing, write this to data array 210.

Furthermore, after the write operation, the change bit is rewritten to indicate that the change is complete (().

In the above operation, if the change bit does not indicate a change in the data block, there is no problem since only a read request is sent to the main storage device 300. If it shows,
A read request is sent to the main storage device 300 immediately after a write request is sent.

By the way, in the main memory device 300, the cycle time of the memory elements is slower than the operating speed of the buffer memory 200 and the central processing unit 100, so in order to fill the speed gap, data blocks are organized into banks on the main memory device 300. In order to have a one-to-one correspondence with each other, and to have multiple banks to enable continuous access within a data block, as well as to enable continuous access between different banks, It has an interleaved structure.

Therefore, consecutive accesses to different banks are possible, but consecutive accesses to the same bank require waiting for at least a time corresponding to the cycle time of the memory element, and consecutive accesses are impossible.

Due to the above operation, if no conversion is performed on the requested address, when the write address to the main memory 200 is compared with the next consecutive read address, although the upper address is different, the bank address is always the same. Become the same.

Therefore, a read request after a write request is made to wait for a time corresponding to the cycle time of the memory element.

(Objective of the Invention) A first and second address conversion section and an address selection section are provided, and the operation of writing data from the packer memory to the main storage device and the operation of reading data from the main storage device to the buffer memory. The above disadvantages are solved by controlling the bank addresses so that there is less opportunity for both bank addresses to match, and the operation of writing data information from the buffer memory to the main memory device and the operation of writing the data information from the main memory device to the main memory device are performed. An object of the present invention is to provide an information processing device configured to be able to continuously perform an operation of reading data information into a memory.

(Structure of the Invention) An information processing device according to the present invention includes a main memory, a buffer memory, a central processing unit, an address register, and a data register.

Main memory is interleaved with bank degrees,
It is used to store data information and address information.

The buffer memory is controlled by a store-in button and is used to store a copy of main memory.

The central processing unit is for executing processing based on data information and address information K exchanged with the main storage device via the buffer memory.

The address register is placed between the central processing unit and the backup memory and is used to store address information.

The data register is placed between the central processing unit and the backup memory and is used to store data information.The buffer memory has a data array, an address array,
It is equipped with a replacement array and address conversion selection means.

Data arrays are for storing data information. The address array is used to set address information bits for data information included in data blocks stored in the data array and change bits to indicate that the data information in the data blocks has been rewritten. be. Replace play is used to indicate a data block to be replaced when replacing a data block stored in a data array.

The address translation selection means forms at least a part of the request address and indicates a bank of the main memory by an upper address other than the set address used to indicate the buffer address of the request address. It converts bank addresses,
It is equipped with a first and second address conversion section and an address selection section.

In the information processing device according to the present invention, when accessing the backup memory, the address array is used to check whether or not the requested request data information exists inside the buffer memory. If not, determine the data block to be replaced by the replace array, and if the modified bit on the address array corresponding to the data block to be replaced indicates that the contents of the data block have already been modified. , performs the operation of writing the contents of the data block to be replaced to the corresponding address in the main memory, and further writes the contents of the main memory at the requested request address to the 7'-ta block. Do the wrong move.

Therefore, the backup memory can be accessed in accordance with the bank address converted by the address conversion selection means.

(Example) Next, the present invention will be described in detail with reference to the drawings.

FIG. 2 partially shows the configuration of an embodiment of an information processing apparatus according to the present invention.

In FIG. 2, the information processing apparatus includes Fang 1 and a second address converting section 25L 252 instead of the address conversion control section 2500 in Fang 1, and also includes an address selection section 253.

As shown in Figure 3, the first address conversion unit 251 converts the corresponding lower two bits of the request address indicating the bank and the lower two bits of the upper address of the set address information. Exclusive OR is performed for each bit.

In addition, the address converting unit 252 of Fang 2 performs an exclusive OR for each corresponding bit of the lower two bits of the address information set in the address array 220 as the upper address and the address bit for indicating the bank. Take.

Here, the address conversion unit 252 of the fang 2 is the data array 2
It is controlled to be replaced only when the contents of 10 are read out and written to the main storage device 300. Further, the address selection unit 253 selects the address array 220 side or the address register 110 side depending on whether a high-order address is written or read out of the address information of the main storage device 300. .

1. Request address A is address register 110
Assuming that it was sent to , the request address A
Assume that the upper address is AO1, the lower address is B3, and the bank address is 3. At this time, there is no corresponding data information on the data array 210, and the replace array 230 replaces the data array 21 with the corresponding data information.
Assume that position Tjo on 0 is selected for replacement.

As shown in Figure 2, the data block on location IJO is given by Xo and the bank address on data array 210 is B3. When reading those data and writing them to the main storage device 300, the Tsuta bank address is 1 because the address of the corresponding address array 220 is A3.
・By the address conversion unit 252 in FIG. 2, )・X on the main storage device 300 in FIG.

The request address A sent to the address register 1.10 is Y on the main storage device 300 shown in FIG.
o, and the bank address is BO3, so X'o
K is in a different bank from Xo to which the contents of K should be written.

Therefore, even if these two requests are successively sent to the main memory bag filt300, the subsequent requests will be processed without having to wait.

As described above, in the above embodiment, the buffer memory IJ 20
The data read from 0 was first written to the main memory device 300 and then a read request was sent to the main memory device 300, but the read request was also sent to the main memory device 300 first and then The contents of the buffer memory 200 are read out, and after the reading of the main memory device 300 is completed, the data read out from the previous buffer memory 200 is transferred to the main memory device fIL30.
Even in the case of writing to 0, the above configuration reduces the probability that different blocks will be accessed by the same address, making continuous access possible.

(Effects of the Invention) As described above, the present invention replaces address information indicating the bank of the main memory device among the requested addresses to the buffer memory with address information indicating the address information of the backup memory among the above-mentioned addresses. By configuring the conversion to be performed using an upper address other than the set address, accesses to the main memory device are not made to wait and are accessed continuously, resulting in an effect that the processing speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional information processing device. FIG. 2 is a block diagram showing an embodiment of the present invention constructed by partially improving the information processing apparatus shown in FIG. Figure 3 is a flowchart showing the flow of control of the address conversion units of Fang 1 and Fang 2 in Fang 2. 100...Central processing unit 110...Address register 120...Data register 200...Backup memory 210...Data array 220...Address array 230...Replace array 240...Buffer control Part 250...Address conversion control unit 251.252...Address conversion unit 253...Address selection unit 300...Main storage device patent applicant Hisashi Inoro, patent attorney representing NEC Corporation

Claims (1)

[Claims] A main memory for storing data information and address information interleaved in units of punctures, a buffer memory for storing a copy of the main memory using a store-in method, and a central processing unit for executing processing according to the data information and the address information exchanged with the device; and an address register for storing the address information between the central processing unit and the buffer memory. and a data register for storing the data information between the central processing unit and the buffer memory, and a data array for the buffer memory to rewrite and store the data information for each data block. and an address for setting an address information bit of data information included in the data block stored in the data array and a change bit for indicating that the data information of the data block has been rewritten. an array, a glue brace play for indicating a data block to be replaced when replacing the data block stored in the data array, and a set used for indicating a buffer address of the request address. address conversion selection means for converting a bank address that forms at least a part of the request address and indicates a bank of the main storage device according to an upper address other than the address of the buffer memory; When accessing, the address array is used to check whether the requested request data information exists inside the buffer memory, and if the request data information does not exist inside the backup memory, the request data information is accessed. Determine a data block to be pre-replaced by a replace array, and determine whether the content of the data block to be replaced has already been changed by the modified bit on the address array corresponding to the data block to be replaced. If so, perform an operation to write the contents of the data block to be replaced to the corresponding address in the main memory, and further write the contents of the data block to be replaced in the main memory at the requested address. The address conversion selection means &
An information processing apparatus characterized in that the buffer memory can be accessed in accordance with the bank address converted by.