JPS59147541A - Ecl logical circuit - Google Patents

Abstract

PURPOSE:To keep the logical amplitude constant by applying negative feedback control to the current of a current source of a logical circuit depending on the fluctuation of logical amplitude. CONSTITUTION:A block 1 surrounded by dotted lines is a 3-input NAND circuit stacked longitudinally in three stages with emitter coupled logical ECL gates and consists of transistors (TRs)T1-T6. A TRT10 and a resistor R6 in a block 3 surrounded by dotted lines 3 constitute a current source, and the same voltage Vc as the base voltage of a TRT7 of the current source of the block 1 is applied to the base of the TRT10 to form a current mirror circuit, and the current of the current source flows to a resistor R7 via TRsT11, T12, and T13. Reference voltages VL, VM and VN are applied respectively to the TRs. Then, resistors R8, R9, TRsT14 and T15 constitute a differential amplifier and the current value of the current source is applied with negative feedback to be controlled by an output voltage of the amplifier.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an ECL logic circuit that is implemented as a semiconductor integrated circuit.

Conventional Structures and Problems Semiconductor integrated circuits have recently become more highly integrated and faster, and this trend is also noticeable in semiconductor integrated circuits based on ECL logic circuits.

Since the ECL logic circuit has a smaller logic amplitude than other logic circuits such as TTL logic circuits, it is more susceptible to changes in the characteristics of circuit elements, power supply voltage, etc., which can cause malfunctions. Furthermore, when the integration is increased, the yield is further reduced.

Below is a first example of the circuit configuration of a conventional ECL logic circuit.
This will be explained with figures.

The circuit of block 1 surrounded by a dotted line in FIG.
This is an example of an L gate circuit, and a three-person NAND circuit is constructed by vertically stacking three ECL gates. Here, T1 and T2. T3 and T41 T5 and T
6 is a pair of transistors each forming an ECL gate, and input signals A, B, and C are applied to each EOL gate, and a reference voltage Vll I v
, l vL, respectively.

Further, R1 is a load resistance for obtaining the logic amplitude of the output signal 0, the transistor T7 and the resistor R2 are a constant current source that supplies the ECL gate current, and a constant voltage V is applied to the base of the transistor T7. is applied. As described above, a [NANI] circuit can be constructed by vertically stacking 5L gates, and the output signal 0 is obtained as 0=A, B, C twin child B+C by input signals 3, S, B, and C.

Next, a block 20 circuit surrounded by a dotted line is a bias circuit that generates a constant voltage to be supplied to the base of the transistor T7 constituting the constant current source in the block 1.

Here T8. T, is transistor Rs + R41R
5 is a resistor, and the collector of T8 is connected to GN through R3.
D is grounded, the emitter is connected to a constant voltage power supply Wil+ via R4, and the base is connected via R5. The collector of T9 is grounded to (1, ND), the base is connected to the connection point between the collectors of R5 and T8, the emitter is connected to the connection point between the bases of R5 and T8, and the constant voltage is applied from the connection point. Obtain Vc.

In the bias circuit as described above, the constant voltage Vc is R
It is determined by the resistance ratio of 3+R4, and when the voltage between the base and emitter of the transistor is vBg, it becomes as shown in the following equation.

Next, the logic amplitude VL of the ECL logic circuit shown in FIG. 1 is determined as follows. First, the current flow through resistor R2 is 2.
is determined by VC and R2, and I2= (Vc-Vn "Vt+
+)/R2(3), and VL becomes vL-■·R1 1 -(Vc-VBK-Vllm), -(4)2. However, the current amplification factor hFI+ of the transistor is assumed to be sufficiently large.

The logic amplitude of the ECL logic circuit is calculated above assuming that hFK is sufficiently large.Next, when hFIl decreases,
In a circuit with three stages of ECL gates stacked vertically as shown in Block 1, as a result of four transistors stacked vertically together with the transistor constituting the constant current source, the current flow through resistor R1 is , the current flow through the resistor R2 is smaller than the current 1 flowing through the resistor R2. That is, the logic amplitude vL5, -
2 degrees is also smaller by that ratio. Furthermore, as the number of vertically stacked ECL gates increases, the logic amplitude becomes even smaller. Furthermore, in a semiconductor integrated circuit, a bias circuit like the one shown in Block 2 applies a constant voltage v to several to several dozen constant current sources.
It is necessary to supply c, and when hFIl decreases, the base current increases and the voltage drop of vc becomes more severe. As the voltage of VC decreases, the logic amplitude becomes even smaller, as shown in equation (4).

However, in the conventional ECL logic circuit shown in FIG.
When the power supply voltage Vllll+ fluctuates, as shown in equation (2), vc fluctuates, and the logic amplitude also fluctuates accordingly.

Due to the reasons mentioned above, when the logic amplitude becomes smaller, the LOW level of the signal rises and approaches the reference voltage, causing the EC
The L gate will no longer be able to switch, and the circuit will no longer operate. As described above, the conventional [iL logic circuit] has a small design margin with respect to variations in circuit element characteristics and variations in power supply voltage.

6. Purpose of the Invention In view of these conventional problems, the present invention is capable of increasing the design margin with respect to characteristic fluctuations of circuit elements and power supply voltage characteristics of ECL logic circuits, and at the same time, reduces logic amplitude to achieve high speed. The object of the present invention is to provide an EOL logic circuit that can be used as an EOL logic circuit.

Structure of the Invention The present invention provides an ECL logic circuit in which the logic amplitude of the ECL gate is determined by the current value of the current source and the load resistance, and a circuit that generates a voltage proportional to the logic amplitude of the reference voltage source and the EGL gate; Fluctuations in the logic amplitude are detected by including an amplifier that amplifies the voltage difference between the voltage and the reference voltage.

By using the output voltage of this amplifier to perform negative feedback control on the current value of the current source, the logic amplitude of the E (iL logic circuit) is kept constant, and fluctuations in the characteristics of the circuit elements and fluctuations in the power supply voltage are controlled. This is to prevent circuit malfunctions caused by such factors.

DESCRIPTION OF THE EMBODIMENTS FIG. 2 shows one embodiment of an ECL logic circuit according to the present invention. For ease of explanation, the numbers of the components common to the conventional example are the same as in Figure 1, and block 1 surrounded by a dotted line
is a three-person NAND circuit constructed by vertically stacking the same ECL game l- in three stages as shown in Fig. 1, and T1 ~
T6 is a transistor. The resistor R1 is a load resistor, the transistor T7 is a current source and the resistor R2 is a current source, and the base voltage of the transistor T7 is V. It is. A, B, and C are input signals, and 0 is an output signal VH+VM+VL is a reference voltage to be compared with input signals A, B, and C, respectively.

Next, block 3 surrounded by a dotted line is an important component of the present invention, and will be explained below. Transistor T.

The resistor R6 is a current source, and the base of T,o is at the same V as the base voltage of the transistor T7 of the current source of block 1.

is supplied, forming a current mirror circuit, and the current from the current source is passed through the resistor R7 and the transistor T111.
Flows through T121 T15. Furthermore, the bases of the transistors TN I T121 TH are each connected to a 0-dimensional resistor R to which the reference voltages VL, V, , VH are applied.
A differential amplifier is configured by B HR9+ transistor T 141 TI5, and the base of TI5 is
Transistor T, 6. Reference voltage va generated by resistor R8
is applied, and the voltage Vb generated at R7 is applied to the base of T14. In the differential amplifier, the positive phase output of the erroneous input voltage vb is output from the collector of the transistor T15 and applied to the base of the transistor T17.

The transistor T17° resistor R1++ R12 is an emitter follower circuit, and the output voltage of the differential amplifier is divided by RN I R12. False resistance R1
2, the voltage at the tangent point of R12 is transferred to the transistor T18. The voltage is input to an emitter follower circuit constituted by a resistor R13, and the output voltage of the erroneous emitter follower circuit is set to vc, which is applied to each of the current sources.

The configuration of one embodiment of the present invention has been described above, and now its operation will be described.

T7. The current source of block 1 consisting of R2, Tlo,
Since the current source of block 2 consisting of T6 has a current mirror configuration, its current ratio is always constant as a resistor ratio of 9 to 2 (R6:R2), and the current flowing through resistor R7 is the current of this current source. flows through the same three transistors as the number of vertically stacked ECL gates in block 1, so it is always proportional to the current flowing through the load resistance of the ECL gate in block 1, regardless of the current amplification factor hFl of the transistor. There is. Therefore, the ratio of the logic amplitude generated in the load resistance R1 of the ECL gate and the voltage vb generated in the resistance R7 is resistance R1+ R2r R6+ 'fi
It is given by y and is always constant.

Next, the voltage vb proportional to this logic amplitude is the reference voltage Va generated using the voltage van between the base and emitter of the transistor Tl6 (7) in the differential amplifier.
A positive phase output of the input voltage vb is generated in the resistor R8, and is outputted as an emitter follower by the TD. Then, the emitter voltage of Tj7 is resistively divided by R11rRI2, and outputted as an emitter follower by Tta and R15, and this output voltage vc is supplied to the transistor TjO and the 10-base transistor T7, which constitute the current source, respectively.

Here, if the circuit constants are determined so that the voltage generated at R7 and the voltage va generated by VBi+ of the transistor TjA are equal when designing the circuit, fluctuations in the characteristics of circuit elements such as hFK of the transistor, and the power supply If the amplitude of the ECL logic circuit becomes smaller due to voltage fluctuations, the voltage vb generated across the resistor R7 increases proportionally, the output voltage of the differential amplifier also increases, and the voltage vG increases. As the voltage of vc increases, the current of the current source increases, and the resistor R7
Negative feedback control is performed so that the voltage vb generated at the voltage Vb decreases and becomes equal to the reference voltage V. When the potential of vb falls, it is also controlled by negative feedback so that it becomes equal to Va, so EC
The logic amplitude of the L logic circuit is always constant. Also, the second
In the circuit shown in the figure, by driving multiple current sources of KCL gates like block 1 in one block 3 circuit, the base current of the transistor of the constant current source of each ECL gate increases, and the voltage of vG increases. Similarly, even when ECL is lowered, the logic amplitude of ECL is kept constant.

11.+. Effects of the Invention As described above, the present invention provides negative feedback control of the current of the current source of the ECL logic circuit according to fluctuations in the logic amplitude.
It is possible to always keep the logic amplitude constant even when the circuit element characteristics change or the power supply voltage fluctuates, increasing the design margin of the circuit.Furthermore, it is possible to design with a smaller logic amplitude. This is an excellent ΣCL that has the effect of increasing the operating speed of the E (3L circuit).
It is possible to realize a logic circuit.

[Brief explanation of drawings]

FIG. 1 shows an example of the configuration of a conventional ECL logic circuit, and FIG. 2 shows a configuration of an IIL logic circuit according to the present invention. T+o+R6... Constant current source, T,, R2...
...Constant current source, Rj+R7...Bend/load resistance, T14
1T151'R8lR9...Differential amplifier, T+
6+ Rho...Reference voltage source. Name of agent: Patent attorney Toshio Nakao and 1 other person c1
'
”1--> Ta(n knowledge)

Claims (1)

[Claims] an ECL logic circuit that determines the logic amplitude of an output signal based on a current value of a current source and a load resistance, the voltage generation circuit generating a voltage proportional to the logic amplitude generated in the load resistance;
The ECL is characterized in that it has an amplifier that amplifies the voltage difference between the output of the voltage generating circuit and a predetermined reference voltage, and that the current value of the current source is controlled by negative feedback using the output voltage of the amplifier.
logic circuit.