JPH024013A - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JPH024013A
JPH024013A JP63152878A JP15287888A JPH024013A JP H024013 A JPH024013 A JP H024013A JP 63152878 A JP63152878 A JP 63152878A JP 15287888 A JP15287888 A JP 15287888A JP H024013 A JPH024013 A JP H024013A
Authority
JP
Japan
Prior art keywords
voltage
current source
constant current
transistor
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63152878A
Other languages
Japanese (ja)
Inventor
Isao Fukushi
功 福士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63152878A priority Critical patent/JPH024013A/en
Publication of JPH024013A publication Critical patent/JPH024013A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE:To always make two constant currents into the same value by comparing the current of the constant current source of a bipolar transistor for detecting and the current of the constant current source of a MOS transistor through the use of a load and a comparing circuit, and controlling the gate voltage of the MOS transistor so that both can coincide when they are different. CONSTITUTION:Potentials at a point E and a point F are compared by a voltage comparing circuit 6, and a G point potential changed according to the difference is outputted to the base of a transistor T7. According to it, a voltage at a point C is changed, and the potentials at the point E and point F are always made equal. Since current values i2 and i5 are decided by resistances R2 and R3, the ratio of the currents i2 and i5 are fixed. Since a current i7 is changed according to the i5 when a transistor Q1 is on, the current i7 has the same temperature characteristic as a current i9.

Description

【発明の詳細な説明】 〔発明の概要〕 バイポーラトランジスタとMOSトランジスタを同一チ
ップに形成した半導体装置に関し、ECL回路の定電流
源として用いられるMOSトランジスタの電流値を、バ
イポーラトランジスタによる定電流源の電流値と等しく
することを目的とし、 MOSトランジスタを定電流源に使用した第1のECL
回路と、バイポーラトランジスタを定電流源に使用した
第2のECL回路とを同−チップに形成した半導体装置
において、MOS)ランジスタを使用した第1の定電流
源およびその負荷と、バイポーラトランジスタを使用し
た第2の定電流源およびその負荷と、該第1および第2
の定電流源とその負荷との接続点の電圧を比較し、その
差に応じた電圧で前記第1の定電流源のMO3+−ラン
ジスタを制御する電圧比較回路を備え、前記第2の定電
流源のバイポーラトランジスタのベースは、前記第2の
ECL回路の定電流源のバイポーラトランジスタの−・
−スと共に定電圧源に接続して同じ電圧を加え、また前
記第1のECL回路の定電流源に使用したMOSトラン
ジスタのゲートには前記電圧比較回路の出力電圧を印加
するように溝底する。
[Detailed Description of the Invention] [Summary of the Invention] Regarding a semiconductor device in which a bipolar transistor and a MOS transistor are formed on the same chip, the current value of the MOS transistor used as a constant current source of an ECL circuit is determined by the current value of the constant current source of the bipolar transistor. The first ECL uses a MOS transistor as a constant current source, aiming to equalize the current value.
In a semiconductor device in which a circuit and a second ECL circuit using a bipolar transistor as a constant current source are formed on the same chip, a first constant current source using a MOS transistor and its load and a bipolar transistor are used. a second constant current source and its load;
a voltage comparison circuit that compares the voltage at a connection point between the constant current source and its load and controls the MO3+- transistor of the first constant current source with a voltage according to the difference; The base of the bipolar transistor of the source is connected to the base of the bipolar transistor of the constant current source of the second ECL circuit.
- the gate of the MOS transistor used as the constant current source of the first ECL circuit so as to apply the output voltage of the voltage comparator circuit. .

〔産業上の利用分野〕[Industrial application field]

本発明は、バイポーラトランジスタとMOSトランジス
タを同−千ノプに形成した半導体装置、特にそのECL
の定電流源に関する。
The present invention relates to a semiconductor device in which a bipolar transistor and a MOS transistor are formed in the same size, and in particular to an ECL thereof.
Regarding a constant current source.

バイポーラトランジスタと抵抗の直列回路はM○Sトラ
ンジスタl素子で実現できるので、バイポーラトランジ
スタを用いた高速ECL回路の定電流源にMOSトラン
ジスタを用いると築積度を向上させることができる。ま
た定電流源にMOSトランジスタを用いたECL回路は
不要時にパワーダウンさせておく制御がし易い。
Since a series circuit of a bipolar transistor and a resistor can be realized with an M○S transistor element, the degree of construction can be improved by using a MOS transistor as a constant current source of a high-speed ECL circuit using a bipolar transistor. Further, an ECL circuit using a MOS transistor as a constant current source can be easily controlled to be powered down when unnecessary.

〔従来の技術〕[Conventional technology]

バイポーラトランジスタとMOS)ランジスタを同一チ
ップ内に混載した半導体装置は一般にB1CMOS (
又はBi門OS)と呼ばれる。このB1CMOSまたは
BiMOSでは、ECL回路内の定電流源をMOSトラ
ンジスタで置き換えることができる。第3図の例ではE
CL回路9の定電流源用バイポーラトランジスタT1を
、ECL回路7′ではMOSトランジスタQ、に置き換
えている。
Semiconductor devices that combine bipolar transistors and MOS transistors on the same chip are generally B1CMOS (
or Bimon OS). In this B1CMOS or BiMOS, the constant current source in the ECL circuit can be replaced with a MOS transistor. In the example in Figure 3, E
The constant current source bipolar transistor T1 of the CL circuit 9 is replaced with a MOS transistor Q in the ECL circuit 7'.

定電流源にMOSトランジスタQ1 を用いたECL回
路7′は該トランジスタQ1 のゲート電圧をスイッチ
回路(パワーダウン回路)8′で制御することによって
電流17′の0N10FFを行ない、パワーダウン機能
を持たせることができる。
The ECL circuit 7' using a MOS transistor Q1 as a constant current source performs 0N10FF of the current 17' by controlling the gate voltage of the transistor Q1 with a switch circuit (power down circuit) 8', thereby providing a power down function. be able to.

つまり、回路8′の制御人力AがL(ロー)の時、出力
BはH(ハイ)すなわちほぼVcc(ここではGND)
となり、定電流源のMOSトランジスタQ、 はONし
て所定の電流17′を流す。これとは逆に入力AがHの
時は出力BがLすなわちほぼvhgになるので、MOS
)ランジスタQ1 はOFFして電流17′の流れない
パワーダウン状態になる。
In other words, when the control power A of the circuit 8' is L (low), the output B is H (high), that is, approximately Vcc (here, GND).
Therefore, the MOS transistor Q, which is a constant current source, is turned on and a predetermined current 17' flows. On the contrary, when input A is H, output B is L, that is, almost vhg, so the MOS
) The transistor Q1 is turned off and enters a power-down state in which no current 17' flows.

尚、1はバイポーラトランジスタT1のベースに定電圧
をしてこれを定電流源に印加する定電圧源である。
Note that 1 is a constant voltage source that applies a constant voltage to the base of the bipolar transistor T1 and applies it to a constant current source.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のB1CMOS (BiMOS )では、
ECL回路7′側の定電流源の電流17′ は、MOS
トランジスタQ】の製造バラツキ(たとえばゲート長、
ゲート酸化膜厚等)により大きくばらつき、消費電力及
び出力振幅のばらつき原因となる。
In the conventional B1CMOS (BiMOS) mentioned above,
The current 17' of the constant current source on the ECL circuit 7' side is a MOS
Transistor Q] manufacturing variations (e.g. gate length,
(gate oxide film thickness, etc.), which causes variations in power consumption and output amplitude.

また、バイポーラトランジスタT1からなる定電流源を
もち、パワーダウン機能のない基本的なECL回路9と
混在する時、ECL回路7の電流i7’ とECL回路
9の電流19は温度、電源電圧等に対して異なる依存性
を持つため、それぞれの出力振幅も別個に変動して、ノ
イズマージンが小さくなるという問題がある。
Furthermore, when a basic ECL circuit 9 having a constant current source consisting of a bipolar transistor T1 and no power-down function is used, the current i7' of the ECL circuit 7 and the current 19 of the ECL circuit 9 vary depending on temperature, power supply voltage, etc. Since the output amplitudes have different dependencies on the signals, the output amplitudes of each signal also vary independently, resulting in a problem that the noise margin becomes small.

本発明はかかる問題点を解決し、ECL回路の定電流源
として用いられるMOSトランジスタの電流値を、バイ
ポーラトランジスタによる定電流源の電流値と等しくす
ることを目的とする。
It is an object of the present invention to solve this problem and to make the current value of a MOS transistor used as a constant current source of an ECL circuit equal to the current value of a constant current source made of a bipolar transistor.

〔課題を解決するための手段〕[Means to solve the problem]

第1図は本発明の原理図で、2はECL回路9の定電流
源トランジスタと同じ電圧(定電圧源1の出力電圧B)
を加えられるバイポーラトランジスタ使用定電流源、3
は該トランジスタを流れる電流を電圧Eに変換する負荷
、5はECL回路7の定電流源トランジスタと同じ電圧
(出力電圧C)を加えられるMQSトランジスタ使用定
電流源、4は該MOSトランジスタに流れる電流を電圧
Fに変換する負荷、6は上記の電圧EとFを比較してそ
の差に応じて変る電圧Cを出力する電圧比較回路である
FIG. 1 is a diagram of the principle of the present invention, and 2 is the same voltage as the constant current source transistor of the ECL circuit 9 (output voltage B of the constant voltage source 1).
Constant current source using bipolar transistor that can add 3
5 is a load that converts the current flowing through the transistor into voltage E; 5 is a constant current source using an MQS transistor to which the same voltage (output voltage C) as the constant current source transistor of the ECL circuit 7 is applied; 4 is the current flowing through the MOS transistor. 6 is a voltage comparator circuit that compares the voltages E and F and outputs a voltage C that changes according to the difference.

ECL回路7の定電流源用MOSトランジスタには前記
電圧Cを、パワーダウン制御回路8を介して加える。
The voltage C is applied to the constant current source MOS transistor of the ECL circuit 7 via the power down control circuit 8.

〔作用〕[Effect]

従来の問題点を解決するためには、ECL回路7の定電
流源に流れる電流が、該定電流源のMOSトランジスタ
の製造バラツキによらず、また温度や電源電圧変動に対
してもECL回路9の定電流源と同じ依存性を持つ様に
制御されれば良い。
In order to solve the conventional problems, it is necessary to ensure that the current flowing through the constant current source of the ECL circuit 7 is independent of manufacturing variations in the MOS transistors of the constant current source, and is also independent of fluctuations in temperature and power supply voltage. It is sufficient if it is controlled so that it has the same dependence as a constant current source.

このため、本発明では検出用に設けたバイポーラトラン
ジスタの定電流源2の電流と、MOSトランジスタの定
電流源5の電流を負荷3.4と比較回路6を用いて比較
し、異なる場合には同じになる様−上記MOSトランジ
スタのゲート電圧を制御する。これにより2つの定電流
を常に同じ値とすることができる。
Therefore, in the present invention, the current of the constant current source 2 of the bipolar transistor provided for detection and the current of the constant current source 5 of the MOS transistor are compared using the load 3.4 and the comparison circuit 6, and if they are different, - Control the gate voltage of the MOS transistor so that it becomes the same. This allows the two constant currents to always have the same value.

(実施例〕 第2図は本発明の一実施例を示す回路図で、第1図のブ
ロック内を詳細に示したものである。定電圧源1はトラ
ンジスタT3.T4と抵抗で構成され、出力電圧Bを抵
抗R1,R2で分割した電圧がトランジスタT3のVB
Hになるような制御が行なわれ、結局一定な電圧Bを出
力する。定電流源2はトランジスタT2のベースに定電
圧源lによる定電圧Bを印加され、一定電流12を負荷
抵抗R3に流す、従って電圧EはECL回路9の定電流
19を示している。パワーダウン制御回路8は、パワー
ダウンしないときはI・ランジスクQpがオン、QNが
オフで、Qpの電圧降下は無視できるので、ECL回路
7の定電流源トランジスタQ(の制御電圧りは電圧比較
回路5の出力電圧Cに等しい。
(Embodiment) Fig. 2 is a circuit diagram showing an embodiment of the present invention, showing the inside of the block in Fig. 1 in detail.The constant voltage source 1 is composed of transistors T3 and T4 and a resistor. The voltage obtained by dividing the output voltage B by the resistors R1 and R2 is the voltage VB of the transistor T3.
Control is performed so that the voltage becomes H, and eventually a constant voltage B is output. A constant voltage source 1 applies a constant voltage B to the base of the transistor T2, and causes a constant current 12 to flow through the load resistor R3. Therefore, the voltage E indicates the constant current 19 of the ECL circuit 9. In the power-down control circuit 8, when not powering down, I-Landisk Qp is on and QN is off, and the voltage drop of Qp can be ignored. Therefore, the control voltage of the constant current source transistor Q (of the ECL circuit 7) is determined by voltage comparison. Equal to the output voltage C of circuit 5.

定電流源5はMOSトランジスタQ2からなり、ゲート
に加えられる電圧Cに応じて負荷抵抗R4に電流i5を
流す。E点の電位は一12XR3であり、F点の電位は
一15XRaである。(VccがGNDのため電位はマ
イナス)。電圧比較回路6はトランジスタT5.T6を
用いた差動アンプで、点Eと点Fの電位を比較し、差に
応じて変るG点電位をトランジスタT7のエミッタに出
力する。例えば、ELFならば点Gの電位が下がり、つ
れて点Cの電位も下がる。このときはMOSトランジス
タQ2のゲート電圧が下がるので電流i5が減少し、点
Fの電位が上がってE=Fとなる。
The constant current source 5 is composed of a MOS transistor Q2, and causes a current i5 to flow through the load resistor R4 in accordance with the voltage C applied to the gate. The potential at point E is -12XR3, and the potential at point F is -15XRa. (The potential is negative because Vcc is GND). The voltage comparator circuit 6 includes a transistor T5. A differential amplifier using T6 compares the potentials at points E and F, and outputs a potential at point G, which changes according to the difference, to the emitter of transistor T7. For example, in the case of ELF, the potential at point G decreases, and the potential at point C also decreases accordingly. At this time, the gate voltage of the MOS transistor Q2 decreases, so the current i5 decreases, and the potential at point F increases, so that E=F.

逆にE<Fなら点Cの電位が上昇してE=Fに戻される
。このように、常にE=Fとなるようフィードバック制
御される。故に 12XR3=i5XR4 であり、R3とR4は定数だから、12とi5の比が一
定に保たれる。
Conversely, if E<F, the potential at point C increases and returns to E=F. In this way, feedback control is performed so that E=F at all times. Therefore, 12XR3=i5XR4, and since R3 and R4 are constants, the ratio of 12 and i5 is kept constant.

点Cの電位はパワーダウン回路8を介してEC■7回路
7のMOSトランジスタQ1 のゲートに印加される。
The potential at point C is applied to the gate of MOS transistor Q1 of EC7 circuit 7 via power down circuit 8.

回路8は第3図の回路8′と同様のパワーダウン制御回
路であり、入力AがLの時は点Cと点りを充分低いON
抵抗でつなぎ(QpはPチャネルMOSトランジスタ)
、入力AがHの時は点りをほぼVERに下げる(QNは
NチャネルM゛OSトランジスタ)ここで、ECL回路
7のパワー(電流t7)の0N10FFを制御する。パ
ワーON (トランジスタQ1 オン)時はC=Dであ
るから、電流17はi5と同様、電流12に応じて制御
される。ia、i7の電流値はMOSトランジスタのゲ
ート長やゲート幅を設定して決められるので、同一チッ
プ上でのバラツキはほとんど同じである。従ってECL
回路7の17は製造バラツキによらず定電流源2の12
に対して一定の比をもち、ECL回路9の19と同じ温
度および電源電圧依存性を持つことができる。
Circuit 8 is a power-down control circuit similar to circuit 8' in FIG.
Connected with a resistor (Qp is a P-channel MOS transistor)
, when the input A is H, the signal level is lowered to approximately VER (QN is an N-channel MOS transistor). Here, the power (current t7) of the ECL circuit 7 is controlled to 0N10FF. Since C=D when the power is ON (transistor Q1 is ON), the current 17 is controlled according to the current 12 like i5. Since the current values of ia and i7 are determined by setting the gate length and gate width of the MOS transistor, the variations on the same chip are almost the same. Therefore, E.C.L.
17 of circuit 7 is 12 of constant current source 2 regardless of manufacturing variations.
It can have the same temperature and power supply voltage dependence as 19 of the ECL circuit 9.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に本発明によれば、B1CMOS (B
iMOS )においてMOSトランジスタを用いた定電
流源の電流値を、MOSトランジスタの製造バラツキに
よらず一定とし、また温度や電源電圧変動等に対する依
存性も、バイポーラトランジスタによるECL回路と同
じにすることができる。
As explained above, according to the present invention, B1CMOS (B
In iMOS), the current value of a constant current source using MOS transistors can be kept constant regardless of manufacturing variations in MOS transistors, and the dependence on temperature, power supply voltage fluctuations, etc. can be made the same as in ECL circuits using bipolar transistors. can.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の原理図、 第2図は本発明の一実施例を示す回路図、第3図は従来
のBiCMO5の部分回路図である。 第1図で1は定電圧源、2はバイポーラ定電流源、3は
その負荷、5はMO3定電流源、4はその負荷、6は電
圧比較回路、7.9はECL回路である。
FIG. 1 is a principle diagram of the present invention, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a partial circuit diagram of a conventional BiCMO5. In FIG. 1, 1 is a constant voltage source, 2 is a bipolar constant current source, 3 is its load, 5 is an MO3 constant current source, 4 is its load, 6 is a voltage comparison circuit, and 7.9 is an ECL circuit.

Claims (1)

【特許請求の範囲】 1、MOSトランジスタを定電流源に使用した第1のE
CL回路(7)と、バイポーラトランジスタを定電流源
に使用した第2のECL回路(9)とを同一チップに形
成した半導体装置において、前記MOSトランジスタが
オンしているとき、前記MOSトランジスタのゲートに
印加する電圧と同等の電圧が印加されるゲートを有する
MOSトランジスタを使用した第1の定電流源(5)お
よびその負荷(4)と、 バイポーラトランジスタを使用した第2の定電流源(2
)およびその負荷(3)と、 該第1および第2の定電流源とその負荷との接続点の電
圧(F、E)を比較し、その差に応じた電圧(C)で前
記第1の定電流源(5)のMOSトランジスタを制御す
る電圧比較回路(6)を備え、 前記第2の定電流源(2)のバイポーラトランジスタの
ベースは、前記第2のECL回路(9)の定電流源のバ
イポーラトランジスタのベースと共に定電圧源(1)に
接続して同じ電圧を加え、また前記第1のECL回路(
7)の定電流源に使用したMOSトランジスタのゲート
には前記電圧比較回路(6)の出力電圧(C)を印加す
るようにしてなることを特徴とする半導体装置
[Claims] 1. First E using a MOS transistor as a constant current source
In a semiconductor device in which a CL circuit (7) and a second ECL circuit (9) using a bipolar transistor as a constant current source are formed on the same chip, when the MOS transistor is turned on, the gate of the MOS transistor A first constant current source (5) using a MOS transistor and its load (4) having a gate to which a voltage equivalent to the voltage applied to the
) and its load (3), and the voltage (F, E) at the connection point between the first and second constant current sources and the load, and the first a voltage comparator circuit (6) that controls a MOS transistor of a constant current source (5), the base of the bipolar transistor of the second constant current source (2) is connected to the constant current source (9) of the second ECL circuit (9); The base of the bipolar transistor of the current source is connected to a constant voltage source (1) to apply the same voltage, and the first ECL circuit (
7) A semiconductor device characterized in that the output voltage (C) of the voltage comparator circuit (6) is applied to the gate of the MOS transistor used as the constant current source.
JP63152878A 1988-06-21 1988-06-21 Semiconductor device Pending JPH024013A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63152878A JPH024013A (en) 1988-06-21 1988-06-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63152878A JPH024013A (en) 1988-06-21 1988-06-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH024013A true JPH024013A (en) 1990-01-09

Family

ID=15550097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63152878A Pending JPH024013A (en) 1988-06-21 1988-06-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH024013A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337501B1 (en) 1999-04-08 2002-01-08 Denso Corporation Semiconductor device having bipolar transistor and MOS transistor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6337501B1 (en) 1999-04-08 2002-01-08 Denso Corporation Semiconductor device having bipolar transistor and MOS transistor

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