JPS59144945U - Day emphasis circuit - Google Patents
Day emphasis circuitInfo
- Publication number
- JPS59144945U JPS59144945U JP3867883U JP3867883U JPS59144945U JP S59144945 U JPS59144945 U JP S59144945U JP 3867883 U JP3867883 U JP 3867883U JP 3867883 U JP3867883 U JP 3867883U JP S59144945 U JPS59144945 U JP S59144945U
- Authority
- JP
- Japan
- Prior art keywords
- buffer circuit
- input
- circuit
- emphasis circuit
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のディエンファシス回路とその周辺の回路
の回路図、第２図は本考案のディエンファシス回路の原
理的回路図、第３図は具体的回路図である。FIG. 1 is a circuit diagram of a conventional de-emphasis circuit and its peripheral circuits, FIG. 2 is a principle circuit diagram of the de-emphasis circuit of the present invention, and FIG. 3 is a specific circuit diagram.
Claims (4)
るための第１のバッファ回路の出力側と、選択モードに
関係なく一定の出力インピーダンスを持った第２のバッ
ファ回路の出力側との間に、１個の抵抗を接続すると共
に、該抵抗の上記第２バッファ回路の共通接続点と接地
間に１個のコンデンサを接続し、該共通接続点から出力
を取り出すようにしたことを特徴とするディエンファシ
ス回路。(1) One between the output side of the first buffer circuit for switching the output impedance for each selection mode and the output side of the second buffer circuit, which has a constant output impedance regardless of the selection mode. A de-emphasis circuit characterized in that a resistor is connected to the resistor, and a capacitor is connected between the common connection point of the second buffer circuit of the resistor and ground, and the output is taken out from the common connection point. .
ワで成ることを特徴とする実用新案登録請求の範囲第１
項記載のディエンファシス回路。(2) Utility model registration claim 1, characterized in that the first buffer circuit is comprised of an emitter follower.
De-emphasis circuit described in section.
源電圧、上記第２のバッファ回路の電源室′ 圧が択一
的に印加するようにしたことを特徴とする実用新案登録
請求の範囲第１項記載のディエンファシス回路。(3) Claims for registration of a utility model characterized in that the power supply voltage of the first buffer circuit and the power supply chamber pressure of the second buffer circuit are selectively applied depending on the selection mode. The de-emphasis circuit described in item 1.
信号が入力し、上記第２のバッファ回路の入力側にＴＶ
復調音声信号が入力するようにしたことを特徴とする実
用新案登録請求の範囲第１項記載のディエンファシス回
路。(4) An FM demodulated audio signal is input to the input side of the first buffer circuit, and a TV signal is input to the input side of the second buffer circuit.
The de-emphasis circuit according to claim 1, wherein a demodulated audio signal is input.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3867883U JPS59144945U (en) | 1983-03-17 | 1983-03-17 | Day emphasis circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3867883U JPS59144945U (en) | 1983-03-17 | 1983-03-17 | Day emphasis circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59144945U true JPS59144945U (en) | 1984-09-27 |
Family
ID=30169346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3867883U Pending JPS59144945U (en) | 1983-03-17 | 1983-03-17 | Day emphasis circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59144945U (en) |
-
1983
- 1983-03-17 JP JP3867883U patent/JPS59144945U/en active Pending
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