JPS59143482A - Clock generating circuit for encoding picture signal - Google Patents

Abstract

PURPOSE:To encode an optional picture signal in a wide range and to obtain a VTR signal from a commercial TV signal only by one encoding device by automatically switching to generate a synchronous sampling clock and an asynchronous sampling clock in accordance with an input picture signal. CONSTITUTION:A horizontal synchronism signal in a picture signal from a picture signal input terminal 1 is separated by a synchronism separating circuit 2 and the separated synchronism signal is applied to a phase synchonism oscillation circuit 3 and an asynchronism detecting circuit 4. The oscillation circuit 3 generates a clock synchronized with the output of the circuit 2 at its phase and supplies the clock to the detecting circuit 4 and a frequency dividing circuit 6. A transmission clock from an external clock input terminal 5 is applied to a frequency dividing circuit 7 and the detecting circuit 4. The detecting circuit 6 checks whether the frequency of the output signal from the oscillation circuit 3 is included within a prescribed period or not and applies as a switching control signal to a switching circuit 8. The switching circuit 8 switches the frequency dividing circuits 6, 7 to encode an optional picture signal in a wide range.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock generation circuit that switches between a synchronous sampling clock and an asynchronous sampling clock in accordance with an input image signal in encoding an image signal.

Traditionally, leased lines have been the king of video communication networks, but in recent years, as services have become more concrete, public networks have begun to be considered. In order to construct an economical system in a public network, it is necessary to use intra-frame coding with low equipment cost for short- and medium-distance sections, and use inter-frame coding, which can reduce transmission path costs, for long-distance sections. It is a good idea to use the method.

In this case, it becomes a digital three-link of intra-frame/inter-frame/intra-frame coding, and considering the additive reduction of noise, it is desirable to cascade 1M digital signals without converting them back to analog signals.

In the interframe coding method, in order to improve coding efficiency, it is necessary to sample at the same position for each frame, that is, to perform synchronous sampling. Therefore, the intraframe encoding method digitally cascaded with this must also be highly synchronous sampling.

On the other hand, video signal sources to be encoded, such as broadcast signals, have a synchronous frequency fluctuation of ±30 pp.
m or less, ±11000p like VTR output
For the former, synchronous sampling is possible. However, in the latter case, synchronous sampling is impossible because it is difficult to generate a sampling clock synchronized with the synchronous frequency.

Although long-distance transmission using inter-frame coding is not possible for the output of VTRs, which have become rapidly popular in recent years, it is necessary to provide short- and medium-distance transmission services using intra-frame coding using asynchronous sampling. .

In this way, future intraframe coding systems will require both synchronous sampling and asynchronous sampling functions.

However, since the studies were conventionally focused on leased lines, the coding device for synchronous sampling and the coding device for asynchronous sampling were configured as completely different devices, and therefore the RI generation circuit was also used. They were configured as separate devices depending on the encoding device being used.

As described above, in order to realize an encoding device having both synchronous/asynchronous sampling functions, it is necessary to realize a clock generation circuit that automatically switches and generates a synchronous/asynchronous sampling clock.

As a lock generating circuit like this, for example,
There is No. 7-009837. FIG. 1 is a block diagram of the same, in which l is an image signal input terminal, 2 is a sync separator circuit that separates and outputs a horizontal sync signal from the input signal, and 3 receives the output of the sync separator circuit 2 and outputs it. A phase synchronized oscillation circuit 40 that generates phase synchronized clocks checks whether the frequency fluctuation of the output of the phase synchronized oscillation circuit 3 is within a predetermined range, and if it is out of this range, outputs an out-of-synchronization signal. Out-of-synchronization detection port 41 is a clock switching signal generation circuit that generates a signal to control the switching circuit 80 based on the output of the out-of-synchronization detection circuit 40 and a signal input from the signal source switching timing signal input terminal 42; Reference numeral 80 indicates a switch for switching between the output of the phase synchronized oscillation circuit 3, that is, a clock that is phase-synchronized with the human input image signal, and the signal that is input from the external clock input terminal 5, that is, a clock that is asynchronous with the input image signal, and outputting it to the clock output terminal 9. It is a circuit.

Here, the signal input through the signal source switching timing signal input terminal 42 is, for example, a call connection signal supplied from an exchange. That is, a pulse is provided each time a call is connected. The clock switching signal generation circuit 41 is composed of, for example, a reset flip-flop, and resets the slip-flop every time a pulse is input from the signal source switching timing signal input terminal 42, and sets the output to II□11 to the switching circuit 80. and connects the output of the phase synchronized oscillation circuit 3. That is, the initial state when a call is connected always starts with the connection of the synchronous clock. Thereafter, according to the frequency fluctuation of the human image signal, if the frequency fluctuation is larger than a predetermined value, the clock switching signal generation circuit 41
The flip-flop is set, and the switching circuit 80 connects the signal from the external clock input terminal 5, that is, the asynchronous clock. If the frequency fluctuation is small, one synchronous node continues to be connected for one year.

As described above, the switching circuit 8 switches to the output side of the phase synchronized oscillation circuit 3 only at the first time a call occurs. For this reason, once the VTR output with large frequency fluctuations is input and the clock is switched to the asynchronous clock side, even if the user switches to the camera output with small frequency fluctuations in the same call, the clock will be synchronized from the asynchronous clock. There was a drawback that the clock could not be switched.

In encoding an image signal, the present invention uses a synchronous sampling clock for an image signal whose synchronous frequency accuracy is within a predetermined standard, and an asynchronous sampling clock for an image signal whose synchronous frequency accuracy is completely outside the standard. By switching automatically and reliably,
The object of the present invention is to provide a link generation circuit for an image signal encoding device capable of encoding a wide range of image signals from commercial television (M number) to simple VTR signals.

In order to achieve the above objects, the present invention provides a synchronous separation circuit that separates a synchronous signal from an input image signal, and a phase synchronous oscillation circuit that generates a clock that is phase-synchronized with synchronous signal No. 8 supplied from the synchronous separation circuit. , an out-of-sync detection circuit that receives the clock supplied from the phase-locked oscillation circuit and detects that the frequency accuracy of the input image signal deviates from the standard, and synchronizes the synchronous sampling clock and the asynchronous sampling clock with each other. In an image encoding clonk generation circuit including a switching circuit that switches and outputs based on the output of a deviation detection circuit,
The out-of-synchronization detection circuit (1) prohibits frequent clock switching when the synchronization frequency of the input image signal is near a predetermined threshold; Prohibits clock switching in the event of a momentary power outage, ■Detects a change from an unattended state to a state in which an image signal with high frequency accuracy is input, and switches from an asynchronous sampling clock to a synchronous sampling clock. is configured to switch to a standard clock. This will be explained in detail below with reference to the drawings.

FIG. 2 shows an embodiment of the present invention, in which 1 is an image signal input terminal, 2 is a synchronization separation circuit, 3 is a Korean phase synchronization boosting circuit, 4 is an out-of-synchronization detection circuit, 5 is an external clock input terminal, 6, 7 8 is a frequency dividing circuit, 8 is a switching circuit, and 9 is a clock output terminal.

To operate this, the image signal input from the image signal input terminal 71 is supplied to the synchronization separation circuit 2, where the horizontal synchronization signal is separated, and the separated horizontal synchronization signal is sent to the phase synchronization oscillation circuit 3 and the synchronization separation circuit 2. Supplied to disconnection detection circuit 4.

The phase synchronized oscillation circuit 3 receives the output of the synchronized separation circuit 2, and
A clock phase-synchronized with this is generated and supplied to the out-of-synchronization detection circuit 4 and the frequency dividing circuit 6.

The out-of-synchronization detection circuit 4 checks whether the frequency of the output signal of the phase-locked oscillation circuit 3 is within a predetermined range, and sends a switching control signal to the switching circuit 8.

A frequency divider circuit 6 divides the output of the phase synchronized oscillation circuit 3 to generate a synchronized sampling clock.

The frequency dividing circuit 7 generates an asynchronous sampling clock by frequency-dividing a signal input from the external clock input terminal 5, for example, a transmission line clock in an image encoding apparatus to which the present invention is applied.

The switching circuit 8 switches the outputs of the two frequency dividing circuits 6 and 7 based on the switching control signal supplied from the out-of-sync detection circuit 4, and sends this signal to the output terminal 9. The filter signal is used as a sampling clock necessary for image encoding or as a lock necessary for other image processing.

FIG. 3 is a detailed diagram of the out-of-synchronization detection circuit 4, and FIG. 4 is a time chart for explaining its operation. 101 is a frequency fluctuation measuring circuit, 102 is an inverter, 103
．． 106.109. 110. 113 is a counter,
104°107 is AND circuit, 105.108 is NOR
circuit, 111 is a threshold circuit, 112 is a latch circuit, 114
．． 116 is a flip-flop, and 115 is a power-on signal input terminal.

The frequency fluctuation measurement circuit 101 measures the frequency of the signal supplied from the phase synchronized oscillation circuit 3, and this is determined to be a specified frequency f.
For example, when it is within ±60 ppm, an output of n1ll is generated, and otherwise, an output of IIOn is generated, and this is sent to the inverter 102, counter 103, and AND circuit 10.
The counter 103 outputs 0 to 4 when the frequency of the input image signal is the threshold -1-
When the frequency fluctuation measurement circuit 101 is around 60 ppm, this circuit sets a switching prohibition period of N seconds, for example, 60 seconds, to prevent frequent synchronous/asynchronous switching. , i.e., from the point in time when the value changes from other than ±60' ppm within - G I G outputs a signal (b) which becomes 1101 after an arbitrary short time) seconds.

Both outputs are supplied to an ANI) circuit 104, which outputs a signal equal to 11 for G seconds to an OR circuit 105. As is clear from FIG. 4(A), the output of the frequency fluctuation measuring circuit 101 becomes 110n again within N seconds, that is, ±6.
A if there is a fluctuation of 0 ppm or more
It does not appear as the output of the ND circuit 104.

The counter 103 is cleared after outputting the value N+G seconds later.

Next, even if the input image signal has high frequency accuracy, such as a broadcast television signal, the instantaneous synchronization signal may disappear if, for example, the camera is switched. However, after that, a highly accurate synchronization signal is input again. The counter 104 is used to provide a gate period of M seconds to prevent switching from synchronous to asynchronous and then back to synchronous due to such a momentary interruption. The counter 106 outputs the output of the inverter 102 from 1IO1' to 111nK1, that is, the synchronization frequency of the input image is ±5o.
Starting from the time when the change is from within PPm to outside, the constant clock input from the external clock input terminal 5 is counted, and after M seconds, for example, after 2 seconds, the signal (c) becomes n111, and after M+G seconds, it becomes 1011. Outputs the A word (d). Both outputs are supplied to an AND circuit 107, where the signal becomes l+1'11 for G seconds and is output to a NOR circuit 108. As is clear from FIG. 4(B), if the output of the inverter 102 is within the M sand trap again with a frequency accuracy of n0rl, that is, within ±60 ppm, it does not appear as the output of the AND circuit 107. . The counter 106 is cleared after outputting the value after M+G seconds, thereby preventing frequent switching between synchronous and asynchronous states. However, if an input signal with high frequency accuracy is connected from the state of J-to synchronization due to unmanned power, it is better to switch to synchronization as soon as possible than to maintain valve opening synchronization for as long as N seconds (for example, 60 seconds). Synchronous encoding should be started. Counter 109 is used for this purpose. FIG. 4(C) is a time chart for explaining this control method.

The counter 109 periodically counts the Hals number of the horizontal synchronization signal supplied from the synchronization separation circuit 2 every L seconds, for example, every 4 seconds, and outputs the value. A clock for cents every L seconds is supplied from the counter 110. counter 110
generates a pulse every L seconds by counting a constant cycle clock supplied via the external a-clock input terminal 5.

The threshold circuit 111 outputs n1n when the output of the counter 109 is greater than the threshold TH, and outputs nOII otherwise. The launch circuit 112 receives the output of the threshold circuit 111,
The output of the counter 110 is latched as a clock and supplied to the counter 113.

The counter 113 starts from the time when the output of the latch circuit 112 changes from nO'' to rll'', counts the clocks input from the external clock input terminal 5,
It outputs a signal that becomes lIO" after G seconds and becomes u and II at other times. The slip-flop 114 receives the output of the latch circuit 112 and sets it, receives the output of the counter 113 and resets it, and outputs a signal that becomes II I n for G seconds. A signal is output and supplied to the NOR circuit 105.Thereby, when an image signal is input, it is possible to switch to synchronization within L seconds.

The NOR circuit 105 receives the outputs of the AND circuit 104 and the slip-flop l14, and selects one of the plane inputs as II'.
111, it outputs llO''.The NOR circuit 108 is
In response to the signals supplied from the AND circuit 107 and the power-on signal input terminal 11'5, any one of the plane inputs becomes 111.
1111 is supplied to the power-on signal input terminal 1115 only when the power is turned on, and the flip 70 knob 116 is set when the output of the NOR circuit 105 is O11, and the output of the NOR circuit 108 is set. Reset when is 1011.

The output of the slip-flop 116 is the output of the out-of-synchronization detection circuit 4, which controls the switching circuit 8.
The time frequency division circuit 6 of IH is connected, and the time frequency division circuit 7 of 1011 is connected. These operations are started from an asynchronous state by supplying a pulse from the power-on signal input terminal 115 K "l" when the power is turned on, and are thereafter controlled according to the synchronization frequency accuracy of the input signal.

In the above explanation, the case of phase synchronization with the horizontal synchronization signal has been described, but also in the case of phase synchronization with the color burst, the synchronization separation circuit 2 detects the color burst and outputs the counter signal of the Sano carrier, and the phase synchronization oscillation circuit 3 and the out-of-synchronization detection circuit 4 can be similarly configured by simply changing the subcarrier frequency to operate at the subcarrier frequency instead of the horizontal synchronization frequency.

As explained above, in the present invention, the synchronous sampling counter, the asynchronous sampling counter, and the clock are automatically switched and generated according to the input image signal. The device has the advantage of being able to encode a wide range of arbitrary image signals from commercial television signals through simple VTR signal switching.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a conventional clock generation circuit. FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a detailed diagram of the out-of-sync detection circuit in FIG. 2. FIG. 4 is a time chart for explaining the operation of the out-of-synchronization detection circuit 4, in which (A) shows a switching operation from asynchronous to synchronous, (B) shows a switching operation from synchronous to asynchronous, and (C) shows a switching operation from synchronous to asynchronous.
) respectively indicate the switching operation to synchronization when an image input is connected. l... Image signal input terminal, 2...
... Synchronization separation circuit, 3 ..... Phase synchronization oscillation circuit, 4 ..... Out-of-synchronization detection circuit,
5...External milling input terminal, 6,7 ・
...... Frequency dividing circuit, 8... Switching circuit,
9......Clock output terminal, 101-...
-... Frequency fluctuation measurement circuit, 102... Inverter, 103, 106109.110.113.
...Counter, 104.107 PAND circuit 1105, tc+, s...NOR' circuit, 111...Threshold circuit, 112...
・-Latch circuit, 114.1115...Flipf. Tub, 115......Power-on signal input terminal. Figure 4 + AI AND Four Chickens 104 power □1−−−−−−−−“−[
-1----------NORIEla+055
1 & power +81 NORia+os Qt power NOR old audience/105 turtleka

Claims (1)

[Scope of Claims] A synchronization separation circuit that separates a synchronization signal from an input image signal, a phase synchronization oscillation circuit that generates a clock that is phase-synchronized with the synchronization signal supplied from the synchronization separation circuit, and a clock that is supplied from the phase synchronization oscillation circuit. an out-of-sync detection circuit that detects that the frequency accuracy of the input image signal deviates from the standard upon receiving a clock; and a first clock that is the output of the phase synchronized oscillation circuit or its frequency-divided output, and a first clock that is supplied from the outside. a switching circuit that switches and outputs a second signal, which is a frequency-divided output thereof, based on the output of the out-of-synchronization detection circuit; is near a predetermined threshold, the input signal is momentarily interrupted while an image signal with high frequency accuracy is being connected to a circuit that prohibits frequent switching of the first and second clocks. In this case, for this purpose, a circuit for prohibiting switching from the first clock to the second clock, and a circuit for detecting a change from an unmanned state to a state in which an image signal with high frequency accuracy is input. , and a circuit for switching from the second clock to the first clock.