JPH04252584A - Moving picture decoding integrated circuit - Google Patents

Abstract

PURPOSE:To attain moving picture decoding processing corresponding to diversified frame rates as required without increasing the device scale. CONSTITUTION:A synchronizing signal generating circuit 11 generating an internal frame synchronizing signal corresponding to a prescribed frame rate, a selection circuit 12 selecting and outputting a desired signal in an external frame synchronizing signal applied externally and the above internal frame synchronizing signal and a moving picture decoding circuit 13 implementing frame synchronization control according to an output signal of the above selection circuit 12 and decoding processing of the coded moving picture data fed externally are realized by one integrated circuit 1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a moving picture decoding integrated circuit constituting a moving picture decoding apparatus used for video telephones and video conferences.

0002

[Background Art] In a video decoding device, the transfer rate of encoded data that is input from a transmission path (communication system) to the decoding device and the rate at which encoded data is output from the video decoding device to a display (image display system) are determined. The image data transfer rate is different. Therefore, it is necessary to perform image decoding processing in synchronization with the display frame timing of the display. When a moving image decoding device is configured using an LSI (Large Scale Integrated Circuit), a synchronization signal generation circuit is provided outside the LSI, and the synchronization signal generated by this synchronization signal generation circuit is transmitted to the LSI.
A method has been adopted in which frame synchronization control is performed by inputting to the SI. This method has the advantage that the video decoding device can be operated at various frame rates by controlling the frame synchronization signal input from the synchronization signal generation circuit to the LSI.

0003

[Problems to be Solved by the Invention] However, when the above-mentioned conventional method is used, an extra circuit for synchronization control is required outside the LSI that realizes the moving image decoding device, and the system configuration becomes large. There is.

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a moving image decoding integrated circuit that can reduce the number of parts and realize a small-scale moving image decoding device. shall be.

[0005]

[Means for Solving the Problems] The present invention provides a synchronization signal generation circuit that generates an internal frame synchronization signal corresponding to a predetermined frame rate, and a synchronization signal generation circuit that generates an internal frame synchronization signal that corresponds to a predetermined frame rate. It includes a selection circuit that selects and outputs any desired one, and a video decoding circuit that performs frame synchronization control according to the output signal of the selection circuit and decodes encoded video data supplied from the outside. It is characterized by

[0006]

[Operation] According to the above structure, when decoding encoded moving image data of a predetermined frame rate, the internal frame synchronization signal output from the built-in synchronization signal generation circuit is selected by the selection circuit, and the moving image decoding circuit Decoding processing is performed by frame synchronization control using an internal frame synchronization signal. In addition, when decoding encoded video data at a frame rate other than the predetermined frame rate, an external frame synchronization signal is selected by the selection circuit, and the video decoding circuit performs decoding by frame synchronization control using the external frame synchronization signal. Processing takes place.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a moving image decoding L according to an embodiment of the present invention.
FIG. 2 is a block diagram showing the configuration of SI1. Inside this LSI 1, there is a frame synchronization signal (hereinafter referred to as an internal frame synchronization signal) corresponding to frequently used frame rates.
A counter circuit 11 is provided for generating . Also,
The LSI 1 is provided with an input terminal 21 for receiving a frame synchronization signal from the outside (hereinafter referred to as an external frame synchronization signal). The internal frame synchronization signal and the external frame synchronization signal are transmitted to the selector circuit 12 based on the external synchronization/internal synchronization selection signal input to the selection input terminal 22.
and is input to the video decoding circuit 13 which decodes encoded video data from the outside. When operating a video decoding device at a frequently used frame rate, it is possible to perform internal frame synchronization control using an internal frame synchronization signal, and in this case, a new synchronization control circuit is installed outside of LSI 1. There is no need to add one, and the overall configuration of the device can be made smaller. When it becomes necessary to operate the moving image decoding device at a rate different from the frame rate of the internal frame synchronization signal, input terminal 2 is input from the outside.
The external frame synchronization signal is inputted to the external frame synchronization signal 2, and the signal value of the external synchronization/internal synchronization selection signal is set so that the external frame synchronization signal is selected by the selector circuit 12. This allows frame synchronization control to be performed at the required rate. In this way, since the counter circuit 11 that generates the internal frame synchronization signal and the selector circuit 12 that selects the frame synchronization signal are built into the LSI 1, it is possible to efficiently configure the moving image decoding device, and also to It becomes possible to configure a device that can flexibly respond to frame rates of

As an example, a case will be explained in which the frame frequency of the internal frame synchronization signal in LSI 1 is designed to be 30 Hz, and the frame rate of encoded image data input to LSI 1 is 15 Hz. In this case, since the frame rate for internal synchronization control of the video decoding device is higher than the frame frequency of the received image, it is possible to perform the decoding process even using internal frame synchronization control. When internal frame synchronization control is performed in this manner, an external synchronization generation circuit is not required, so that the scale of the apparatus can be reduced. Figures 2 and 3 show the operation of LSI 1 when internal frame synchronization is performed under the above conditions.
Shown below. The rate of decoded and displayed images is shown in Figures 2 and 3.
As shown in the figure, the average frequency is 15Hz, but since the frame rate of the decoding device and the frame rate of the input decoded image are not synchronized, the display time of each frame is
Variations occur. For this reason, unnaturalness tends to occur in the movement of the displayed image in the time direction.

Next, when the frame rate of encoded video data is 15 Hz, an example of the operation of LSI 1 when a 15 Hz external frame synchronization signal is input and used as a frame synchronization signal to perform external frame synchronization control. are shown in FIGS. 4 and 5. As shown in these figures, since the frame synchronization signal in this case is synchronized with the frame rate of encoded data, the rate of the displayed image is 15 Hz, and unnatural movement in the time direction is unlikely to occur. In this case, the circuit scale of the device increases, but the quality of the temporal movement of the image improves.

[0010] As described above, when constructing a moving picture decoding device using the present invention, it is possible to use internal synchronization control and external synchronization control depending on the purpose. When placing importance on the configuration scale of the device, internal frame synchronization control is adopted at the expense of movement in the time direction. At this time, by setting the internally generated frame synchronization signal to the maximum frame rate of encoded image data, it is possible to support all frame rates. On the other hand, when placing emphasis on the quality of displayed images, external frame synchronization control is adopted at the expense of device scale.

[0011]

As explained above, the moving picture decoding integrated circuit according to the present invention includes a synchronization signal generation circuit that generates an internal frame synchronization signal corresponding to a predetermined frame rate;
a selection circuit that selects and outputs a desired one of the external frame synchronization signal and the internal frame synchronization signal supplied from the outside; and a selection circuit that performs frame synchronization control according to the output signal of the selection circuit and supplies the external frame synchronization signal. Since it has a video decoding circuit that performs decoding processing of encoded video data, it is possible to configure a video decoding device without increasing the scale of the device, and it also supports various frame rates as necessary. This has the advantage that flexible decoding processing can be performed.

[Brief explanation of the drawing]

[Fig. 1] Video decoding LS according to an embodiment of the present invention
FIG. 2 is a block diagram showing the configuration of I.

FIG. 2 is a time chart illustrating the operation of the same embodiment.

FIG. 3 is a time chart illustrating the operation of the same embodiment.

FIG. 4 is a time chart illustrating the operation of the same embodiment.

FIG. 5 is a time chart illustrating the operation of the same embodiment.

[Explanation of symbols]

1 Video decoding LSI 11 Internal counter circuit 12 Selector circuit 13 Video decoding circuit

Claims (1)

[Claims] 1. A synchronization signal generation circuit that generates an internal frame synchronization signal corresponding to a predetermined frame rate, a desired one of an external frame synchronization signal supplied from the outside, and the internal frame synchronization signal. and a video decoding circuit that performs frame synchronization control according to an output signal of the selection circuit and decodes encoded video data supplied from the outside. Decoding integrated circuit.