JPS59141885A - Reproducing circuit of sampling clock - Google Patents

Abstract

PURPOSE:To reproduce data with a small number of errors by detecting the output of a phase shift circuit having a phase shift equivalent to the phase difference between a signal of double frequency (5.73MHz) as much as the repeating frequency of a clock run-in signal and an oscillation output of 5.73MHz. CONSTITUTION:The pulse of a gate pulse generating circuit 15 is supplied to a gate circuit 16. Then a clock run-in signal is sampled and doubled by a doubling circuit 18 via a band pass filter (BPF)17 of 2.86MHz to be transmitted through a BPF19 of 5.73MHz. Thus an oscillation signal of 5.73MHz is obtained. The phase difference between the ouput signal of the BPF19 and the output of a crystal oscillating circuit 20 of 5.73MHz is detected by phase comparators 21 and 22. Then the phase of the oscillation output signal is shifted by an amount equivalent to said phase difference through a phase shift circuit 23. Thus it is possible to reproduce a sampling clock having the phase synchronism with the clock run-in signal of an input character data signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is a teletext receiver that uses information (including text and image data, hereinafter referred to as character data) superimposed on a predetermined horizontal scanning period of a television signal. ) This relates to a sampling clock regeneration circuit that regenerates a data sampling clock for reading signals.

Conventional structure and its problems As an example of teletext broadcasting, a teletext system has already been broadcast in the UK, and in Japan, in March 1980, a teletext broadcasting system using a pattern transmission method was approved by the Radio Technology Council. The answer was answered. The character data signals of these systems are all binary NRZ signals, and are superimposed on arbitrary 1 to 2 H within the vertical blanking period of the video signal in the form of data packets with one horizontal scanning period (1H) as a unit. be done.

FIG. 1 shows a waveform diagram of an example of a superimposed character data signal. In FIG. 1, the character data signal consists of a header part and an information data part, and the header part includes a clock run-in signal and a framing code signal. The framing code signal is the signal used to synchronize the data packets.In the teletext system, the text signal has the signal form shown in Figure 1. This signal is sent to the receiving side and reproduced by the receiving side, but in order to do this, the receiving side must accurately reproduce the sampling clock used to sample each subsequent signal based on the clock run-in signal. The frequency of the sampling clock differs depending on the system in each country, but it is generally twice the fundamental frequency of the clock run-in signal, and in Japan it is 5.73 MB2 (=364fH=815
fs, + fH are the frequencies of the horizontal synchronizing pulse, and 'SC is the frequency of the color subcarrier). The Japanese system will be described below.

To reproduce the sampling clock, set the frequency to 5.73 above.
It is necessary to match the phase with the clock run-in signal in order to match the MHz and at the same time reproduce the data correctly. Further, jitter in the sampling signal b7 when the S/N of the received signal deteriorates does not cause a large error in the reproduction of the received data, so the jitter must be small even if the S/N deteriorates.

The following is a conventional sampling clock regeneration circuit that is intended to solve these problems. That is, the vicinity of the character data clock run-in signal f2.
T&, 5.73 MHz extracted by 9.2 through an 86-MHz bandpass filter and gate circuit
passes through a bandpass filter, and the output is 5.73M.
The ringing oscillator of H2 is driven to generate a preliminary sampling clock.

This preliminary sampling clock is used to detect a framing code for frame synchronization.On the other hand, the main sampling clock is used to detect a signal having a frequency of n times 5.73 MHz (for example, 5 times 28.6 MHz) using a counter. /n, sample the data using a preliminary sampling clock, and reset this counter using a normalizing code obtained by error correction.However, a proper sampling clock with phase synchronization can be obtained. In this case, a preliminary sampling clock is used for sampling the framing code, and for subsequent data sampling, the oscillator output of 5.73MHz x n is divided into 17n, and the frequency divider is used to detect the framing code. The 01 has the complexity of switching to the one reset by the signal.When oscillating at 5 times the frequency of 6.73MHz, the high frequency of 28.6MHz is divided, so the harmonics generated at that time are transmitted to the antenna and the system as interference signals. This can significantly degrade the error rate when receiving certain stations. For example, the video carrier frequency of Japan's 9th channel is 199.25 MB2, while the 7x harmonic of 2s and 6M is 200.2 MHz, creating a beat signal of about IMHz and reducing the error rate. make a big impact.

Unfortunately, even if the sampling clock is phase-synchronized with the clock run-in signal, it is necessary to adjust the phase according to the difference between the sampling clock, the reproducing circuit configuration, and the data slice system circuit configuration. The sampling clock is passed through a phase shift circuit to match its phase, but because the frequency is high, the character data signal has only one signal per field.
Due to the intermittent signal of ~2H minutes, there is also the drawback that it is difficult to adjust the phase.

OBJECT OF THE INVENTION The present invention eliminates the above-mentioned drawbacks of the conventional technology.It is an object of the present invention to provide data reproduction with a simple configuration and with less jitter, that is, fewer errors even if the S'/N of the received signal is poor. In addition, by eliminating digital processing such as frequency division and regenerating the sampling clock using analog processing at the signal transmission rate even at the highest frequency, interference to the antenna is reduced and it is possible to easily combine slice data with It is an object of the present invention to provide a sampling clock regeneration circuit that also facilitates phase matching.

Structure of the Invention In the present invention, the vicinity of the clock run-in signal of character data is set at a repetition frequency (for example, 2, 86 MHz).
z) to') is extracted through a first band-pass filter and a gate circuit, multiplied by 2, and then passed through a second band-pass filter at the frequency of the data transmission rate (for example, 5.73 MHJ.On the other hand, apart from this, Oo, 9
An oscillation circuit with a frequency of a data transmission rate having 04 phase outputs such as 00.18'Oo and 270o, and a phase difference between two mutually orthogonal output signals of this oscillation circuit and the output of the second bandpass filter. two mutually orthogonal phase difference detection circuits that detect By configuring and matching the phase of the output of the phase shift circuit to a signal obtained by doubling the clock run-in signal (the output signal of the second band-pass filter), a sampling clock that is phase-synchronized with the clock run-in signal is generated. It happens.

With this configuration, even if the S/N of the received signal deteriorates, jitter due to noise in the reproduced sampling clock can be suppressed by removing noise components using the first and second filters. In addition, since all circuits are analog processed and the maximum frequency handled is the data transmission rate frequency (5.73 MHz), there is little interference with received signals.

Description of examples Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 2 is an overall configuration diagram of the teletext receiver.

1 is a reception antenna, 2 is a video reception section, 3 is a brightness amplification and color demodulation section, 4 is a character data decoder section, 5 is a keyboard for specifying the program to be received, and 6 is a demodulated TV image that is received. The video switching section that switches between character images and the cathode ray tube (which displays the switched video)
'CRT).

In the decoder section 4, 8 is a data slicing circuit that slices the character signal superimposed on the video signal and reproduces data, 9 is a sampling clock reproduction circuit that reproduces a sampling clock for reading data, and 10n synchronization separation circuit ( 11 is an FC detection circuit that detects the framing code, which reads the sliced data after FC detection, stores the obtained information in memory, and displays it on the CRT. This is a character signal processing circuit that outputs a possible signal.

FIG. 3 is a more detailed configuration diagram of the sampling clock recovery circuit 90 according to the embodiment of the present invention. The same blocks as in FIG. 2 are given the same numbers.

13 is an input terminal for a video signal on which a character data signal is superimposed, 14 is an input terminal for a horizontal synchronizing pulse, and 8 is an output terminal for a reproduced sampling clock. 15 is a gate pulse generation circuit that extracts the clock run-in signal part of the character data signal, and this gate pulse can be generated by mono-multi-by-break etc. based on the horizontal synchronization pulse inputted from the input terminal 14. The clock run-in signal portion of the signal supplied to the circuit 16 and input through the circuit 13 is extracted. Clocks pulled out.

The crank-in signal is passed through a 2.86 MHz band-pass filter 17 to remove high frequency components and noise components of the repetition frequency of the cyclic run-in signal.

Its output is converted into a 2,86MH2O sine wave signal that continues to oscillate even after the Q clock run-in signal period due to the resonance characteristics of the bandpass filter 17.

This signal is doubled by the doubling circuit 18, and the frequency is 5; 73MHz.
Bandpass band pass filter 19, this time the frequency is twice the repeating frequency of the clock run-in signal 5
, 73 MH2 vibration signals are obtained. Here, the doubler circuit 18 can be realized by a multiplication circuit that multiplies each other by the same human input signal. Since it is difficult to sustain the oscillation over the horizontal period of the output 141 of the O-band pass filter 19, this sampling clock is generated. The circuit has a separate 5.73 MHz crystal oscillation circuit 20, and the phase difference between this oscillation output and the output signal of the bandpass filter 19 is detected by phase comparator circuits 21 and 22, and the total shift of the oscillation output signal is determined by the phase difference. The phase is shifted by the phase circuit 23, and the phase is synchronized with the clock run-in signal of the input character data signal, and by using a crystal oscillator, a sampling clock having a stable frequency for one horizontal period is regenerated.

20 is the 5.73MHz oscillation circuit at 0°, iao'
.

Outputting four orthogonal phases such as 90° and 2700,
It is represented by c and d. 21 and 22 are phase comparators that compare the phases of the oscillation output of Oo and the input signal, and the oscillation output of 900 and the input signal, respectively. In FIG. Each of these is a.

k;, c, and d'.

Note that since the output signal of the bandpass filter 19 is a signal that oscillates only for a certain period after the clock run-in signal, the phase comparators 21 and 22 detect the phase difference during the period of the clock run-in signal, and then It is necessary to sample and hold the character data signal during the period.

Here, the phase of the gate signal output period of the gate pulse generation circuit 15 is compared, and then held.

The phase shift circuit 23 outputs phase difference detection outputs a, b', C',
d) 6.73. Oscillation output a of four phases of MHz.

It consists of circuits that control the levels of b, c, and d, respectively, and a circuit that vector-synthesizes each controlled oscillation output.9 Its operation is as follows. Now, assuming 5.73 MHz
The phase of the output of the bandpass filter 19 is 5.73
Assuming that there is a 45° phase difference with the output d of the MHz oscillation circuit 19, d' and ci have the same voltage, and a positive voltage with respect to the reference level is obtained, and b' and d' are also the same voltage. ,
A negative voltage is obtained with respect to the reference level. With these voltages, for example, X represents a, b' represents b, C' represents C, and d' represents d.
If f and y oscillations are controlled once and the controlled outputs are vector-synthesized, an output signal with a phase shift of 5 degrees from A to B, which is exactly in phase with the output of the bandpass filter 19, is obtained. It will be done.

Next, if this is shaped by the pulse shaping circuit 24, a sampling clock whose phase is synchronized with the clock run-in signal of the character data signal is obtained from the output terminal 68.

FIG. 4 shows a specific circuit example of the phase shift circuit 23. Here, 25, 26, 27.28 are oscillation output signals a, b, c from the 5.7.3 MHz oscillation circuit 20.

At the input terminals of d, 29, 30, 31.32 are comparison output signals a', b', c from the phase comparator 21.22.
'.

This is the input terminal of d. 32 and 33 are current sources that flow the same current, and are made by one current source or a dicurrent mirror circuit. Also, transistors 34°, 35.3, et al., 37.
38.39 and resistance 4Q.

41. 42, 43, 44. 46 are one double-balanced differential amplifier, transistors 46, 47° 4s, 4
9,5o, sl:%'' and resistance 52,53.

54,55,56.5γ constitutes another differential amplifier. Here, the resistance 4C1, 41°42.43,
52, 53, 54.55 are resistors with the same resistance value p,
Resistors 44, 45, 56 and 57 have the same resistance value. Resistor 58 is transistor 35.37, 47.49
59 is a power supply.

Here, input terminals 25, 26, 27, and 28 each have 5
．． The oscillation outputs of the 73MH2 oscillation circuit 2ooa+b+c+d are input, and the input terminals 29, 30° 31.32 are a', b', and from the phase comparison circuit 21.22, respectively.
When the phase difference detection outputs of c' and d' are connected, the change 11 in the collector current of the transistor 36 in Fig. 4 is in the same phase as its own oscillation output, and its level is controlled by the phase difference detection output of a'. be done. Similarly, the change 2 in the collector current of the transistor 37 is in the same phase as the oscillation output of b, and its level is controlled by the phase difference detection output of b', and the change 13 in the collector current of the transistor 4 is the oscillation output of C. The change 14 in the collector current of the transistor 49 is in the same phase as the oscillation output of d, and its level is controlled by the phase difference detection output of d'. Ru. When these currents are completely combined and flown through the load resistor 581, the outputs of each phase are vector-combined, and the operation as the above-mentioned phase shifter can be realized.

In addition, in the above signal connection, the 0° oscillation output a is controlled by the 00 axis phase difference detection output a', and the 0° oscillation output a is
The 90° oscillation output C is controlled by the 90° axis phase difference detection output C' (the 90° oscillation output C is controlled by the 90° axis phase difference detection output C'), and the 2700 oscillation output d is
Since it is controlled by the phase difference detection output d' of the 700-axis axis, the output phase of the phase shifter 23 becomes It when it matches the phase of the output signal of the 5.73 MHz bandpass filter 19.

Incidentally, from the viewpoint of margin, it is desirable to perform the sampling point of the character data signal at a part of the center of the data signal. However, when extracting the multiplexed signal and regenerating and reading the data and sampling clock, phase alignment is generally required because there is a difference in the configuration of the data slice circuit and the sampling clock regeneration circuit. In the method using the phase shift circuit 23, the oscillation outputs (a, b, c, d) with the above four phases and the four
The output phase of the phase shift circuit 23 can be shifted in 9o0 steps by combining the three phase difference detection outputs (a, 6.c, ci'). That is, the above a-a'.

If the combination ob, c-c, dd' is the first combination, then a-C', b-d',
The second combination of C-b', d-a' has a phase lead of 90° relative to the first combination, and a-b, b-, a',
The third combination of c-d', d-c' is 18o with respect to the first combination.

The phase advances to a-d', b-c', c-a', d-;
The fourth combination is 2700 phases ahead of the first combination. Therefore, by selecting these combinations, the slice data and the sampling clock can be phase-aligned in 90° steps without using a separate phase shift circuit.

Furthermore, if detailed phasing is required, 5.73M
Hz band pass band pass filter ~19l, W point 6.
You can make even more detailed adjustments by shifting the Q from 73MHz. For example, if a 6,73 MHz bandpass filter, -19, is singly tuned, then
If the amplitude of 5.73 MHz deviates from center tuning within -3 dB, a phase shift of ±45° is possible.
By combining with 9o0 step phasing, 3
Phasing over 600 is possible.

In particular, if the data slice circuit and the sampling clock regeneration circuit are constructed using integrated circuit elements, and the two circuits are formed on the same chip, variations in the relative phases of the slice data and the sampling clock can be suppressed to a minimum, making it easier to achieve phase alignment. A separate phase shift circuit for
It is possible to reduce costs and eliminate phase adjustment at the same time.

In addition, in Figure 3, four 5.73 MHz oscillation outputs, 0°, 90°, and 1800.2700, are used, but Oo, 1800.90°, and 2o0 are simply opposite in polarity. Therefore, it is not impossible to say that oo and 900 cabinets can be similarly realized using the 1800 and 2700 outputs and phase comparison outputs.

The 5.7 s MHz oscillation circuit 2o shown in Fig. 3, which has four outputs with a phase shift of 9 oO, can also be used with a known oscillation circuit used in the reproduction of chroma signals of television receivers as shown in Fig. 5. By ○ that can be achieved, 60 is 5.73
A MHz crystal oscillator 61 is a capacitor connected in series with the crystal oscillator.

The circuit formed by the resistor 62 and capacitor 63 is 5-73
It has a cutoff point at MHz, thus 5.73M
Delay the phase of the H2 signal by 45°. Therefore, the phase relationship between e and f in FIG. 5 is as shown in the vector diagram in FIG. 6. If the transistors 64, 65, 66, and 7 are transistors with the same characteristics and the bias conditions are determined so that the DC voltages of their bases are equal, then the transistor 6
The phase relationship among the collector output a of transistor 7, collector output J of transistor 6, collector output c of transistor 65, and collector output d of transistor 4 can be expressed in a vector diagram as shown in FIG. 6 based on the operating principle of a differential amplifier. .

In addition, by using a crystal oscillator like this circuit, the frequency deviation can be suppressed to 164 or less without adjustment, so 1
One phase error due to frequency shift in the horizontal period is very small, and sufficient accuracy as a sampling clock can be obtained for reading data in one horizontal period without configuring a closed loop such as PL'L as an oscillation circuit.

Effects of the Invention As described above, the sampling clock recovery circuit of the present invention provides the following effects.

(1) Unlike conventional circuits, there is no need for a complicated configuration in which separate sampling clock generation circuits are switched for the data portion up to and after the 7-raming code, and a sampling clock regeneration circuit can be realized with a simple configuration.

(2) The first . By using the second two filters to remove noise components, a sampling clock with less jitter, that is, fewer reception errors, can be regenerated even if the S/N of the received signal is degraded.

(3) Since there is no need to perform digital processing such as frequency division from a high oscillation frequency, the circuits operate using analog processing at the data transmission rate even at the highest frequency, and these circuits do not emit interference waves to the outside. Few. This also makes it possible to reduce reception errors.

(4) Generally, when sampling data at proper timing using a data slice circuit and a sampling clock recovery circuit, it is necessary to align the phases of the slice data and the sampling clock, and a phase shift circuit for the sampling clock is required. However, it can be omitted in the configuration of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram of a character data signal superimposed on a television signal, FIG. 2 is a block diagram showing the overall configuration of an example of a teletext receiver, and FIG. 3 is a sampling clock in an embodiment of the present invention. A block diagram showing the configuration of the regeneration circuit, Fig. 4 is a specific circuit diagram of an example of a phase shift circuit used in the sampling clock regeneration circuit, and Fig. 5 is a block diagram showing an example of a phase shift circuit used in the sampling clock regeneration circuit. A specific circuit diagram of an example of an oscillation circuit, and FIG. 6 is a vector diagram of output signals of each part thereof. 1...Antenna, 2...Video receiving section, 4
... Character data decoder section, 8 ... Data slice circuit, 9 ... Sampling clock regeneration circuit, 10 ... Synchronization separation circuit, 11 ...
...FC detection circuit, 12... Character signal processing circuit, 13... Input terminal for video signal superimposed with character data, 14... Input terminal for horizontal synchronizing pulse, 1
5 ・Gate pulse generation circuit, 16- ・Gate circuit, 17---2.86 MHz band pass filter,
18...2 multiplier circuit, 19...5.73 MHz
Band pass filter, 21゜22...phase comparison circuit, 23...phase shift circuit, 24-pulse shaping circuit,
68...Sampling clock output terminal. Name of agent: Patent attorney Toshio Nakao Haga 1 person No. 4
Figure 5 Figure 6

Claims (2)

[Claims] (1) a gate circuit that allows the vicinity of a clock run-in signal of a teletext broadcasting signal to pass; a first bandpass filter that is connected to the gate circuit and has a tuning frequency that is the repetition frequency of the clock run-in signal; a doubling circuit that doubles the output signal of the filter; and a doubling circuit that doubles the output signal of the filter;
9. a second bandpass filter whose tuning frequency is approximately twice the repetition frequency of the clock run-in signal; an oscillation circuit that oscillates at a frequency twice the repetition frequency of the clock run-in signal; an output signal of the oscillation circuit; a phase comparison circuit that detects a phase difference with the output signal of the second bandpass filter; and a phase shift circuit that receives the output signal of the oscillation circuit and whose phase is controlled by the output of the phase comparison circuit. A sampling clock reproducing circuit comprising: a sampling clock reproducing circuit, comprising: reproducing a sampling clock from an output signal of the phase shift circuit. (2) The oscillation circuit is configured to generate two or more output signals with mutually orthogonal phases as its output signals, and the phase comparator circuit generates the oscillation output signals of each phase and the second bandpass filter. The phase shift circuit compares the phase with the output signal and outputs two or more phase comparison output signals corresponding to each oscillation output signal phase, and the phase shift circuit outputs the two or more orthogonal oscillation output signals and the phase comparison output signal. 2. The sampling clock regeneration circuit according to claim 1, wherein the phase of the output signal can be changed by a combination of the following.